JP2018101938A - Imaging device control device, control method of the same, control program, and imaging apparatus - Google Patents

Abstract

PROBLEM TO BE SOLVED: To prevent deterioration of image quality by reducing influence of random noise without increasing reading time of an image signal.SOLUTION: An imaging device 102 has a plurality of pixels arranged in a two-dimensional matrix and has a first pixel area for receiving light and a second pixel area shielded from light. A column circuit control unit 110 performs AD conversion on a first pixel signal obtained by performing read control on the pixels in the first pixel area by the column circuit, and, when performing AD conversion on a second pixel signal obtained by performing read control on the pixels in the second pixel area, while performing the AD conversion on the first pixel signal once and performs AD conversion on the second pixel signal a plurality of times. then, adds AD conversion results obtained by multiple AD conversion and averages them.SELECTED DRAWING: Figure 5

Description

  The present invention relates to an image sensor control apparatus, a control method thereof, a control program, and an image pickup apparatus, and more particularly to an image sensor control apparatus that performs correlated double sampling.

  In general, a CMOS image sensor used in an imaging device such as a digital camera has a light-shielding pixel (OB pixel) serving as a reference for a black level and an aperture pixel that outputs an image signal corresponding to incident light. The OB pixel is used as a correction value acquisition region for correcting the output level of the aperture pixel based on the black level.

  However, when the OB pixel is affected by so-called random noise and an error in the correction value obtained by the OB pixel becomes large, when the output of the aperture pixel is corrected based on the output of the OB pixel, pattern noise occurs and the image quality is reduced. May deteriorate.

  As an imaging apparatus that reduces the influence of random noise as described above, for example, an imaging apparatus described in Patent Document 1 is known.

  In the CMOS image sensor used in the imaging device defined in Patent Document 1, a column processing unit having an AD conversion unit for each column is provided. The column processing unit AD samples the reset level and the signal level of the pixel a plurality of times, and averages the results. As a result, random noise generated in the pixel and the AD conversion unit is reduced.

JP 2012-4727 A

  However, in the imaging apparatus described in Patent Document 1, since the reset level and the signal level are AD sampled a plurality of times, the readout time of the image signal inevitably increases. As a result, the time until photographing is completed increases. On the other hand, if sampling is performed in order to reduce the readout time, the noise reduction effect by sampling cannot be obtained sufficiently.

  SUMMARY OF THE INVENTION An object of the present invention is to provide an image sensor control device, a control method thereof, a control program, and an image pickup device in which the image signal readout time does not increase and the influence of random noise is reduced and the image quality does not deteriorate. Is to provide.

  In order to achieve the above object, an image sensor control apparatus according to the present invention includes a first pixel region in which a plurality of pixels are arranged in a two-dimensional matrix, and receives light, and a second pixel region that is shielded from light. An image sensor control apparatus that performs readout control of the pixel with respect to an image sensor having the first pixel signal obtained by performing readout control with respect to a pixel in the first pixel region, and performs second conversion on the second pixel signal. A reading unit that performs AD conversion on the second pixel signal obtained by performing reading control for the pixels in the pixel region, and a period in which the AD conversion is performed once for the first pixel signal by controlling the reading unit. And a control means for performing AD conversion on the second pixel signal a plurality of times, and an arithmetic means for adding and averaging the AD conversion results obtained by the plurality of AD conversions. To.

  According to the present invention, it is possible to prevent an increase in the readout time of an image signal, reduce the influence of random noise, and reduce image quality degradation.

It is a block diagram which shows the structure about an example of the imaging device with which the imaging device control apparatus which concerns on the 1st Embodiment of this invention is used. It is a figure which shows an example of the structure about the pixel shown in FIG. FIG. 3 is a timing chart for explaining a reading operation of the pixel shown in FIG. 2. It is a figure which shows an example of the structure about the column circuit shown in FIG. FIG. 5 is a diagram for explaining an operation according to signal readout of an OB pixel provided in an OB region in the column circuit shown in FIG. 4. FIG. 5 is a diagram for explaining an operation according to signal readout of an aperture pixel provided in an aperture pixel region in the column circuit shown in FIG. 4. It is a figure which shows the example about the structure of the pixel in the image pick-up element used with the camera which concerns on the 2nd Embodiment of this invention. FIG. 8 is a timing chart for explaining a reading operation of the pixel shown in FIG. 7. It is a figure for demonstrating the operation | movement according to the signal reading of the OB pixel with which the OB area | region was equipped in the column circuit used with the camera which concerns on the 2nd Embodiment of this invention. It is a figure for demonstrating the operation | movement according to the signal reading of the aperture pixel provided in the aperture pixel area | region in the column circuit used with the camera which concerns on the 2nd Embodiment of this invention.

  Hereinafter, an example of an image sensor control apparatus according to an embodiment of the present invention will be described with reference to the drawings.

[First Embodiment]
FIG. 1 is a block diagram illustrating a configuration of an example of an imaging apparatus in which the imaging element control apparatus according to the first embodiment of the present invention is used.

  The illustrated imaging apparatus is, for example, a digital camera (hereinafter simply referred to as a camera) 100, and includes a pixel unit 101 in which a plurality of pixels 104 are arranged in a two-dimensional matrix. The pixel 104 includes an OB pixel 105 that is optically shielded and serves as a black level reference pixel, and an aperture pixel 106 that receives incident light and outputs a signal (pixel signal) corresponding to the incident light. The pixel unit 101 includes an OB region 102 and an aperture pixel region 103. In the OB region 102, OB pixels 105 are arranged in a two-dimensional matrix. In the aperture pixel region 103, the aperture pixels 106 are arranged in a two-dimensional matrix.

  The camera 100 further includes a vertical scanning circuit 108, a vertical signal line 107, a column circuit 109, and a column circuit control unit 110. The vertical scanning circuit 108 selects and sequentially scans the pixels 104 that output pixel signals, and outputs the pixel signals to the vertical signal line 107. The column circuit 109 processes the pixel signal output to the vertical signal line 107 for each column under the control of the column circuit control unit 110.

  The camera 100 also includes a horizontal scanning circuit 111, a timing control unit 112, and an output unit 113. The horizontal scanning circuit 111 sequentially reads out pixel signals processed by the column circuit 109 for each column. The timing control unit 112 controls the operation timing of the vertical scanning circuit 108 and the horizontal scanning circuit 111 and outputs an image signal from the output unit 113.

  As will be described later, the column circuit control unit 110 outputs the first switch signal P_SW1, the second switch signal P_SW2, the third switch signal P_SW3, the fourth switch signal P_SW4, and the fifth switch signal P_SW5 to the column circuit. Output to 109. Further, the column circuit control unit 110 outputs the ramp signal Vramp, the reference voltage Vref, the count reset signal P_rst_count, and the clock CLK to the column circuit 109.

  FIG. 2 is a diagram showing an example of the configuration of the pixel shown in FIG.

  The pixel 104 includes a photodiode (PD: photoelectric conversion unit) 201, a floating diffusion layer 202, a pixel transistor 203, a selection transistor 204, a transfer transistor 205, and a reset transistor 206. The PD 201 outputs charges corresponding to incident light by photoelectric conversion. The transfer transistor 205 transfers the charge of the PD 201 to the floating diffusion layer 202. The floating diffusion layer 202 converts charges into a voltage. The pixel transistor 203 outputs a voltage signal corresponding to the voltage of the floating diffusion layer 202 as a pixel signal. The selection transistor 204 selectively connects the pixel transistor 203 to the vertical signal line 107. The reset transistor 106 is a transistor for resetting the electric charge of the floating diffusion layer 202.

  A selection signal SEL, a transfer signal TX, and a reset signal RES are sent from the vertical scanning circuit 108 to the selection transistor 204, the transfer transistor 205, and the reset transistor 206, respectively. Here, the pixel signal output from the pixel transistor 203 to the vertical signal line 107 is Vpix.

  FIG. 3 is a timing chart for explaining a reading operation of the pixel shown in FIG.

  In the period T300, the vertical scanning circuit 108 sets the transfer signal TX and the reset signal RES to a high level (H level) under the control of the timing control unit 112. As a result, the transfer transistor 205 and the reset transistor 206 are turned on, and the PD 201 and the floating diffusion layer 202 are reset to a potential corresponding to the power supply voltage VDD.

  In the T301 period, light is incident on the pixel portion 101 and charge is accumulated. Here, under the control of the timing control unit 112, the vertical scanning circuit 108 sets the selection signal SEL to the H level. As a result, the selection transistor 204 is turned on, and the reset level is output as the pixel signal Vpix via the vertical output line 107. The pixel signal Vpix at this time is an N signal.

  In the period T302, the vertical scanning circuit 108 sets the transfer signal TX to the H level. As a result, the transfer transistor 205 is turned on, and the charge accumulated in the PD 201 is transferred to the floating diffusion layer 202. Then, the pixel signal Vpix obtained by adding the reset level held in the floating diffusion layer 202 to the charge accumulated in the PD 201 is output to the vertical signal line 107 via the pixel transistor 203 and the selection transistor 204. The pixel signal Vpix at this time is an S signal.

  FIG. 4 is a diagram showing an example of the configuration of the column circuit shown in FIG.

  The column circuit 109 includes a comparator 402, a counter 403, an AD conversion unit 404 including an OR circuit OG1, and an amplifier 401. Further, the column circuit 109 includes first to fifth switches SW1 to SW5, a clamp capacitor element Cclmp, and sample and hold capacitor elements C_Vpix1 and C_Vpix2. The first to fifth switches SW1 to SW5 are on / off controlled by the first switch signals P_SW1 to P_SW5, respectively.

  A pixel signal Vpix is input from the pixel unit 101 to the amplifier 401 via the vertical signal line 107. The amplifier 401 amplifies the pixel signal Vpix and outputs an amplified signal Vpix_amp. In accordance with the on / off control of the first to fourth switches SW1 to SW4, the sample hold capacitor elements C_Vpix1 and C_Vpix2 sample and hold the amplified signal Vpix_amp and output it as the sample hold signal Vpix_sh.

  The comparator 402 receives the sample hold signal Vpix_sh. Further, the ramp signal Vramp is input to the comparator 402 as the ramp signal Vcomp through the clamp capacitor element Cclmp in accordance with the on / off control of the fifth switch SW5. As illustrated, the sample hold signal Vpix_sh is input to one input terminal of the comparator 402, and the ramp signal Vcomp is input to the other input terminal. Then, the comparator 402 outputs the comparison result as a comparison result signal CMP to the OR circuit OG1.

  Further, the fifth switch signal P_SW5 is input to the OR circuit OG1, and the OR circuit OG1 outputs an OR signal obtained by ORing the comparison result signal CMP and the fifth switch signal P_SW5 to the counter 403. The counter 403 performs counting based on the clock CLK in a period in which the OR signal is at L level, that is, in a period in which the comparison result signal CMP and the fifth switch signal P_SW5 are at L level. Then, the counter 403 outputs the count result as a count signal.

  The counter 403 resets the count result in response to the count reset signal P_rst_count.

  FIG. 5 is a diagram for explaining an operation according to signal reading of the OB pixel provided in the OB region in the column circuit shown in FIG.

  In the illustrated example, since the signal level of the OB pixel 105 is small, AD conversion is performed a plurality of times. When the first to fifth switch signals P_SW1 to P_SW5 are at the H level, the first to fifth switches SW1 to SW5 are turned on, and when the first to fifth switch signals P_SW1 to P_SW5 are at the L level. The first to fifth switches SW1 to SW5 are turned off. Although omitted in FIG. 5, the ramp signal Vramp increases monotonously in the periods T506 to T528.

  In the period T500, the column circuit control unit 110 resets the counter 403 by setting the counter reset signal P_rst_count to the H level. Further, the column circuit control unit 110 sets the fifth switch signal P_SW5 to the H level and turns on the fifth switch SW5. As a result, the ramp signal Vcomp is clamped to the reference voltage Vref. Further, when the fifth switch signal P_SW5 becomes H level, the output of the OR circuit OG1 becomes H level, and the counter 403 stops counting operation.

  Subsequently, in a period T501, an N signal is output from the pixel row selected by the vertical scanning circuit 108. As a result, the amplified signal Vpix_amp changes. Further, the column circuit control unit 110 sets the first switch signal P_SW1 to the H level and turns on the switch SW1. As a result, the amplified signal Vpix_amp is sampled and held by the sample and hold capacitive element C_Vpix1. Hereinafter, the amplified signal Vpix_amp is referred to as an AMP_N signal.

  In the period T502, the column circuit control unit 110 sets the second switch signal P_SW2 to the H level and turns on the switch SW2. As a result, the AMP_N signal sampled and held in the sample and hold capacitor C_Vpix1 is input to the comparator 402. The comparator 402 compares the ramp signal Vcomp and the AMP_N signal and outputs a comparison result signal CMP.

  Note that in the period T502, since the potential (voltage) of the ramp signal Vcomp is lower than the potential of the AMP_N signal, the comparison result signal CMP is at the L level.

  Further, the column circuit control unit 110 sets the fifth switch signal P_SW5 to the L level. Thereby, the OR circuit OG1 outputs an OR signal of L level in response to the comparison result signal CMP and the fifth switch signal P_SW5. As a result, in the period T502, the counter 403 starts a count operation at the timing when the fifth switch signal P_SW5 becomes L level.

  In the period T503, since the potential of the ramp signal Vcomp becomes higher than the potential of the AMP_N signal, the comparison result signal CMP that is the output of the comparator 402 is at the H level. Therefore, since the OR circuit OG1 outputs an OR signal at the H level, the counter 403 stops the counting operation.

  At this time, the counter 403 holds the count value in order to add and output the result of AD conversion a plurality of times, as will be described later.

  In the period T504, the column circuit control unit 110 sets the fifth switch signal P_SW5 to the L level and turns on the fifth switch SW5. As a result, the ramp signal Vramp is reset to the reference potential Vref and clamped to the reference voltage Vref. Further, since the fifth switch signal P_SW5 is at the H level, the OR circuit OG1 maintains the OR signal at the H level. As a result, the counter 403 maintains a stopped state.

  In the period T505, the vertical scanning circuit 108 sets the transfer signal TX to H level to turn on the transfer transistor 205. As a result, the S signal is output to the amplifier 401 via the vertical signal line 107. Further, the column circuit control unit 110 sets the third switch signal P_SW3 to the H level and turns on the third switch SW3. As a result, the S signal is sampled and held by the sample and hold capacitive element C_Vpix2, and the amplified signal Vpix_amp is output as the AMP_S signal.

  In periods T506 to T507, operations similar to those in the above-described periods T502 to T503 are performed. Note that here, the counter 403 starts and stops counting from the count value held in the period T503, and as a result, the AD conversion result is added.

  In the period T508, the column circuit control unit 110 sets the fifth switch signal P_SW5 to the H level and turns on the switch SW5. As a result, the ramp signal Vcomp is clamped to the reference voltage Vref as described above.

  In the periods T509 to T516, operations similar to those in the periods T506 to T508 are repeated. Note that the count value held by the counter 403 in the period T516 is obtained by adding the result of AD conversion of the AMP_N signal a plurality of times, and is divided by the number of times of AD conversion by the arithmetic circuit (not shown). Average.

  In the period T517, the column circuit control unit 110 sets the counter reset signal P_rst_count to the H level and resets the count value of the counter 403 to the initial value. Further, the column circuit control unit 110 sets the fourth switch signal P_SW4 to the H level and turns on the switch SW4. As a result, the AMP_S signal sampled and held in the sample and hold capacitor C_Vpix2 is input to the comparator 402.

  In the periods T518 to T528, operations similar to those in the periods T506 to T516 are performed on the AMP_S signal. Note that the count value held by the counter 403 in the period T528 is obtained by adding the results of AD conversion of the AMP_S signal a plurality of times, and dividing the addition result by the number of times of AD conversion by the arithmetic circuit and averaging the result.

  In the period T529, the column circuit control unit 110 sets the counter reset signal P_rst_count to the H level and resets the count value of the counter 403 to the initial value. In a period T529, the operation of reading the selected row is completed, the next row is selected by the vertical scanning circuit 108, and the same operation is performed.

  FIG. 6 is a diagram for explaining an operation according to signal readout of the aperture pixel provided in the aperture pixel region in the column circuit shown in FIG. Although omitted in FIG. 6, the ramp signal Vramp increases monotonously in the periods T606 to T607.

  In the periods T600 to 603, operations similar to those in the periods T500 to T503 described in FIG. 5 are performed. Note that in the period T603, the count value held by the counter 403 is a digital signal corresponding to the AMP_N signal.

  In the period T604, the column circuit control unit 110 sets the fifth switch signal P_SW5 to the H level and turns on the fifth switch SW5. As a result, the ramp signal Vramp is reset and clamped to the reference voltage Vref. Further, since the fifth switch signal P_SW5 is at the H level, the OR signal that is the output of the OR circuit OG1 is maintained at the H level, and the counter 403 is in a stopped state.

  In the period T605, an operation similar to that in the period T505 described in FIG. 5 is performed. In the period T606, the operation performed on the AMP_N signal in the period T602 is performed on the AMP_S signal. In the period T607, an operation similar to that in the period T603 is performed. At this time, the count value held by the counter 403 becomes a digital signal corresponding to the AMP_S signal.

  In the period T610, the column circuit control unit 110 sets the counter reset signal P_rst_count to the H level and resets the count value of the counter 403 to the initial value. In a period T610, the operation of reading the selected row is completed, the next row is selected by the vertical scanning circuit 108, and the same operation is performed. In FIG. 6, periods T500 to T529 are similar to the periods T500 to T529 shown in FIG.

  As is clear from the above description, AD conversion is performed a plurality of times for the N signal in the OB region 102 at the timing when AD conversion is started for the S signal in the aperture pixel region 103.

  Here, the noise reduction effect and the determination of the number of AD conversions in the above-described camera will be described.

  In correlated double sampling used in the illustrated camera, the noise reduction effect of multiple sampling is given by the following equation (1) by error propagation.

  In Expression (1), σmulti indicates a noise level when sampling is performed a plurality of times, and σsingle indicates a noise level when sampling is not performed a plurality of times. Further, l and m indicate the number of samplings of the AMP_N signal and the AMP_S signal, respectively.

  From the equation (1), under the condition that the total number of sampling times of the AMP_N signal and the AMP_S signal is constant, the effect of reducing random noise by sampling a plurality of times becomes maximum when the sampling times l and m are equal.

  On the other hand, when one of the sampling counts l and m is 1 under the same conditions, the random noise reduction effect by sampling a plurality of times is minimized.

  For example, the total number of sampling times of the AMP_N signal and the AMP_S signal in the OB area 102 is nine. In this case, the number of samplings of the AMP_N signal is set to 5 and the number of samplings of the AMP_S signal is set to 4 so that the noise reduction effect is maximized when the sampling is performed a plurality of times in the correlated double sampling. The number of times of sampling is an example, and the present invention is not limited to this example.

  Furthermore, the signal level of the S signal in the OB region 102 may be increased due to a change in imaging conditions (for example, during high sensitivity, long-second exposure, or high temperature environment) despite being shielded from light. In such a case, the total number of AD conversions of the AMP_N signal and the AMP_S signal may be changed by changing the dynamic range in AD conversion.

  Thus, in the first embodiment of the present invention, AD conversion is performed for the second pixel signal obtained from the OB region while AD conversion is performed once for the first pixel signal obtained from the aperture pixel region. Let the conversion occur multiple times. Then, the AD conversion results of the plurality of AD conversions are added and averaged. As a result, it is possible to reduce the occurrence of pattern noise due to random noise as a result of reducing random noise in the OB region while preventing an increase in the time required to read an image signal.

[Second Embodiment]
Next, an example of a camera according to the second embodiment of the present invention will be described. The configuration of the camera according to the second embodiment is the same as that of the camera shown in FIG.

  FIG. 7 is a diagram illustrating an example of the configuration of the pixels in the image sensor used in the camera according to the second embodiment of the present invention.

  A pixel 104 illustrated in FIG. 7 has a plurality of PDs 701 and 702 corresponding to pupil division, unlike the pixel 104 described with reference to FIG. The transfer transistors 706 and 707 transfer the charges of the PDs 701 and 702 to the floating diffusion layer 703, respectively. The pixel transistor 704 outputs a voltage signal corresponding to the voltage of the floating diffusion layer 703 as a pixel signal. The selection transistor 705 selectively connects the pixel transistor 704 to the vertical signal line 107. The reset transistor 708 is a transistor for resetting the electric charge of the floating diffusion layer 703.

  A selection signal SEL, transfer signals TX_A and TX_B, and a reset signal RES are sent from the vertical scanning circuit 108 to the selection transistor 705, transfer transistors 706 and 707, and reset transistor 708, respectively.

  FIG. 8 is a timing chart for explaining the readout operation of the pixel shown in FIG.

  In the period T800, the vertical scanning circuit 108 sets the transfer signals TX_A and TX_B and the reset signal RE to the H level, and turns on the transfer transistors 706 and 707 and the reset transistor 708. As a result, the PDs 701 and 702 and the floating diffusion layer 703 are reset to a potential corresponding to the power supply voltage VDD.

  In a period T801, light enters the pixel portion 101, and charge accumulation in the PDs 701 and 702 starts. The vertical scanning circuit 108 sets the selection signal SEL to H level to turn on the selection transistor 705. As a result, the reset level is output to the vertical output line 107 as the pixel signal Vpix. The pixel signal Vpix at this time is an N signal.

  In the period T802, the vertical scanning circuit 108 sets the transfer signal TX_A to the H level and turns on the transfer transistor A706. As a result, charges accumulated in the PD 701 are transferred to the floating diffusion layer 703. Then, the pixel signal Vpix obtained by adding the reset level held in the floating diffusion layer 703 to the charge accumulated in the PD 701 is output to the vertical signal line 107 via the pixel transistor 704 and the selection transistor 705. The pixel signal Vpix at this time is an S_A signal.

  In the period T803, the vertical scanning circuit 108 sets the transfer signals TX_A and TX_B to the H level to turn on the transfer transistors 706 and 707. As a result, the charges accumulated in the PDs 701 and 702 are transferred to the floating diffusion layer 703. Then, a pixel signal Vpix obtained by adding the reset level held in the floating diffusion layer 703 to the charges accumulated in the PDs 701 and 702 is output to the vertical signal line 107 via the pixel transistor 704 and the selection transistor 705. The pixel signal Vpix at this time is an S_AB signal.

  FIG. 9 is a diagram for explaining an operation according to signal readout of an OB pixel provided in an OB region in a column circuit used in a camera according to the second embodiment of the present invention. The configuration of the column circuit used in the camera according to the second embodiment is the same as that of the column circuit shown in FIG.

  In the illustrated example, since the signal level of the OB pixel 105 is small, AD conversion is performed a plurality of times. Although omitted in FIG. 9, the ramp signal Vramp monotonously increases in the periods T906 to T917 and the periods T920 to 930.

  In the period T900, the column circuit control unit 110 resets the counter 403 by setting the counter reset signal P_rst_count to the H level. Further, the column circuit control unit 110 sets the fifth switch signal P_SW5 to the H level and turns on the switch SW5. As a result, the ramp signal Vcomp is clamped to the reference voltage Vref. When the fifth switch signal P_SW5 becomes H level, the OR signal that is the output of the OR circuit OG1 becomes H level, and the counter 403 stops counting operation.

  In the periods T901 to T904, operations similar to those in the periods T501 to T504 described in FIG. 5 are performed.

  In the period T905, the vertical scanning circuit 108 sets the transfer signal TX_A to the H level and turns on the transfer transistor 706. As a result, the S_A signal is output to the amplifier 401 via the vertical signal line 107 as described above. Further, the column circuit control unit 110 sets the third switch signal P_SW3 to the H level and turns on the third switch SW3. As a result, the S_A signal is sampled and held in the sample and hold capacitive element C_Vpix2. Here, the amplified signal Vpix_amp, which is the output of the amplifier 401, is assumed to be an AMP_S_A signal.

  In the periods T906 to T909, operations similar to those in the periods T506 to T509 described in FIG. 5 are performed. In the period T910, an operation similar to that in the period T907 is performed. At this time, the count value held by the counter 403 is obtained by adding the results of AD conversion of the AMP_N signal a plurality of times, and is divided and averaged by the number of times of the AD conversion by the arithmetic circuit.

  In the period T911, the column circuit control unit 110 sets the fifth switch signal P_SW5 to the H level and turns on the fifth switch SW5. As a result, the ramp signal Vcomp is clamped at the reference voltage Vref. Then, the column circuit control unit 110 sets the counter reset signal P_rst_count to the H level and resets the count value of the counter 403 to the initial value.

  In the period T912, the column circuit control unit 110 sets the fourth switch signal P_SW4 to the H level and turns on the fourth switch SW4. As a result, the comparator 402 receives the AMP_S_A signal sampled and held by the sample and hold capacitor element C_Vpix2.

  In the periods T913 to T916, operations similar to those in the periods T906 to T909 are performed on the AMP_S_A signal. In the period T917, the operation similar to that in the period T910 is performed on the AMP_S_A signal. At this time, the count value held by the counter 403 is obtained by adding the results of AD conversion of the AMP_S_A signal a plurality of times, and is averaged by dividing the addition result by the number of times of AD conversion by the arithmetic circuit. In the period T918, an operation similar to that in the period T911 is performed.

  In the period T919, the column circuit control unit 110 sets the transfer signals TX_A and TX_B to the H level and turns on the transfer transistors 706 and 707. As a result, the S_AB signal is output to the amplifier 401 via the vertical signal line 107. Further, the column circuit control unit 110 turns on the first switch SW1 and the third switch SW3, and samples and holds the S_AB signal with the sample hold capacitor C_Vpix1. Here, the amplified signal Vpix_amp, which is the output of the amplifier 401, is an AMP_S_AB signal.

  In the periods T920 to T931, operations similar to those in the periods T518 to T529 described with reference to FIG. 5 are performed on the AMP_S_AB signal. In a period T931, the operation of reading the selected row is completed, the next row is selected by the vertical scanning circuit 108, and the same operation is performed.

  FIG. 10 is a diagram for explaining an operation according to signal readout of the aperture pixel provided in the aperture pixel region in the column circuit used in the camera according to the second embodiment of the present invention. Although omitted in FIG. 10, the ramp signal Vramp monotonously increases in the periods T1006 to T1017 and the periods T1020 to T1030.

  In the periods T1001 to T1004, operations similar to those in the periods T601 to T604 described in FIG. 6 are performed.

  In the period T1005, the column circuit control unit 110 sets the transfer signal TX_A to the H level to turn on the transfer transistor 706. As a result, the S_A signal is output to the amplifier 401 via the vertical signal line 107. Further, the column circuit control unit 110 sets the third switch signal P_SW3 to the H level and turns on the third switch SW3. As a result, the S_A signal is sampled and held by the sample and hold capacitive element C_Vpix2. Note that the amplified signal Vpix_amp, which is the output of the amplifier 401, is an AMP_S_A signal.

  In the periods T1006 to T1007, the operation performed on the AMP_N signal in the period T1002 is performed on the AMP_S_A signal. In the periods T1008 to T1016, the same operation as that in the period T1003 is performed, and in the periods T1017 and T1018, the same operation as that in the period T1004 is performed. In the period T1019, the same operation as that in the period T919 described with reference to FIG. 9 is performed.

  In the periods T1020 to T1022, operations similar to those in the periods T1006 to 1007 are performed on the AMP_S_AB signal. In the periods T1023 to T1030, operations similar to those in the periods T1008 to T1015 are performed.

  In the period T1031, the column circuit control unit 110 sets the counter reset signal P_rst_count to the H level and resets the count value of the counter 403 to the initial value. In a period T1031, the operation of one row selected in the pixel portion is completed, the next row is selected by the vertical scanning circuit 108, and the same operation is performed.

  Thus, in the second embodiment of the present invention, AD conversion is performed on the N signal in the OB region 102 in the period T1006 when AD conversion is started for the S_A signal in the opening region 103. The S_AB signal in the OB area 102 is AD-converted between the S_A signal in the opening area 103 and the same period.

  In the second embodiment, for example, the AMP_N signal is sampled three times in the OB region, the AMP_S_A signal is sampled twice, and the AMP_S_AB signal is sampled four times. Note that the number of times of sampling is an example, and the present invention is not limited to this example.

  Furthermore, as in the first embodiment, the signal level of the S signal in the OB region 102 may be high despite being shielded from light by a change in imaging conditions or the like. In such a case, the total AD conversion count of the AMP_N signal, the AMP_S_A signal, and the AMP_S_AB signal may be changed by changing the dynamic range in the AD conversion. Accordingly, AD conversion may be performed on the S_A signal in the OB region 102 during the period in which AD conversion is performed on the S_AB signal in the opening region 103.

  Thus, also in the second embodiment of the present invention, the occurrence of pattern noise due to random noise can be reduced as a result of the reduction of random noise in the OB region.

  Although not shown in FIG. 1, the camera includes an imaging lens and a processing device such as an image processing unit that performs predetermined image processing on an image signal read from the imaging element.

  As mentioned above, although this invention was demonstrated based on embodiment, this invention is not limited to these embodiment, Various forms of the range which does not deviate from the summary of this invention are also included in this invention. .

  For example, the function of the above-described embodiment may be used as a control method, and this control method may be executed by the image sensor control apparatus. Further, a program having the functions of the above-described embodiments may be used as a control program, and the control program may be executed by a computer included in the image sensor control apparatus. The control program is recorded on a computer-readable recording medium, for example.

[Other Embodiments]
The present invention supplies a program that realizes one or more functions of the above-described embodiments to a system or apparatus via a network or a storage medium, and one or more processors in the computer of the system or apparatus read and execute the program This process can be realized. It can also be realized by a circuit (for example, ASIC) that realizes one or more functions.

DESCRIPTION OF SYMBOLS 101 Pixel part 102 OB area | region 103 Open pixel area 108 Vertical scanning circuit 109 Column circuit 110 Column circuit control part 111 Horizontal scanning circuit 112 Timing control part 113 Output part

Claims (7)

An image sensor control apparatus that performs readout control of a pixel with respect to an image sensor having a plurality of pixels arranged in a two-dimensional matrix and having a first pixel area that receives light and a second pixel area that is shielded from light. And
AD conversion is performed on the first pixel signal obtained by performing readout control on the pixels in the first pixel region, and second pixel signal obtained by performing readout control on the pixels in the second pixel region. Reading means for performing AD conversion with respect to
Control means for performing AD conversion for the second pixel signal a plurality of times while controlling the reading means to perform AD conversion for the first pixel signal once;
Arithmetic means for averaging the AD conversion results of the plurality of AD conversions;
An image sensor control device comprising:   The control means performs AD conversion of the first pixel signal while the second pixel signal obtained when the pixel is reset by the readout means is AD converted. 2. The image sensor control device according to 1. Each of the plurality of pixels includes a plurality of photoelectric conversion units divided into pupils,
The control means outputs the first pixel signals obtained by the plurality of photoelectric conversion units to the reading means while the second pixel signals obtained when the pixels are reset are AD-converted. The image sensor control apparatus according to claim 1, wherein the image sensor is AD-converted. The first photoelectric conversion unit and the second photoelectric conversion unit as the plurality of photoelectric conversion units,
When the AD conversion is performed, the reading unit samples and holds the second pixel signal, and then reads the first pixel signal obtained by the first photoelectric conversion unit and the second photoelectric conversion unit. The image pickup device control apparatus according to claim 3, wherein the image pickup device control device performs sample hold and further samples and holds the second pixel signal obtained by the first photoelectric conversion unit. An imaging device having a plurality of pixels arranged in a two-dimensional matrix and having a first pixel region that receives light and a second pixel region that is shielded from light;
The image sensor control device according to any one of claims 1 to 4,
Image processing means for performing predetermined image processing on an image signal obtained by AD conversion by the reading means;
An imaging device comprising: Control of an image sensor control device that performs readout control of the pixel for an image sensor having a first pixel area that receives light and a light-shielded second pixel area, in which a plurality of pixels are arranged in a two-dimensional matrix. A method,
AD conversion is performed on the first pixel signal obtained by performing readout control on the pixels in the first pixel region, and second pixel signal obtained by performing readout control on the pixels in the second pixel region. A read step for performing AD conversion for
A control step in which AD conversion is performed a plurality of times for the second pixel signal while AD conversion is performed once for the first pixel signal in the reading step;
An arithmetic step of adding and averaging the AD conversion results of the plurality of AD conversions;
A control method characterized by comprising: A plurality of pixels are arranged in a two-dimensional matrix, and are used in an image sensor control device that performs readout control of the pixels for an image sensor having a first pixel area that receives light and a second pixel area that is shielded from light. A control program,
In the computer provided in the image sensor control device,
AD conversion is performed on the first pixel signal obtained by performing readout control on the pixels in the first pixel region, and second pixel signal obtained by performing readout control on the pixels in the second pixel region. A read step for performing AD conversion for
A control step in which AD conversion is performed a plurality of times for the second pixel signal while AD conversion is performed once for the first pixel signal in the reading step;
An arithmetic step of adding and averaging the AD conversion results of the plurality of AD conversions;
A control program characterized by causing

Images