JP6635700B2 - Imaging device, imaging system, and signal processing method - Google Patents

Description

  The present invention relates to an imaging device, an imaging system, and a signal processing method.

  When high-luminance light is incident on the photoelectric conversion unit of the imaging device, the charge generated by the photoelectric conversion unit may overflow into the floating diffusion (FD), and the value of the reference signal corresponding to a dark state may increase. Therefore, the value of the signal obtained from the difference between the image signal and the reference signal may be smaller than the value corresponding to the actual luminance. In such a case, a black sun phenomenon may occur in which an image in which a high-luminance portion looks low-luminance is actually output.

  Patent Literature 1 discloses a technique in which a comparison circuit that detects saturation of a photoelectric conversion unit based on the level of an analog signal read from a pixel is provided in each column circuit in order to suppress the black sun phenomenon described above. Have been.

U.S. Pat. No. 6,873,363

  In the technique described in Patent Literature 1, a comparison circuit for detecting saturation is provided in a column circuit of each column. Therefore, the circuit scale can be large.

  The present invention has been made in view of the above-described problems, and has as its object to suppress an increase in circuit scale while reducing the influence of the black sun phenomenon.

An imaging device according to an aspect of the present invention includes a plurality of pixels arranged in a plurality of rows and a plurality of columns, and each of the plurality of pixels generates an analog reference signal and an analog image signal; A plurality of gains can be set, and an amplifier that amplifies each of the analog reference signal and the analog image signal generated by each of the plurality of pixels with any of the plurality of gains, and a column of the pixel unit. Each is provided correspondingly, and each converts the analog reference signal amplified by the amplifier into a digital reference signal, and converts the analog image signal amplified by the amplifier into a digital image signal. A plurality of column circuit units, a reference signal output line to which the digital reference signal of each of the plurality of column circuit units is input, and the plurality of column circuit units An image signal output line, each said digital image signal is input, a threshold comparator for comparing the digital signal value and the threshold value is a value of the digital reference signal input from the reference signal output line, the If the result of the comparison of the threshold comparison unit indicates that the digital signal value is smaller than the threshold, a first value that is a difference between the digital reference signal and the digital image signal is output, When the result of the comparison by the threshold comparing unit indicates that the digital signal value is larger than the threshold, the threshold comparing unit includes a difference processing unit that outputs a second value different from the first value. Features.

  There is provided an imaging apparatus in which the influence of the black sun phenomenon is reduced and the increase in circuit scale is suppressed.

FIG. 2 is a diagram illustrating a configuration of an imaging device according to the first embodiment. FIG. 2 is a diagram illustrating configurations of a pixel, a readout unit, and a DSP according to the first embodiment. FIG. 3 is a diagram illustrating the timing of AD conversion of the imaging device according to the first embodiment. It is a figure showing composition of a pixel, a read-out part, and DSP concerning a 2nd embodiment. It is a figure showing the timing of AD conversion of an imaging device concerning a 3rd embodiment. (A) is a diagram showing a configuration of a DSP according to a fourth embodiment, and (b) is a diagram showing a configuration of a DSP according to a fifth embodiment. It is a figure showing the composition of the amplification part concerning a 6th embodiment. It is a figure showing the circuit composition of the pixel and the comparator concerning a 7th embodiment. It is a figure showing the composition of the imaging system concerning an 8th embodiment.

  An embodiment of the present invention will be described with reference to the drawings. In the drawings of each embodiment, elements having the same functions are denoted by the same reference numerals, and redundant description may be omitted.

(1st Embodiment)
FIG. 1 is a diagram illustrating a configuration of an imaging device 100 according to the first embodiment. The imaging device 100 includes a pixel unit 10, a vertical scanning circuit 20, a reading unit 30, a reference signal generation circuit 40, a counter 50, a horizontal scanning circuit 60, a digital signal processor (DSP) 70, and a timing generation circuit (TG) 80. The reading unit 30 includes a comparing unit 34 and a memory unit 36. The comparison unit 34 includes comparators 34a provided corresponding to each column of the pixel unit 10.

  The pixel unit 10 includes a plurality of pixels 10a arranged in a matrix of m rows and n columns over a plurality of rows (m rows) and a plurality of columns (n columns). The vertical scanning circuit 20 supplies a control signal for each row to the pixels 10a via a row control signal line (X1,... Xm) provided corresponding to each row of the pixel unit 10. With these control signals, the pixels 10a in each row of the pixel section 10 are sequentially selected, and the pixel signals Vpix, which are analog signals, are output from the pixels 10a. The pixel signal Vpix includes two types of signals, a reference signal Vn (analog reference signal) and an image signal Vs (analog image signal). The reference signal Vn is a signal indicating a reference level when the pixel 10a is reset, and the image signal Vs is a signal obtained by superimposing the reference signal Vn on a signal corresponding to light incident on the pixel 10a.

  The pixel signal Vpix output from the pixel 10a is transmitted to the readout unit 30 via vertical signal lines (Y1,... Yn) provided corresponding to each column of the pixel unit 10.

  The reading unit 30 includes a comparing unit 34 and a memory unit 36. The comparison unit 34 includes comparators 34a provided corresponding to each column of the pixel unit 10. The memory unit 36 includes a memory 36S and a memory 36N provided corresponding to each column of the pixel unit 10. The reading unit 30 mainly has a function of converting the pixel signal Vpix output from the pixel unit 10 from analog to digital (AD conversion). The reading unit 30 has a plurality of column circuit units. Each of the plurality of column circuit units has one comparator 34a, one memory 36S, and one memory 36N. One column circuit portion is provided corresponding to one column of the pixel 10a.

  The reference signal generation circuit 40 outputs a reference signal to each of the comparators 34a provided in the comparison unit 34. The reference signal is, for example, a ramp signal whose potential changes linearly with time. In the following description, the reference signal is a ramp signal Vramp. The counter 50 outputs a counter signal Φcot to each of the memories 36N and 36S provided in the memory unit 36.

  The comparing unit 34 compares the pixel signal Vpix output from the pixel 10a in each column with the ramp signal Vramp. At this time, the processing in the comparison unit 34 for each column is performed in parallel. The counter value indicating the time until the comparison result is inverted is temporarily held in each of the memories 36N and 36S in the memory unit 36 as digital data (for example, 12-bit binary digital data). In this way, AD conversion is performed for each column. Each memory 36N holds a reference signal Vn (digital reference signal) after AD conversion, and each memory 36S holds an image signal Vs (digital image signal) after AD conversion.

  The horizontal scanning circuit 60 outputs control signals (H1,... Hn) to the memories 36N, 36S. Each of the memories 36N and 36S sequentially outputs the digital data held therein to the reference signal output line 38N and the image signal output line 38S according to the control signals (H1,... Hn). That is, the digital data held in the memory 36N of each column is commonly input to the reference signal output line 38N, and the digital data held in the memory 36S of each column is commonly input to the image signal output line 38S. The reference signal output line 38N and the image signal output line 38S are connected to the DSP 70.

  The DSP 70 performs signal processing such as detection of saturation of the pixel 10a and noise reduction based on digital data input via the reference signal output line 38N and the image signal output line 38S, and outputs image data to the outside of the imaging device 100. Signal processing device.

  The TG 80 outputs control signals to the vertical scanning circuit 20, the reference signal generation circuit 40, the counter 50, the horizontal scanning circuit 60, and the DSP 70 based on a predetermined processing flow to control them. The TG 80 performs these operations based on external control. For example, the TG 80 is controlled by a system control unit of an imaging system in which the imaging device 100 is mounted.

  FIG. 2 is a diagram illustrating the configuration of the pixel 10a, the readout unit 30, and the DSP 70 according to the first embodiment. The illustrated pixel 10a is a pixel arranged in the i-th column, and the circuit shown in the read-out unit 30 shows only a portion corresponding to the pixel 10a in the i-th column.

  The pixel 10a has a photodiode PD, a transfer transistor 11, a reset transistor 12, an amplification transistor 13, and a selection transistor 14. Control signals ΦTx, ΦRes, and ΦSel are input from the vertical scanning circuit 20 to the gates of the transfer transistor 11, the reset transistor 12, and the selection transistor 14, respectively. Although these transistors are N-type MOS transistors, other transistors may be used. For example, each transistor may be p-type.

  The photodiode PD is a photoelectric conversion unit that generates a charge according to incident light. The cathode of the photodiode PD is connected to the source of the transfer transistor 11. The drain of the transfer transistor 11 and the source of the reset transistor 12 are connected to a floating diffusion (FD) which is a gate of the amplification transistor. The power supply voltage Vd is input to the drain of the reset transistor 12 and the drain of the amplification transistor 13. The source of the amplification transistor 13 is connected to the drain of the selection transistor 14, and the source of the selection transistor 14 is connected to the vertical signal line Yi.

  When the control signal φTx input to the gate of the transfer transistor 11 becomes High, the photocharge generated in the photodiode PD is transferred to the FD, and charge-voltage conversion is performed by the parasitic capacitance generated in the FD. When the control signal φRes input to the gate of the reset transistor 12 becomes High, the residual charges held in the FD are removed and the reset is performed. The amplification transistor 13, the selection transistor 14, and the current source IR form a source follower circuit.

  The selection transistor 14 controls the operation of the source follower circuit by controlling the connection between the source of the amplification transistor 13 and the current source IR by the control signal ΦSel. By the operation of the source follower circuit, the pixel signal Vpix is output from the pixel 10a to the vertical signal line Yi.

  As described above, the pixel signal Vpix includes two types of signals, the reference signal Vn and the image signal Vs. The reference signal Vn is a signal output to the vertical signal line Yi when the reset transistor 12 is turned on to reset the FD. The image signal Vs is a signal output to the vertical signal line Yi when the phototransistor stored in the photodiode PD is transferred to the FD when the transfer transistor 11 is turned on. That is, the image signal Vs is a signal in which the reference signal Vn is superimposed on a signal corresponding to the incident light.

  The comparator 34a has a first input terminal and a second input terminal to which two voltages to be compared are input, and an output terminal to output a comparison result. The reset switch SW0 and the clamp capacitors Ci1 and Ci2 are connected to the comparator 34a. The pixel signal Vpix is input to the first input terminal of the comparator 34a via the clamp capacitance Ci1. The ramp signal Vramp output from the reference signal generation circuit 40 is input to the second input terminal of the comparator 34a via the clamp capacitance Ci2.

  One ends of the two reset switches SW0 are connected to a first input terminal and a second input terminal signal of the comparator 34a, respectively. The reset switch SW0 is controlled by a control signal ΦAz. When the control signal ΦAz becomes High, the voltage clamped by the clamp capacitors Ci1 and Ci2 is reset.

  The comparator 34a outputs the latch signal φLt when the magnitude relationship between the signal levels of the pixel signal Vpix and the ramp signal Vramp is inverted. A counter signal Φcot corresponding to 12 bits is supplied from the counter 50 to the memories 36S and 36N, and the memories 36S and 36N hold the counter value of the counter signal Φcot at the time when the latch signal ΦLt is input as a digital signal. .

  The memory 36N outputs a digital signal DN (digital reference signal) corresponding to the reference signal Vn to a reference signal output line 38N. The memory 36S outputs a digital signal DS (digital image signal) corresponding to the image signal Vs to the image signal output line 38S. The digital signals DN and DS are input to the DSP 70.

  The DSP 70 includes a difference processing unit 72, a signal processing unit 74, a determination data output unit 76, and a determination unit 78.

  The difference processing unit 72 performs a difference process of subtracting the digital signal DN from the digital signal DS to remove the influence of the voltage of the reference signal of the pixel 10a, the offset voltage of the comparator 34a, and the like. The signal DS2 is output.

  The signal processing unit 74 obtains the digital signal DS3 by adding a black offset signal to the digital signal DS2 as a measure against shading of a dark signal, shifting the data level as digital gain processing of an effective signal, adjusting the number of data bits, and the like. Output to the outside.

  The determining unit 78 determines whether the signal level of the digital signal DS is saturated. The saturation of the signal level of the digital signal DS can be caused by the saturation of electric charge in the photodiode PD. Further, the saturation of the signal level of the digital signal DS may be caused by the fact that the image signal Vs exceeds the range in which AD conversion can be performed and the AD conversion process is saturated.

  The determination data output unit 76 includes a storage unit such as a register that stores a predetermined determination value used for determination by the determination unit 78. The predetermined determination value is a threshold value that is compared with a digital signal value of at least one of the digital reference signal and the digital image signal. The judgment data output unit 76 has a judgment data DS_H (digital image signal judgment) within a range smaller than the value corresponding to the output value when the charge is already saturated in the photodiode PD, that is, within a range where the charge is not saturated in the photodiode PD. Value). The determination data DS_H is set within a range where the AD conversion processing of the image signal Vs is not saturated so that the saturation of the signal level of the digital signal DS can be correctly detected.

  The determination unit 78 compares the digital signal DS with the determination data DS_H. As a result of the comparison, when the signal level of the digital signal DS is equal to or higher than the determination data DS_H, the determination unit 78 outputs the determination signal ΦCT indicating the determination result as High. When the signal level of the digital signal DS is lower than the determination data DS_H, the determination unit 78 outputs the determination signal ΦCT indicating the determination result as Low. The determination unit 78 is a threshold comparison unit that compares a digital signal value of at least one of the digital reference signal and the digital image signal with a predetermined determination value that is a threshold.

  The difference processing unit 72 outputs one of the two types of signals as the digital signal DS2 based on the level of the determination signal ΦCT. Specifically, when the determination signal ΦCT is Low, the difference value obtained by subtracting the digital signal DN from the digital signal DS is output as the digital signal DS2 as described above. Thus, the influence of the voltage of the reference signal Vn of the pixel 10a, the offset voltage of the comparator 34a, and the like is removed, and the digital signal DS2 corresponding to the photocharge is obtained. On the other hand, when the determination signal ΦCT is High, the difference processing unit 72 outputs a digital signal having a correction value corresponding to a white level different from a difference value obtained by subtracting the digital signal DN from the digital signal DS as the digital signal DS2. I do. The digital signal corresponding to the white level can be, for example, the maximum value among the possible values of the digital signal.

  When charges are saturated in the photodiode PD, a false signal generated by charges overflowing from the photodiode PD is superimposed on the digital signal DN. In such a case, the digital signal DS2 may have a signal level lower than the white level due to the difference processing between the digital signal DS and the digital signal DN. At this time, the captured image may have a black sun phenomenon in which the luminance of a part that should be white originally appears to be reduced. In the present embodiment, the effect of the black sun phenomenon can be reduced by detecting that the charge of the photodiode PD is saturated and setting the output signal to a signal level equivalent to the white level.

  The signal corresponding to the white level output as the digital signal DS2 may be a high-resolution 12-bit signal or a low-resolution 6-bit signal.

  Similarly, the judgment data DS_H is data for judging saturation, and therefore may be low-resolution data, for example, 6 bits. However, the present invention is not limited to this, and may be, for example, 12 bits.

  The determination unit 78, the determination data output unit 76, and the like of the first embodiment are circuits provided in common for each column of the reading unit 30. Therefore, in the first embodiment, the circuit scale can be reduced as compared with the case where the determination unit 78, the determination data output unit 76, and the like are provided for each column. Therefore, according to the first embodiment, it is possible to suppress an increase in the circuit scale while reducing the influence of the black sun phenomenon. In addition, according to the configuration of the first embodiment, since the circuit scale is small, power consumption can be reduced.

  As described above, the determination signal ΦCT indicating the determination result is a signal supplied to the difference processing unit 72. However, the determination signal ΦCT may be output to the outside as a flag signal. In the signal processing unit external to the imaging device 100, for example, the data corresponding to the case where the determination signal ΦCT is High is not used for the interpolation processing between the image data, thereby achieving an appropriate interpolation signal level. Becomes possible.

  FIG. 3 is a diagram illustrating the timing of AD conversion of the pixel signal Vpix in the imaging device 100 according to the first embodiment. In FIG. 3, the horizontal direction indicates time, and the vertical direction indicates a schematic waveform of the potential of each signal.

  The waveforms of the ramp signal Vramp and the pixel signal Vpix in FIG. 3 indicate changes in the potentials input to the two input terminals of the comparator 34a and compared by the comparator 34a.

  FIG. 3 shows each signal at the time of normal light, which is an incident light amount in a range where the photodiode PD of the pixel 10a is not saturated, and each signal at the time of excessive light, which is an incident light amount at which the photodiode PD of the pixel 10a is saturated. It is shown. “Vn” and “Vs” in the figure indicate a reference signal and an image signal during normal light, and “Vn ′” and “Vs ′” indicate a reference signal and an image signal during excessive light. .

  The period from time t31 to t33 is a period during which AD conversion of the reference signal Vn is performed (N-AD conversion period), and the period from time t51 to t53 is a period during which AD conversion of the image signal Vs is performed (S-AD conversion). Period). In the N-AD period, the comparator 34a performs a comparison process between the reference signal Vn (or Vn ') and the ramp signal Vramp_N. In the S-AD period, the comparator 34a performs a comparison process between the image signal Vs (or Vs') and the ramp signal Vramp_S. In each AD conversion period, the counter 50 supplies the counter signal Φcot to the memories 36S and 36N. When the magnitude relationship between the potentials of the pixel signal Vpix and the ramp signal Vramp is inverted, the comparator 34a generates a latch signal ΦLt based on the comparison result. In response to this, the counter value at that time is held in the memories 36S and 36N.

  First, the AD conversion in normal light and the processing operation in the DSP 70 will be described.

  At time t1, the control signal ΦSel becomes High, and the pixel source follower circuit operates. At time t1, the control signals ΦRes and ΦAz become High, and the FD and the comparator 34a are reset to the initial state.

  At time t2, the control signal ΦRes becomes Low, and the reference signal Vn is output to the vertical signal line Yi.

  At time t3, the control signal ΦAz becomes Low, and the potential of the input terminal of the clamp capacitor Ci1 becomes the level of the reference signal Vn. As a result, the output terminal of the capacitor Ci1, that is, the input potential of the comparator 34a is clamped at Vn. The potential of the input terminal of the capacitor Ci2 is clamped to the reference potential of the ramp signal Vramp, and the output of the capacitor Ci2 is clamped to the same potential as Vn.

  At time t31, the N-AD conversion starts, and the potential of the ramp signal Vramp_N starts to decrease. At time t32, the potential of the ramp signal Vramp_N falls below the potential of the reference signal Vn. At this time, a pulse of the latch signal ΦLt is generated, and the count value N1 is held in the memory 36N.

  At time t4, the control signal ΦTx becomes High, the photocharge accumulated in the photodiode PD is transferred, and at time t5, the control signal ΦTx becomes Low, and the input potential of the comparator 34a becomes the potential of the image signal Vs. Become.

  At time t51, S-AD conversion is started, and the potential of the ramp signal Vramp_S starts to decrease. At time t52, the potential of the ramp signal Vramp_S falls below the potential of the image signal Vs. As a result, a pulse of the latch signal φLt is generated, and the count value S1 is held in the memory 36S.

  The count values N1 and S1 are transmitted to the difference processing unit 72 as digital signals DN and DS, respectively. The level of the digital signal DS is compared with the level of the determination data DS_H in the determination unit 78. However, since the digital signal DS is smaller than the level of the determination data DS_H, the determination signal φCT remains Low. Therefore, the difference processing section 72 outputs a digital signal DS2 of the difference between DS and DN.

  Next, the AD conversion at the time of excessive light and the processing operation in the DSP 70 will be described. The description of the same operation as in the normal light may be simplified or omitted.

  At time t3, the control signal ΦAz becomes Low, and the potential of the input terminal of the clamp capacitor Ci1 becomes the level of the reference signal Vn '. As a result, the output terminal of the capacitor Ci1, that is, the input potential of the comparator 34a is clamped at Vn '. However, after time t3, the charge saturated in the photodiode PD overflows to the FD, and the level of the reference signal Vn 'gradually decreases with time. At this time, the potential of the input terminal of the capacitor Ci2 is clamped to the reference potential of the ramp signal Vramp, and the output of the capacitor Ci2 is clamped to the same potential as Vn '.

  Unlike the normal light described above, the potential of the reference signal Vn 'decreases with time, so that the comparison processing between the reference signal Vn' and the ramp signal Vramp_N may not be completed within the N-AD period. At this time, a value indicating that the AD conversion has not been completed within the N-AD period is held in the memory 36N. More specifically, at time t34, the memory 36N holds an excess bit for overflow or a count value N2 by carry. As another example, predetermined data may be stored in the memory 36N before AD conversion, and may be held.

  At time t4, the control signal ΦTx becomes High, and the pixel signal Vpix changes to the image signal Vs 'by superimposing a signal based on photocharge on the reference signal Vn'. Similarly to the N-AD period, the comparison process between the image signal Vs' and the ramp signal Vramp_S may not be completed within the S-AD period. Therefore, at time t54, the memory 36S holds the excess bit for overflow or the count value S2 due to carry. As another example, data corresponding to the determination data DS_H may be stored in the memory 36S before the AD conversion, and may be held.

  The count values N2 and S2 are transmitted to the difference processing unit 72 as digital signals DN and DS, respectively. The digital signal DS is compared with the determination data DS_H by the determination unit 78. Since the digital signal DS is larger than the determination data DS_H, the determination signal ΦCT changes from low to high. In response to the change of the determination signal ΦCT to High, the difference processing unit 72 outputs a signal corresponding to a white level as the digital signal DS2 instead of the difference between the digital signal DS and the digital signal DN.

  As described above, by performing the saturation determination of the photodiode PD based on the signal level of the digital signal DS, the digital signal DS2 can be set to the white level regardless of the value of the digital signal DN. Can be reduced. In the present embodiment, one column circuit unit is provided for one column of pixels 10a. As another example, one column circuit unit may be provided for a plurality of columns of pixels 10a. Further, a plurality of column circuit units may be provided for one column of pixels 10a. Such an example is also included in a form in which each of the plurality of column circuit units is arranged corresponding to the column in which the pixels 10a are arranged. In the present embodiment, an example has been described in which the potential of the ramp signal Vramp changes in a slope shape. The present invention is not limited to this example. For example, a signal whose potential changes stepwise is also included in the category of the ramp signal.

(2nd Embodiment)
In the first embodiment, the saturation of the photodiode PD is determined by comparing the digital signal DS with the determination data DS_H. On the other hand, in the second embodiment, the configuration of the DSP 70 is changed. By comparing the digital signal DN with the determination data DN_H (digital reference signal determination value) for the digital signal DN, the saturation of the photodiode PD is achieved. Is determined. The other configuration is the same as that of the first embodiment, and the description will be simplified or omitted.

  FIG. 4 is a diagram illustrating a configuration of a pixel 10a, a readout unit 30, and a DSP 70 according to the second embodiment.

  In the determination data output unit 76, the determination data DN_H is set in advance to a value smaller than the value corresponding to the output value when the charge is saturated in the photodiode PD, that is, within a range where the charge is not saturated in the photodiode PD. . Further, the determination data DN_H is set within a range where the AD conversion processing of the reference signal Vn is not saturated so that the saturation of the signal level of the digital signal DN can be correctly detected.

  The determination unit 78 compares the digital signal DN with the determination data DN_H. As a result of the comparison, when the signal level of the digital signal DN is equal to or higher than the determination data DN_H, the determination unit 78 outputs the determination signal ΦCT indicating the determination result as High. When the signal level of the digital signal DN is lower than the determination data DN_H, the determination unit 78 outputs the determination signal ΦCT indicating the determination result as Low. When the determination signal ΦCT is High, the difference processing unit 72 outputs a digital signal corresponding to a white level different from the difference obtained by subtracting the digital signal DN from the digital signal DS.

  Also in the second embodiment, similarly to the first embodiment, it is possible to suppress an increase in the circuit scale while reducing the influence of the black sun phenomenon. Further, since the circuit scale is small, power consumption can be reduced.

  Note that the configuration for comparing the digital signal DS and the determination data DS_H of the first embodiment and the configuration for comparing the digital signal DN and the determination data DN_H of the second embodiment are combined to determine both the digital signals DS and DN. A configuration that can be used may be adopted.

(Third embodiment)
FIG. 5 is a diagram illustrating the timing of AD conversion of the imaging device according to the third embodiment. In the third embodiment, a function of making the amplitude of the ramp signal Vramp output from the reference signal generation circuit variable is added to the configuration of the first embodiment or the second embodiment. By making the amplitude of the ramp signal Vramp signal variable, the resolution of AD conversion can be made variable. That is, the gain of the pixel signal at the time of AD conversion can be changed. In the third embodiment, a description will be given assuming that the gain is variable to two values of 1 or 2 times. The other configuration is the same as that of the first embodiment or the second embodiment, so that the description is omitted or simplified. In the third embodiment, the determination may be performed using the digital signal DS as in the first embodiment, the determination may be performed using the digital signal DN as in the second embodiment, or both of them may be performed. Good.

  The change of the signal level with respect to the time of the ramp signal Vramp differs by a factor of 2 between the case where the gain is 1 and the case where the gain is 2 times. The N-AD ramp signal Vramp_N1 and the S-AD ramp signal Vramp_S1 shown in FIG. 5 correspond to a gain of one. The ramp signal Vramp_N2 for N-AD and the ramp signal Vramp_S2 for S-AD correspond to a double gain.

  First, determination data used for determining the saturation of the photodiode PD (or the maximum value of AD conversion) from the digital signal DS will be described. When the gain is 1, the determination data DS_H1 having a value smaller than the digital value corresponding to the maximum value of the ramp signal Vramp_S1 is used. When the gain is twice, the determination data DS_H2 having a value smaller than the digital value corresponding to the maximum value of the ramp signal Vramp_S2 is used. As described above, the determination data serving as the reference for the determination can be determined according to the resolution of the AD conversion.

  When the gain is twice, even if the photodiode PD is saturated, the signal level after AD conversion is hardly saturated. However, the maximum value of the AD conversion that is larger than the determination data DS_H2 corresponds to the white level. Therefore, when the value obtained by AD-converting the image signal Vs' with a double gain is equal to or greater than the determination data DS_H2, the difference processing unit 72 determines that the difference between the digital signal DS and the digital signal DN is a signal corresponding to the white level. As a digital signal DS2.

  Next, determination data for determining the saturation of the photodiode PD (or the maximum value of AD conversion) from the digital signal DN will be described. After the initialization, the comparator 34a generates an offset voltage between the two input terminals. Therefore, it is necessary to obtain and remove the offset voltage. A period during which the AD conversion of the reference signal Vn including the offset voltage is performed is an N-AD period. The amplitude of the ramp signal Vramp_N2 is set to a voltage larger than the range of the variation of the offset voltage between the columns △ Voff. In addition, it is necessary to consider the level of a false signal generated when the charge overflowing due to the saturation of the photodiode PD is superimposed on the reference signal. The maximum value of the ramp signal Vramp_N2 when the gain determined in consideration of the above is twice is the determination data DN_H1. This determination data DN_H1 is used both when the gain is one and when the gain is two. As described above, the determination data serving as the reference for the determination of the digital signal DN can be determined in consideration of the variation of the offset voltage between the columns and the level of the false signal, and is the same even when the resolution of the AD conversion is changed. It can be.

  The reason why the determination data DN_H1 should be used even when the gain is 1 will be described. It is assumed that the decision data DN_H corresponding to the maximum value of the AD conversion when the gain is 1 is set. The reference signal Vn 'is obtained by superimposing charges overflowing due to the saturation of the photodiode PD. Here, in the A / D conversion in which the gain comparing the ramp signal Vramp_N and the reference signal Vn ′ is one, the output of the comparator 34a is inverted within the N-AD period, and the count value N at that time is held in the memory 36N. Is done. The determination unit 78 compares the digital signal DN corresponding to the count value N with the determination data DN_H. As a result, the value of the digital signal DN is smaller than the value of the determination data DN_H, so that the determination signal ΦCT remains Low. Therefore, even though the photodiode PD is saturated, the difference processing section 72 outputs the difference between the digital signal DS and the digital signal DN. As a result, the signal level of the digital signal DS2 is reduced by the level of the false signal, and a black sun phenomenon may occur in an image. The determination data DN_H1 is set in consideration of the influence of the false signal due to the saturation of the photodiode PD. Therefore, if the determination data DN_H1 is used even when the gain is 1 as in the third embodiment, the influence of the black sun phenomenon due to such factors can be reduced.

  As described above, according to the third embodiment, in addition to obtaining the same effects as those of the first and second embodiments, a function of changing a gain at the time of AD conversion is added.

(Fourth embodiment)
FIG. 6A is a diagram illustrating a configuration of a DSP 70 according to the fourth embodiment. The difference processing unit 72 included in the DSP 70 illustrated in FIG. 6A includes a difference circuit 72A, a white data output unit 72B, and a switch SW1. The other configuration is the same as that of the above-described first embodiment, and thus the description is omitted or simplified.

  The difference circuit 72A outputs a difference between the digital signal DS and the digital signal DN. The white data output unit 72B outputs a digital signal corresponding to a white level as white data. The switch SW1 connects the signal processing unit 74 to the difference circuit 72A or the white data output unit 72B based on the determination signal ΦCT from the determination unit 78. When the determination signal ΦCT from the determination unit 78 is High, the output signal of the white data output unit 72B is input to the signal processing unit 74, and when the determination signal ΦCT from the determination unit 78 is Low, the output signal of the difference circuit 72A is The signal is input to the signal processing unit 74.

  In the fourth embodiment, the same effects as in the first embodiment can be obtained. In addition, in the fourth embodiment, the white data can be set to an arbitrary value, and there is an effect that the degree of freedom of operation is improved.

(Fifth embodiment)
FIG. 6B is a diagram illustrating a configuration of the DSP 70 according to the fifth embodiment. The difference processing unit 72 included in the DSP 70 illustrated in FIG. 6B includes a difference circuit 72A and a switch SW1. The other configuration is the same as that of the above-described first embodiment, and thus the description is omitted or simplified.

  The switch SW1 switches whether to input the digital signal DN to the difference circuit 72A based on the determination signal ΦCT from the determination unit 78. The difference circuit 72A outputs a difference between the digital signal DS and the digital signal DN. When the determination signal ΦCT from the determination unit 78 is High, the switch SW1 is disconnected, and the digital signal DN is not input to the difference circuit 72A. That is, the difference circuit 72A outputs a signal corresponding to the digital signal DS that is the input value as the digital signal DS2. When the determination signal ΦCT from the determination unit 78 is Low, the switch SW1 is in a connected state, and the difference circuit 72A outputs a digital signal DS2 that is a difference between the digital signal DS and the digital signal DN.

  In the fifth embodiment, the same effect as in the first embodiment can be obtained. Further, since a circuit for generating white data can be omitted, the circuit scale can be further reduced.

  As a modified embodiment of FIG. 6B, the switch SW1 may be replaced by a circuit that replaces the digital signal DS with black level data when the determination signal ΦCT is High. In this modified embodiment, the same effect as in the first embodiment can be obtained. Further, in the present modified embodiment, the switch SW1 can be omitted, so that the circuit scale can be further reduced.

(Sixth embodiment)
FIG. 7 is a diagram illustrating a circuit configuration of the amplification unit 32 according to the sixth embodiment. In the present embodiment, an amplifying unit 32 is added between the pixel unit 10 of the first embodiment and the comparator 34a. FIG. 7 shows only the circuit in the i-th column.

  The amplification unit 32 includes an amplifier 32a, an input capacitance Co, a variable capacitance Cf, and a switch SWC. The input capacitance Co is connected between the vertical signal line Yi and the inverting input terminal of the amplifier 32a. The variable capacitance Cf is connected between the inverting input terminal of the amplifier 32a and the output terminal of the amplifier 32a. The switch SWC is also connected between the inverting input terminal of the amplifier 32a and the output terminal of the amplifier 32a, and has a parallel connection with the variable capacitance Cf. The voltage Vref is input to the non-inverting input terminal of the amplifier 32a.

  The amplifier 32 can change the gain (Co / Cf) by changing the capacitance value of the variable capacitor Cf. Thereby, the imaging apparatus 100 can switch the imaging sensitivity.

  The operation of the amplifier 32 will be described. When the pixel 10a is reset, the switch SWC is controlled so as to be in a connected state. Thereby, the amplification unit 32 is reset. Thereafter, the switch SWC is turned off, and the image signal is input.

  In the sixth embodiment, the same effect as in the first embodiment can be obtained. In the sixth embodiment, the provision of the amplifying unit 32 makes it possible to amplify the image signal while suppressing a decrease in the S / N ratio of the image signal during photographing under low illuminance.

  Note that the amplification unit 32 of the sixth embodiment may be combined with the gain setting based on the amplitude of the ramp signal amplitude of the third embodiment.

(Seventh embodiment)
FIG. 8 is a diagram illustrating a circuit configuration of a pixel 10a and a comparator 34a according to the seventh embodiment of the present invention. In the seventh embodiment, a part of the circuit of the pixel 10a and the comparator 34a included in the readout unit 30 share a part of elements to form a differential circuit. The comparator 34a according to the seventh embodiment includes transistors 15, 16, a capacitor Cp, and a switch SW3. In the seventh embodiment, the transistor 15 is described as an N-type and the transistor 16 is described as a P-type. However, the present invention is not limited to this. Since the configuration of the pixel 10a is the same as that of the first embodiment, the description is omitted or simplified.

  The ramp signal Vramp is applied to the gate of the transistor 15 via the capacitor Cp. The source of transistor 15 is connected to vertical signal line Yi. That is, the source of the transistor 15 and the source of the selection transistor 14 are shared by the vertical signal line Yi, and are connected to the current source IR. The drain of the transistor 15 is connected to the drain of the transistor 16. The switch SW3 is connected between the gate and the drain of the transistor 15. The switch SW3 is controlled by the control signal ΦAz.

  Transistor 16 is a load transistor of transistor 15. A bias voltage Vb is connected to the gate of the transistor 16. The power supply voltage Vd is input to the source of the transistor 16.

  At the drain node of the transistor 15, a voltage indicating the result of comparison between the potential of the FD and the ramp signal Vramp is generated. That is, the drain node of the transistor 15 is an output terminal of a differential circuit including the pixel 10a and the comparator 34a. The output voltage Vo of the differential circuit is input to a subsequent circuit (not shown), and a latch signal φLt is generated. Subsequent circuits can be configured in the same manner as in the first embodiment.

  Even in the case where the circuits of the pixel 10a and the comparator 34a share a part to constitute a differential circuit as in the seventh embodiment, the same effect as in the first embodiment can be obtained. In the present embodiment, in addition, since the configuration of the comparator 34a is simplified, the AD conversion processing can be performed at high speed.

(Eighth embodiment)
FIG. 9 is a diagram illustrating a configuration of an imaging system 200 according to the eighth embodiment. The imaging system 200 includes, for example, an optical unit 210, an imaging device 100, a video signal processing unit 230, a recording / communication unit 240, a system control unit 260, and a reproduction / display unit 270. Note that this configuration is an example, and a portion having another function may be added, or a part thereof may be omitted. As the imaging device 100 provided in the imaging system 200 of the eighth embodiment, any of the imaging devices 100 of the first to seventh embodiments can be used.

  The optical unit 210, which is an optical system such as a lens, forms an image of the subject by forming light from the subject on the pixel unit 10 of the imaging device 100 in which the plurality of pixels 10a are arranged in a matrix.

  The imaging device 100 outputs a signal corresponding to the light imaged on the pixel unit 10 at a timing based on the signal from the TG 80. The signal output from the imaging device 100 is input to the video signal processing unit 230. The video signal processing unit 230 performs signal processing according to a method determined by a program or the like. Note that the DSP 70 described in the first to seventh embodiments may be provided in the video signal processing unit 230 instead of the imaging device 100, and a separate signal processing unit may be provided between the imaging device 100 and the video signal processing unit 230. It may be provided as a device. The signal obtained by the processing in the video signal processing unit 230 is sent to the recording / communication unit 240 as image data. The recording / communication unit 240 sends a signal for forming an image to the reproduction / display unit 270, and causes the reproduction / display unit 270 to reproduce / display a moving image / still image. The recording / communication unit 240 receives a signal from the video signal processing unit 230, communicates with the system control unit 260, and also performs an operation of recording a signal for forming an image on a recording medium (not shown). Do.

  The system control unit 260 controls the operation of the imaging system as a whole, and controls the driving of the optical unit 210, the TG 80, the recording / communication unit 240, and the reproduction / display unit 270. The system control unit 260 includes, for example, a storage device (not shown) that is a recording medium, in which programs and the like necessary for controlling the operation of the imaging system are recorded. Further, the system control unit 260 supplies a signal for switching the drive mode according to, for example, a user operation into the imaging system 200.

(Other embodiments)
The embodiment to which the present invention is applied is merely an example of some aspects to which the present invention can be applied, and does not prevent appropriate modification or modification without departing from the spirit of the present invention.

  For example, some or all of the configurations shown in the above embodiments may be arbitrarily selected and combined.

  The present invention supplies a program for realizing one or more functions of the above-described embodiments to a system or an apparatus via a network or a recording medium, and one or more processors in a computer of the system or the apparatus read and execute the program. This process can be realized. Further, it can also be realized by a circuit (for example, an ASIC) that realizes one or more functions.

10 pixel section 10a pixel 30 readout section (column circuit section)
38N reference signal output line 38S image signal output line 72 difference processing unit 78 determination unit (threshold comparison unit)

Claims (12)

A pixel unit having a plurality of pixels arranged in a plurality of rows and a plurality of columns, each of the plurality of pixels generating an analog reference signal and an analog image signal;
An amplifier that can set a plurality of gains and amplifies each of the analog reference signal and the analog image signal generated by each of the plurality of pixels with any of the plurality of gains,
Each is provided corresponding to the column of the pixel portion, each converts the analog reference signal amplified by the amplifier into a digital reference signal from analog to digital, and converts the analog image signal amplified by the amplifier into a digital image. A plurality of column circuit units for converting analog to digital into signals,
A reference signal output line to which the digital reference signal of each of the plurality of column circuit units is input;
An image signal output line to which the digital image signal of each of the plurality of column circuit units is input;
A threshold comparator for comparing the digital signal value and the threshold value is a value of the digital reference signal input from the reference signal output line,
When the result of the comparison of the threshold comparing unit indicates that the digital signal value is smaller than the threshold, a first value that is a difference between the digital reference signal and the digital image signal is output, And a difference processing unit that outputs a second value different from the first value when the result of the comparison by the threshold value comparison unit indicates that the digital signal value is larger than the threshold value. An imaging device characterized by the above-mentioned.   The imaging apparatus according to claim 1, wherein the threshold comparing unit compares the value of the digital reference signal as the digital signal value with a predetermined digital reference signal determination value as the threshold, as the comparison. . The imaging apparatus according to claim 2 , wherein the digital reference signal determination value is set to a value within a range where a process of analog-to-digital conversion of the analog reference signal is not saturated. The imaging apparatus according to claim 2 , wherein the digital reference signal determination value is set to a value within a range in which electric charges are not saturated in a photoelectric conversion unit included in each of the plurality of pixels. The imaging device according to any one of claims 1 to 4 , wherein the resolution of the analog-to-digital conversion performed in each of the plurality of column circuit units is variable. The second value, the imaging apparatus according to any one of claims 1 to 5, characterized in that corresponding to the white level. The second value, the imaging apparatus according to any one of claims 1 to 5, characterized in that corresponding to the input value of the digital image signal. The second value, the digital image signal and an imaging device according to any one of claims 1 to 5, characterized in that corresponding to the difference between the black level. The imaging apparatus according to any one of claims 1 to 8 , wherein the threshold comparing unit outputs a signal indicating a determination result as a flag signal used for signal processing outside the imaging apparatus. . Each of the plurality of column circuit units forms a differential circuit with each of the pixels,
The imaging apparatus according to any one of claims 1 to 9, characterized in that the analog-to-digital conversion is performed by the differential circuit. An imaging device according to any one of claims 1 to 10,
A video signal processing unit that processes a signal output from the imaging device. A pixel unit having a plurality of pixels arranged in a plurality of rows and a plurality of columns, each of the plurality of pixels generating an analog reference signal and an analog image signal;
An amplifier that can set a plurality of gains and amplifies each of the analog reference signal and the analog image signal generated by each of the plurality of pixels with any of the plurality of gains,
Each is provided corresponding to the column of the pixel portion, each converts the analog reference signal amplified by the amplifier into a digital reference signal from analog to digital, and converts the analog image signal amplified by the amplifier into a digital image. A plurality of column circuit units for converting analog to digital into signals,
A reference signal output line to which the digital reference signal of each of the plurality of column circuit units is input;
An image signal output line to which the digital image signal of each of the plurality of column circuit units is input;
A signal processing method of the digital reference signal and the digital image signal output from an imaging device having
It makes a comparison between the reference signal the digital signal value is a value of the digital reference signal supplied from the output line and a threshold value,
When the result of the comparison indicates that the digital signal value is smaller than the threshold, a first value that is a difference between the digital reference signal and the digital image signal is output, and the result of the comparison is And outputting a second value different from the first value when the digital signal value is larger than the threshold value.

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