TWI424742B - Methods and apparatus for high dynamic operation of a pixel cell - Google Patents

Methods and apparatus for high dynamic operation of a pixel cell Download PDF

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Publication number
TWI424742B
TWI424742B TW99106674A TW99106674A TWI424742B TW I424742 B TWI424742 B TW I424742B TW 99106674 A TW99106674 A TW 99106674A TW 99106674 A TW99106674 A TW 99106674A TW I424742 B TWI424742 B TW I424742B
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Taiwan
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photo
charge
exposure period
generated charge
transistor
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TW99106674A
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Chinese (zh)
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TW201106690A (en
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Sohrab Yaghmai
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Micron Technology Inc
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    • HELECTRICITY
    • H04ELECTRIC COMMUNICATION TECHNIQUE
    • H04NPICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N5/00Details of television systems
    • H04N5/30Transforming light or analogous information into electric information
    • H04N5/335Transforming light or analogous information into electric information using solid-state image sensors [SSIS]
    • H04N5/369SSIS architecture; Circuitry associated therewith
    • H04N5/374Addressed sensors, e.g. MOS or CMOS sensors
    • H04N5/3745Addressed sensors, e.g. MOS or CMOS sensors having additional components embedded within a pixel or connected to a group of pixels within a sensor matrix, e.g. memories, A/D converters, pixel amplifiers, shared circuits or shared components
    • H04N5/37452Addressed sensors, e.g. MOS or CMOS sensors having additional components embedded within a pixel or connected to a group of pixels within a sensor matrix, e.g. memories, A/D converters, pixel amplifiers, shared circuits or shared components comprising additional storage means
    • HELECTRICITY
    • H04ELECTRIC COMMUNICATION TECHNIQUE
    • H04NPICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N5/00Details of television systems
    • H04N5/30Transforming light or analogous information into electric information
    • H04N5/335Transforming light or analogous information into electric information using solid-state image sensors [SSIS]
    • H04N5/351Control of the SSIS depending on the scene, e.g. brightness or motion in the scene
    • H04N5/355Control of the dynamic range
    • H04N5/35536Control of the dynamic range involving multiple exposures
    • H04N5/35572Control of the dynamic range involving multiple exposures sequentially taken, e.g. using the combination of odd and even image fields
    • H04N5/35581Control of the dynamic range involving multiple exposures sequentially taken, e.g. using the combination of odd and even image fields with different integration times, e.g. short and long exposures
    • HELECTRICITY
    • H04ELECTRIC COMMUNICATION TECHNIQUE
    • H04NPICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N5/00Details of television systems
    • H04N5/30Transforming light or analogous information into electric information
    • H04N5/335Transforming light or analogous information into electric information using solid-state image sensors [SSIS]
    • H04N5/369SSIS architecture; Circuitry associated therewith
    • H04N5/374Addressed sensors, e.g. MOS or CMOS sensors
    • H04N5/3745Addressed sensors, e.g. MOS or CMOS sensors having additional components embedded within a pixel or connected to a group of pixels within a sensor matrix, e.g. memories, A/D converters, pixel amplifiers, shared circuits or shared components
    • H04N5/37457Addressed sensors, e.g. MOS or CMOS sensors having additional components embedded within a pixel or connected to a group of pixels within a sensor matrix, e.g. memories, A/D converters, pixel amplifiers, shared circuits or shared components comprising amplifiers shared between a plurality of pixels, e.g. at least one part of the amplifier has to be on the sensor array itself
    • HELECTRICITY
    • H04ELECTRIC COMMUNICATION TECHNIQUE
    • H04NPICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N5/00Details of television systems
    • H04N5/30Transforming light or analogous information into electric information
    • H04N5/335Transforming light or analogous information into electric information using solid-state image sensors [SSIS]
    • H04N5/369SSIS architecture; Circuitry associated therewith
    • H04N5/378Readout circuits, e.g. correlated double sampling [CDS] circuits, output amplifiers or A/D converters

Description

Method and device for high dynamic operation of pixel unit

The embodiments set forth herein are generally directed to imaging devices and, more particularly, to methods and apparatus for providing high dynamic operation of an imaging device.

Many portable electronic devices, such as cameras, cellular phones, personal digital assistants (PDAs), MP3 players, computers, and other devices, contain an imager for capturing images. An example of an imager is a complementary metal oxide semiconductor ("CMOS") imager. A CMOS imager includes a focus plane array of pixels, each of the pixels including at least one photo-electric sensor overlying a substrate for accumulating photo-generated charges in a lower portion of the substrate. Each pixel can include at least one electronic device (eg, a transistor) for transferring charge from the photo-electrical sensor to a storage region.

Each pixel has a corresponding readout circuit, the corresponding readout circuit comprising: at least one charge storage region connected to the gate of the output transistor; an output source follower transistor; and a reset transistor for The charge storage region is reset to a predetermined charge level; and a column of control transistors for selectively connecting the readout circuit to a row of lines. The charge storage region can be constructed as a floating diffusion region. Each pixel may have a separate readout circuit, or may employ a common element pixel architecture (CEPA), which may include multiple pixels that share a single readout circuit group.

A pixel (including a photo-electric detector) and its corresponding readout circuitry are collectively referred to herein as a "pixel circuit." In a CMOS imager, the active components of a pixel circuit perform the following necessary functions: (1) photon to charge conversion; (2) cumulative image charge; (3) resetting the storage area to a known state; (4) The charge is transferred to the storage region along with the charge amplification; (5) a pixel circuit is selected for reading; and (6) the output signal is amplified and represents one of a reset level and a pixel charge. The charge can be amplified as it moves from the initial charge accumulation region to the storage region. The charge at the storage area is typically converted to a pixel output voltage by a source follower output transistor.

1 illustrates a typical four transistor (4T) pixel circuit 100 for use in a pixel array of an imager (eg, a CMOS imager). The pixel circuit 100 includes a pixel having a photo-electric detector 102 (for example, a photo-electric detector, a photodiode, a shutter or a photoconductor) and a transfer transistor 120. The pixel circuit 100 also includes a readout circuit including a storage region configured as a floating diffusion region 106, a reset transistor 130, a source follower transistor 140, and a column of select transistors 150. When the transfer transistor 120 is activated by a transfer control signal TX, the at least one photo-electric detector 102 is connected to the floating diffusion region 106 by the transfer transistor 120. The reset transistor 130 is connected between the floating diffusion region 106 and an array of pixel supply voltages V AA . A reset control signal RST is used to activate reset transistor 130, which resets floating diffusion region 106 to a predetermined reset voltage corresponding to one of array pixel supply voltages V AA , as is well known in the art.

The source follower transistor 140 has its gate connected to the floating diffusion region 106 and connected between the array pixel supply voltage V AA and the column selection transistor 150. The source follower transistor 140 converts the charge stored at the floating diffusion region 106 into an electrical output signal. Column select transistor 150 can be controlled by a column of select signals RS for selectively outputting an output signal V OPIX from source follower transistor 140 to row line 108. In a CMOS imager, conventionally two output signals for each pixel circuit; a signal output line reset signal V OPIX_RST one generated after the reset floating diffusion region 106, the output signal is further based on the charge from the photoelectric One of the image or optical signals V OPIX — SIG generated after the sensor 102 transitions to the floating diffusion region 106 . This process is often referred to as "related double sampling" or "CDS." The output signals V OPIX_RST , V OPIX_SIG are selectively stored in a sample and hold circuit (not shown).

The image sensor (eg, one of the image sensors of conventional pixel circuit 100) has a characteristic dynamic range. Dynamic range refers to the range of incident light that can be contained in a single pixel data frame by an image sensor. It is desirable to have an image sensor having a high dynamic range for imaging scenes that produce high dynamic range incident signals, such as indoor rooms with outward windows, outdoor scenes with mixed shadows and bright sunlight, combinations Night scenes with artificial lighting and shadows and many other scenes.

The dynamic range of an image sensor is typically defined as the ratio of its maximum unsaturated signal to the standard deviation of its noise in dark conditions. The dynamic range is limited by an upper limit of the charge saturation level of the sensor and is limited by a limit and/or quantization limit imposed by the analog to digital converter used to generate the digital image to a lower limit. Image distortion can occur when the dynamic range of an image sensor is too small to accommodate changes in the intensity of the imaged scene (eg, due to a low saturation level).

One problem associated with charge generation in conventional pixel circuits occurs when the incident light captured during an integration period and converted to charge is greater than the charge storage capacity of the photo-electrical sensor. In the case where one photo-inductor of a pixel circuit is exposed to a large amount of incident light (which generates a charge that exceeds the capacity of the photo-inductor), any additional photon-to-charge conversion will require some charge leakage to escape the photodiode Body region 102. Typically, this leakage causes the charge to migrate to adjacent pixel circuits, causing crosstalk.

Additionally, when charge generated during an integration cycle is output from the photodetector to the floating diffusion region 106 during transfer, a small amount of residual charge may remain in the photodetector. This residual charge causes an accumulation of charge in a subsequent captured image to be excessive and can cause the photoinductor to exceed its maximum capacity more quickly, thereby causing excess charge to overflow to adjacent pixels. The phenomenon of charge overflow at this undesired photo-inductor is referred to as blooming and can produce several vertical and/or horizontal stripes in the resulting output image.

One solution that has been proposed for this blooming problem is a plurality of exposure modes in which the charge generated in a photodetector region during a plurality of exposure periods is sampled and combined. For example, a pixel can be operated in a double exposure mode, wherein an output circuit of the pixel circuit is output during a first sampling operation during a first exposure period T1 in a photodetector region (eg, for example, One of the first charges V1 is generated in the photodiode 102) of FIG. Then, the photodetector region is reset, and a second charge V2 is generated in the photodetector region during a second exposure period T2 via the output circuit of the pixel circuit during a second sampling operation. While a plurality of exposure operations allow for a higher dynamic range of one of the pixel circuits 100, multiple charge generation and sampling cycles result in a reduced frame rate. In addition, a line buffer for storing a plurality of sampled charges is required, resulting in a higher desired grain size and/or a lower fill rate for one of the pixel circuits.

Yet another solution that has been proposed is a lateral overflow mode in which photogenerated charges are generated in a photoelectric conversion region (e.g., photodiode 102), and if the photogenerated charge exceeds one of the photoelectric conversion regions When a threshold is predetermined, an excess of the photo-generated charge is transferred to a floating diffusion region of the pixel circuit (for example, the floating diffusion region 106 of FIG. 1) after a first exposure period T1. The excess portion can be transferred by applying a "soft transfer" signal to one of the gates of the transfer transistor (e.g., transfer transistor 120 of FIG. 1) separating the photoelectric conversion region from the floating diffusion region, wherein The soft transfer signal is less than a voltage across the voltage required to fully transfer charge across the transfer transistor.

The excess charge can be discarded by resetting the floating diffusion region (e.g., by applying a reset signal to reset transistor 130 in Figure 1), or alternatively, the excess charge can be sampled. The remaining charge generated during the first exposure period T1 and any additional charge generated during a second exposure period T2 are transferred to the floating diffusion region and sampled to produce an output pixel signal V OPIX_SIG . Regardless of whether the excess charge V1 is discarded or sampled, in order to account for the excess charge, when operating in the lateral overflow mode, the output pixel signal V OPIX_SIG must be calculated according to one of the pixel circuits "inflection point", which is the soft transfer signal of the transfer transistor and / or one of the resulting threshold voltages V TH . Although a lateral transfer mode increases the dynamic range of the pixel, the inflection point of the pixel circuit must be calibrated (associated with the threshold voltage VTH ), requiring an additional readout cycle of one of the pixel circuits, and thus resulting in a reduced frame rate and / or add noise.

A further solution has been proposed for overcoming the above-mentioned problems (as disclosed in U.S. Patent No. 7,238,977, issued to U.S. Patent No. 7, 238, 977 The content is incorporated herein by reference in its entirety to the extent that it is provided to one of the pixel circuits 200 having an anti-overflow transistor 260. As shown in FIG. 2, pixel circuit 200 is similar to 4T pixel circuit 100 of FIG. 1, but has an additional transistor 260.

During one integration period of the pixel circuit 200, when the photoelectric conversion region 102 (which may be any one of a photo-electrical sensor, a photodiode, a shutter, or a photoconductor) becomes charged saturated, it is resistant to blooming (AB) The transistor 260 transfers some excess charge to one of the drain regions 262 associated with the AB transistor 260. The drain region 262 can be connected, for example, to a pixel voltage V AA , and the excess charge is discarded into the drain region 262 of the AB transistor 260 without being sampled. The proposed pixel circuit 200 design effectively increases the dynamic range compared to the conventional pixel circuit 100 (FIG. 1), however, the proposed pixel circuit 200 also has disadvantages. Since the excess charge is not sampled, the readout voltage V OPIX_SIG must account for the excess charge transferred across the drain region 262 of the AB transistor 260 if the excess charge is to be fully accounted for. A CMOS transistor (e.g., AB transistor 260) has a high threshold voltage deviation between the wafer and the wafer and typically between the transistor and the transistor. This bias causes an uncertainty in the amount of charge stored between the pixel circuit and the pixel circuit because the threshold voltage of each transistor (including the anti-brightout transistor) can be different. The difference in charge storage between the pixel circuit and the pixel circuit results in a fixed pattern noise (FPN) in the imager array due to the inconsistency in the barrier height of the transistor 260 between the pixel and the pixel, resulting in reduced image quality.

An optimal pixel circuit has a high dynamic range (which has a predictable response), a low die size and high fill rate, a high frame rate potential, and low noise. Therefore, there is a need for a pixel circuit that has the potential for improved saturation response and lower blooming potential but that has the potential to cause other effects resulting from the previously proposed solutions set forth above.

In the following detailed description, reference is made to the specific embodiments The embodiments are described in sufficient detail to enable those skilled in the art to practice the invention. It is understood that other embodiments may be employed, and the structure and logic may be made without departing from the spirit or scope of the invention. change.

The present disclosure includes embodiments of a pixel circuit configured to improve high dynamic range operation. The pixel circuit and method of operating the pixel circuit described herein provide an increased dynamic range by sampling a photo-generated charge that exceeds one of the capacitances of one of the photoelectric conversion regions without the need for threshold calibration (eg, The required horizontal buffer mode or the additional line buffer or multiple non-overlapping sampling periods (as required in the double exposure mode set forth above). Embodiments include: a pixel circuit having a storage region between a photoelectric conversion region and another storage region configured to be connected by a storage transistor; and operating the pixel circuit in a lateral overflow and double exposure mode The method.

FIG. 3 shows a pixel circuit 300 configured to operate in accordance with the embodiments set forth herein. The pixel circuit 300 includes a photo-electric detector 302 (for example, a photo-electric detector, a photodiode, a shutter or a photoconductor) and a transfer transistor 320. The pixel circuit 300 also includes a readout circuit that includes a readout storage region configured as a floating diffusion region 306, a reset transistor 330, a source follower transistor 340, and a column of select transistors 350. The pixel circuit 300 also includes a storage area 304 for storing photo-generated charges from the photo-inductor 302. The pixel circuit 300 can also include an anti-bright overflow transistor 360 that connects the photo-inductor 302 to a high-intensity highlight when an anti-brightness signal is applied to the gate AB of the anti-overflow transistor 360. Overflow bungee area 362. The anti-bright drain drain region 362 can be connected to an array of pixel supply voltages V AA or another voltage that is opposite in charge to the photogenerated charge generated in photodetector 302.

The storage area 304 is separated from the photodetector 302 by a storage transistor 310 (which can be configured as a global shutter transistor). Photodetector 302 is coupled to storage region 304 when a storage control signal is applied to one of the gates SG to activate storage transistor 310. The gate SG of the storage transistor 310 can be configured as a global shutter gate in which all shutter gates 310 of all pixels of an array are simultaneously operated. The storage region 304 is coupled to the floating diffusion region 306 by the transfer transistor 320 when a transfer control signal is applied to the gate TX TX to activate the transfer transistor 320. Reset transistor 330 is connected between the floating diffusion region 306 and array pixel supply voltage V AA. A reset control signal applied to one of the gates RST is used to activate the reset transistor 330, which resets the floating diffusion region 306 to a known state (ie, to correspond to the array pixel supply voltage V AA ) A predetermined reset voltage).

The source follower transistor 340 has its gate connected to the floating diffusion region 306 and connected between the array pixel supply voltage V AA and the column selection transistor 350. Source follower transistor 340 converts the charge stored at floating diffusion region 306 into an electrical output signal. The column select transistor 350 can be controlled by applying a column of select signals to the gate RS to selectively output the output signal V OPIX (which can include one of the output signals V OPIX_1 or V OPIX_2 in the method of operation described below) One or more of the output from the source follower transistor 340 to the line 308. The output signal V OPIX on the line line 308 can be sampled using "Related Double Sampling" or "CDS" (as is well known in the art).

4 through 7 illustrate a method of operating a pixel circuit (e.g., pixel circuit 300) and a corresponding imager assembly (described further below with respect to Figure 8) in which a signal is applied to operate the components of the pixel circuit. An imager control circuit 1076 (Fig. 8) can be configured to control the column and row driver circuits 1072, 1078 such that a drive voltage can be applied to the gate SG of the storage transistor 310 and the gate TX of the transfer transistor 320 (Fig. 3) and optional gate AB of the anti-overflow transistor 360. The gates SG, TX, and RS can be configured for rolling shutter operation or global shutter operation. However, the methods set forth below are not limited to embodiments in which operation is controlled by a control circuit, and may be in accordance with any of the devices or processes used to control the operation of the pixel circuitry and corresponding imager components well known to those skilled in the art. Operation.

FIG. 4 illustrates a method 400 of operating pixel circuit 300 in a lateral overflow mode. 5 shows a timing diagram of pixel circuit 300 corresponding to operation of pixel circuit 300 in accordance with the lateral overflow mode of method 400.

In step 402 of method 400 (FIG. 4), a first photogenerated charge is accumulated at photodetector 302 during a first exposure period T1. The first exposure period T1 has a duration that is longer than one of the subsequent second exposure periods T2 as further explained below. For example, the first exposure period T1 may be twice as long as the second exposure period T2. FIG. 5 shows (duration from times t 1 to time t 2), a first gate SG during the exposure period T1, AB and TX lines off.

The first photo-generated charge is accumulated until the end of the first exposure period T1 (at this time, as shown in step 404, a "soft transfer" signal is applied to the gate AB of the anti-overfill transistor 360 (Fig. 5)). The soft transfer signal is less than one of the amount required to fully transfer the charge across the anti-overflow transistor 360, thereby producing a minimum threshold voltage to be transferred to one of the drain regions of the anti-overflow transistor 360. V TH . If the first photogenerated charge stored in photodetector 302 is below the threshold voltage VTH , the charge will not be transferred across anti-corona transistor 360. If the first photo-generated charge stored in the photo-detector 302 is greater than the threshold voltage V TH , then an excess of the first photo-generated charge stored in the photo-detector 302 will be transferred to the anti-corona transistor 360. The pole region, for example to the array pixel supply voltage V AA .

In step 406, the remaining portion of the first photo-generated charge (ie, the original first) is applied to the gate SG (FIG. 5) of the storage transistor 310 by applying a signal (ie, a "storage signal"). The photogenerated charge (if the photogenerated charge is less than the threshold voltage VTH ) or approximately equal to a portion of the threshold voltage VTH (if the original photogenerated charge is greater than the threshold voltage VTH )) (referred to as charge V1) is transferred to the storage region. The gate SG can be configured for global shutter operation.

Also during step 406 (or, alternatively, during more than one of steps 402, 404 or steps 402, 404, 406), resetting is performed by applying a reset signal to the reset gate RST. Floating diffusion region 306, and sampling pixel reset signal V OPIX_RST by amplifying the reset voltage stored in floating diffusion region 306 across source follower transistor 340 by applying a transfer signal to the column The gate RS of the transistor 350 is selected and the pixel circuit is selected for output and the pixel reset signal V OPIX_RST_1 is output to the line line 308. The pixel reset signal V OPIX_RST_1 is sampled by the sample and hold circuit 1082 (FIG. 8) by activating a first sample and hold signal SH1 (as shown in FIG. 5).

In step 408, the charge V1 is sampled by applying a signal (ie, a "transfer signal") to the gate TX of the transfer transistor 320 to transfer the charge V1 to the floating diffusion region 306, Amplifying the charge V1 across the source follower transistor 340 selects the pixel circuit 300 for outputting and outputting the charge V1 to the line line 308 by applying a signal to the gate RS of the column select transistor 350. The sample and hold circuit 1082 (FIG. 8) stores the amplified first pixel signal V OPIX_SIG1 by a second sample and hold signal SH2 (as shown in FIG. 5) and sets the differential voltage signal V OPIX_DIF1 = (V OPIX_RST_1 -V OPIX_SIG1) outputs to an analog to digital converter 1086 (FIG. 8). The analog to digital converter 1086 digitizes the differential signal V OPIX_DIF1 and supplies the digitized pixel signal V OPIX_DIF1 to an image processor 1088 (FIG. 8). If the original first photogenerated charge in the photodetector 302 is less than the threshold voltage V TH , the differential signal V OPIX — DIF1 represents a true sampled voltage corresponding to the amount of light detected at the photodetector 302 . If the original first photogenerated charge in the photodetector 302 is greater than the threshold voltage VTH (and thus transitions across the anti-overflow transistor 360 beyond the threshold voltage VTH during step 404), then the differential signal V OPIX_DIF1 Indicates a sampling voltage corresponding to one of the threshold voltages V TH .

Also in step 408, and simultaneously with the transfer and sampling of the charge V OPIX_DIF1 , a second photogenerated charge (referred to as V2) is accumulated at the photodetector 302 during a second exposure period T2. As shown in FIG. 5, the second exposure period T2 has a duration shorter than the first exposure period T1 (eg, T2 may be one-half length of T1), and thus, generally less charge during the second exposure period T2. Accumulated on the photodetector 302, and the photodetector 302 is unlikely to reach a saturation point. Since the photodetector 302 will typically not reach a saturation point during the second exposure period T2, the "soft transition" signal is not applied to the anti-highlight overflow during the second exposure period T2 or immediately after the second exposure period T2. Gate AB of transistor 360 (Fig. 5).

In step 410, the second photogenerated charge V2 is transferred to the storage region 304 by applying a signal to the gate SG of the storage transistor 310. Also during step 410, the floating diffusion region 306 is reset by activating the gate RST (FIG. 5) of the reset transistor 330, and the pixel reset signal V OPIX_RST_2 is sampled by: crossing the source The coupler transistor 340 amplifies the reset voltage stored in the floating diffusion region 306, selects a pixel circuit for outputting and outputs the pixel reset signal V OPIX_RST_2 by applying a signal to the gate RS of the column selection transistor 350. On line 308. The pixel reset signal V OPIX_RST_2 is sampled by the sample and hold circuit 1082 (FIG. 8) by activating the first sample and hold signal SH1 (as shown in FIG. 5).

In step 412, similar to a typical linear pixel, the second photogenerated charge V2 is sampled by transferring a charge V2 to the floating diffusion region by applying a signal to the gate TX of the transfer transistor 320. 306. Amplifying the charge V2 stored in the floating diffusion region 306 across the source follower transistor 340, and selecting a pixel circuit for outputting and discharging the charge V2 by applying a signal to the gate RS of the column selection transistor 350. Output to line 308. The amplified second pixel reset signal V OPIX_SIG2 is stored by the sample and hold circuit 1082 (FIG. 8) by activating the second sample and hold signal SH2 (as shown in FIG. 5), and the differential voltage signal V OPIX_DIF2 is (V OPIX_RST_2 -V OPIX_SIG2 ) is output to an analog to digital converter 1086 (Fig. 8). The analog to digital converter 1086 digitizes the differential signal V OPIX_DIF2 and supplies the digitized pixel signal to an image processor 1088 (FIG. 8).

In step 414, image processor 1088 (FIG. 8) determines pixel value V OPIX according to Equation 1:

Equation 1:

Wherein N is the ratio of the exposure period T1/T2, and VTH_MIN is one of the minimum threshold voltages of the pixel circuit 300 (FIG. 3). As shown in Equation 1, the calculated pixel signal V OPIX is not directly affected by the threshold voltage V TH derived from the anti-bright overflow transistor 360. Rather, if there is no saturation of the photodetector 302 during the first exposure period T1, then V OPIX = V OPIX_DIF1 . If V OPIX_DIF1 is less than the minimum threshold voltage V TH — MIN , there is no saturation of the photodetector 302 during the first exposure period T1 . If V OPIX_DIF1 is greater than the minimum threshold voltage V TH_MIN , but the normalized value of V OPIX_DIF 2 (ie, N *V OPIX_DIF2 ) is less than V OPIX_DIF1 , then there is no saturation of the photodetector 302 during the first exposure period T1 . It is thus indicated that the photo sensor 302 continues to generate charge during the entire exposure period T1.

However, if the normalized value of V OPIX_DIF2 (ie, N *V OPIX_DIF2 ) is greater than V OPIX_DIF1 , then this indication saturation does occur in photodetector 302 during the first exposure period T1 and is represented by sampled voltage V OPIX_DIF1 The threshold voltage V TH of the photo-inductor 302 derived from the anti-bright overflow transistor 360. The difference between the sampled voltages V OPIX_DIF1 and V OPIX_DIF2 is thus normalized for the first exposure period T1. There is no need for calibration of the threshold voltage VTH (as required in the prior art lateral flooding method). Furthermore, since V1 is sampled during the second exposure period T2, the total operating time is less than the double exposure mode well known in the art. In an alternate embodiment, the pixel value V OPIX may be determined in the analog domain prior to digitizing the differential signal V OPIX — DIF2 .

FIG. 6 illustrates a second method 600 of operating pixel circuit 300 in a dual exposure mode. FIG. 7 shows a timing diagram of pixel circuit 300 corresponding to operation of the dual exposure mode in accordance with method 600. While the anti-overfill transistor 360 is not necessary for the dual exposure mode of method 600, embodiments of pixel circuit 300 configured to operate in accordance with the dual exposure mode of method 600 may also include an anti-overfill transistor 360 (which remains off) Broken (as shown in Figure 7)) to provide operational flexibility, such as an option configured to operate in accordance with the lateral overflow mode of method 400.

In step 602 of method 600 (FIG. 6), a first photogenerated charge is accumulated at photodetector 302 during a first exposure period T1. The first exposure period T1 is one exposure period longer than one of the subsequent second exposure periods T2 as further explained below. For example, the first exposure period T1 may be twice as long as the second exposure period T2. During T1, as shown in Figure 7, the gates SG, AB, and TX are turned off.

Also during step 602 (or during step 604, described below), the floating diffusion region 306 is reset by applying a reset signal to the reset gate RST, and the pixel is reset by the following means V OPIX_RST_1 performs sampling: amplifying the reset voltage stored in the floating diffusion region 306 across the source follower transistor 340, and selecting the pixel circuit 300 by applying a signal to the gate RS of the column selection transistor 350 for The output and output of the pixel reset signal V OPIX_RST_1 to the line line 308. By starting a first sample and hold signal SH1 (shown in FIG. 7) by the sample and hold circuit 1082 (FIG. 8) to reset the signal V OPIX_RST_1 sampled and stored pixel.

In step 604 of method 600, a signal (ie, a "storage signal") is applied to gate SG (FIG. 7) of storage transistor 310 to convert the first photo-generated charge (referred to as charge V1) from the photo-inductor. The detector 302 is transferred to the storage area 304. The gate SG can be configured for global shutter operation.

In step 606, the charge V1 is sampled by applying a signal (ie, a "transfer signal") to the gate TX of the transfer transistor 320 to transfer the charge V1 to the floating diffusion region 306, Amplifying the charge V1 across the source follower transistor 340, selecting a pixel circuit 300 for outputting and discharging a charge (representing a signal V OPIX_SIG1 of the charge V1) by applying a signal to the gate RS of the column selection transistor 350 Output to line 308. The sample and hold circuit 1082 (FIG. 8) stores the amplified first pixel signal V OPIX_SIG1 by a second sample and hold signal SH2 (as shown in FIG. 7) and sets the differential voltage signal V OPIX_DIF1 = (V OPIX_RST_1 -V OPIX_SIG1 ) Output to a analog to digital converter 1086 (Figure 8). Analog to digital converter 1086 digitized differential signal V OPIX_DIF1, and the supply via the digitized pixel signals to an image processor V OPIX_DIF1 1088 (FIG. 8).

Also during step 606, and simultaneously with the transfer and sampling of V OPIX_DIF1 , a second photogenerated charge (referred to as V2) is accumulated at photodetector 302 during a second exposure period T2. As shown in FIG. 7, the second exposure period T2 has a duration that is shorter than the first exposure period T1, and thus, less charge is typically accumulated on the photodetector 302 during the second exposure period T2.

In step 608, the second photo-generated charge V2 is transferred to the storage region 310 by applying a signal to the gate SG of the storage transistor 310. Also during step 608, the floating diffusion region 306 is reset by activating the gate RST of the reset transistor 330, and the pixel reset signal V OPIX_RST_2 is sampled by crossing the source follower transistor 340 amplifies the reset voltage stored in the floating diffusion region 306, and selects the pixel circuit 300 for outputting and outputting the pixel reset signal V OPIX_RST_2 to the row line by applying a signal to the gate RS of the column selection transistor 350. On 308. By activating the first sample and hold signal SH1 (shown in FIG. 7) by the sample and hold circuit 1082 (FIG. 8) to reset the signal V OPIX_RST_2 sampled and stored pixel.

In step 610, similar to a typical linear pixel, the second photogenerated charge V2 is sampled by applying a signal to the gate TX of the transfer transistor 320 to transfer the charge V2 to the floating diffusion region 306, The charge V2 is amplified across the source follower transistor 340, and the pixel circuit 300 is selected for output and output of the charge V2 to the line 308 by applying a signal to the gate RS of the column select transistor 350. Sample and hold circuits 1082 (FIG. 8) by activating the second sample and hold signal SH2 (shown in FIG. 7) for storing the amplified second pixel reset signal V OPIX_SIG2, and the differential voltage signal V OPIX_DIF2 = ( V OPIX_RST_2 -V OPIX_SIG2 ) is output to a analog to digital converter 1086 (Fig. 8). The analog to digital converter 1086 digitizes the differential signal V OPIX_DIF2 and supplies the digitized pixel signal to an image processor 1088 (FIG. 8).

In step 612, image processor 1088 determines pixel value V OPIX according to Equation 2:

Wherein N is the ratio of the exposure period T1/T2, and VTH_MIN is one of the minimum threshold voltages of the pixel circuit 300 (FIG. 3). Therefore, as shown in Equation 2, if there is no saturation of the photodetector 302 during the first exposure period T1, then V OPIX =V OPIX_DIF1 . If V OPIX_DIF1 is less than the minimum threshold voltage V TH — MIN , there is no saturation of the photodetector 302 during the first exposure period T1 . If V OPIX_DIF1 is greater than the minimum threshold voltage V TH_MIN , but the normalized value of V OPIX_DIF 2 (ie, N *V OPIX_DIF2 ) is less than V OPIX_DIF1 , then there is no saturation of the photodetector 302 during the first exposure period T1 . It is thus indicated that the photodetector 302 continues to generate charge during the entire exposure period T1.

However, if the normalized value of V OPIX_DIF2 (i.e., N *V OPIX_DIF2 ) is greater than V OPIX_DIF1 , then this indication saturation does occur in photodetector 302 during the first exposure period T1. The sampled voltage V OPIX_DIF2 corresponding to the second photo-generated charge V2 is normalized for the first exposure period T1. Thus, no line buffers and non-overlapping samples of the charge generated during the two exposure periods are required (as required in the prior art dual exposure mode). In an alternative embodiment, may be determined in pixel value V OPIX analog domain before digitization differential signal V OPIX_DIF1,2.

The operational methods 400, 600 provide high dynamic range operation of the pixel circuit 300. Pixel circuit 300 and associated methods of use (including methods 400 and 600) can be implemented as part of an imager or imager system. FIG. 8 illustrates a block diagram of a CMOS imager 1000 having a pixel array 1070 that includes a plurality of pixels configured in a predetermined number of rows and columns. Each pixel (at least one of which includes a photo-electrical sensor 302, a storage region 304, a storage transistor 310, a transfer transistor 320, and optionally an anti-overflow transistor 360, as shown in FIG. 3) also has a corresponding The readout circuitry is shown in pixel circuit 300 of FIG. Alternatively, as is well known in the art, the pixels can share readout circuitry, such as in a common component pixel array ("CEPA") configuration. The pixel circuits in pixel array 1070 are configured in accordance with any of the embodiments set forth above.

The pixel values generated as described above in one of methods 400 and 600 are outputted column by column in response to a list of address decoders 1074 being activated by control signals from column drivers 1072. Row driver 1078 and row address decoder 1080 are also used to selectively activate individual pixel rows by applying a signal to the gate RS of corresponding column select transistor 350 (Fig. 3). An imager control circuit 1076 controls the address decoders 1074, 1080 to select the appropriate columns and row lines for pixel value readout. Control circuit 1076 also controls column and row driver circuits 1072, 1078 such that a drive voltage can be applied to gate SG of storage transistor 310 and gate TX of transfer transistor 320 (FIG. 3) and optional anti-corona transistor The gate of 360 is AB. The gates SG, TX, and RS can be configured for rolling shutter operation or global shutter operation.

As explained above with respect to methods 400 and 600, in the embodiments set forth above, the readout circuitry associated with each pixel outputs a reset signal V OPIX_RST_1, 2 and a respective first and second sampled charge V. OPIX_SIG1, 2 both. The samples are sampled, held, and amplified by a sample and hold circuit 1082 in accordance with a correlated double sampling ("CDS") scheme. The sample and hold circuit 1082 outputs the amplified pixel reset and video signals V OPIX_RST1 , V OPIX_SIG1 , V OPIX_RST2 , V OPIX_SIG2 . The difference V OPIX_DIF2 = (V OPIX_RST_2 - V OPIX_SIG1, 2 ) between each individual output V OPIX_RST_1, 2 and V OPIX_SIG1 , 2 represents the actual pixel output in which the common mode noise is eliminated. The differential amplifier 1084 generates a differential signal V OPIX_DIF1,2 for each voltage read from the pixel array 1070. The differential signals are digitized by analog to digital converter 1086. Analog to digital converter 1086 supplies the digitized pixel signals to image processor 1088, which determines each pixel value V OPIX_SIG according to Equation 1 or Equation 2 set forth above in connection with methods 400 and 600, respectively, and forms Output a digital image.

The imager 1000 and associated methods of use described above can be used in any system employing a CMOS imager device, including but not limited to a computer system, camera system, scanner, machine vision, vehicle navigation, video telephony, Surveillance systems, autofocus systems, star tracking systems, motion detection systems, image stabilization systems, and other imaging systems. Exemplary digital camera systems in which the above embodiments may be used include both still digital cameras and video digital cameras, cellular telephone cameras, handheld personal digital assistant (PDA) cameras, and other types of cameras.

FIG. 9 shows one such system 1100 that is part of a digital camera 1191. System 1100 includes an imager 1000 that includes a pixel array having at least one pixel circuit (eg, pixel circuit 300) configured to be used according to at least one of methods 400 and/or 600 as set forth above One operates. System 1100 generally includes a processing unit 1192 (e.g., a microprocessor) that controls system functions and communicates with an input/output (I/O) device 1196 via a bus 1193. Imager 1000 is also in communication with processing unit 1192 via bus bar 1193. System 1100 also includes random access memory (RAM) 1194 and may include removable memory 1198 (eg, flash memory) that also communicates with processing unit 1192 via bus 1193. Lens 1195 focuses an image on one of pixel arrays 1070 of imager 1000 when shutter release button 1190 is pressed.

System 1100 can alternatively be part of a larger processing system (eg, a computer). Via bus 1193, system 1100 communicates with other computer components in an illustrative manner, including but not limited to a hard drive (not shown) and/or one or more removable media devices 1198. The imager 1000 can be combined with a processor (eg, a central processing unit, a digital signal processor, or a microprocessor) with or without a single integrated circuit or on a different wafer than the processor. Memory storage.

100. . . Pixel circuit

102. . . Photoelectric detector

106. . . Floating diffusion area

108. . . Line

120. . . Transfer transistor

130. . . Reset transistor

140. . . Source follower transistor

150. . . Column selection transistor

200. . . Pixel circuit

260. . . Anti-bright overflow transistor

262. . . Bungee area

300. . . Pixel circuit

302. . . Photoelectric detector

304. . . Storage area

306. . . Floating diffusion area

308. . . Line

310. . . Storage transistor

320. . . Transfer transistor

330. . . Reset transistor

340. . . Source follower transistor

350. . . Column selection transistor

360. . . Anti-bright overflow transistor

362. . . Anti-high light overflow bungee area

1000. . . Imager

1070. . . Pixel array

1072. . . Column driver

1074. . . Column address decoder

1076. . . Imager control circuit

1078. . . Line driver

1080. . . Row address decoder

1082. . . Sampling and holding circuit

1084. . . Differential amplifier

1086. . . Analog to digital converter

1088. . . Image processor

1100. . . system

1190. . . Shutter release button

1191. . . Digital camera

1192. . . Processing unit

1193. . . Busbar

1194. . . Random access memory (RAM)

1195. . . lens

1196. . . Input/output (I/O) device

1198. . . Removable memory

AB. . . Gate

RST. . . Gate

RS. . . Gate

SG. . . Gate

SH1. . . First sample and hold signal

SH2. . . Second sample and hold signal

TX. . . Gate

V AA . . . Array pixel supply voltage

V OPIX . . . output signal

Figure 1 shows a conventional 4T pixel circuit;

Figure 2 shows a conventional 5T pixel circuit with a high-reflective transistor;

3 shows a pixel circuit having a storage transistor and an optional anti-overfill transistor that is configured to operate in accordance with the embodiments set forth herein;

4 illustrates a method of operating a pixel circuit having one of a storage transistor and an anti-high-gloss transistor for improving high dynamic operation in accordance with one embodiment set forth herein;

Figure 5 illustrates a timing diagram of a pixel circuit operating in accordance with the method illustrated in Figure 4;

6 illustrates a method of operating one of the pixel circuits of one of the storage transistors for improving high dynamic operation in accordance with one embodiment set forth herein;

Figure 7 illustrates a timing diagram of a pixel circuit operating in accordance with the method illustrated in Figure 6;

Figure 8 is a block diagram of an imager in accordance with one embodiment of the disclosed embodiment;

9 is a block diagram of one of the camera systems in accordance with one disclosed embodiment.

(no component symbol description)

Claims (39)

  1. A method of operating a pixel circuit, comprising: generating a first photo-generated charge in at least one of the photoelectric conversion regions during a first exposure period; transferring at least a portion of the first photo-generated charge to a storage region; Generating a second photo-generated charge in the at least one photoelectric conversion region during a second exposure period; sampling the at least a portion of the first photo-generated charge during the second exposure period; transferring the second photo-generated charge to the storage region And sampling the second photogenerated charge.
  2. The method of claim 1, wherein the first exposure time is longer than the second exposure time.
  3. The method of claim 1, further comprising: transferring the excess portion of the first photo-generated charge above a threshold voltage to an opposite charge before transferring the at least a portion of the first photo-generated charge to the storage region The area.
  4. The method of claim 1, further comprising: determining, by a processor, an output pixel signal based on whether the photoelectric conversion region is saturated during the first exposure period.
  5. The method of claim 4, wherein the output pixel signal corresponds to one of the sampled pixel signals of the first photo-generated charge when the photoelectric conversion region is not saturated during the first exposure period.
  6. The method of claim 4, wherein when the photoelectric conversion region is in the first exposure The output pixel signal is normalized to a pixel signal corresponding to one of the second photo-generated charges when saturated during the photoperiod.
  7. The method of claim 4, wherein the output pixel signal is normalized to the pixel corresponding to the at least one of the second photogenerated charge and the first photogenerated charge when the photoelectric conversion region is saturated during the first exposure period signal.
  8. The method of claim 3, further comprising: determining, by a processor, an output pixel signal based on whether the photoelectric conversion region is saturated during the first exposure period, wherein the processor determines the output pixel signal according to Equation 1: Wherein V OPIX is the output pixel signal, V OPIX_DIF1 is the sampled portion of the first photogenerated charge, V TH — MIN is a minimum threshold voltage of the pixel circuit, V OPIX — DIF 2 is the sampled second photogenerated charge, and N The ratio of the first exposure period to the second exposure period.
  9. The method of claim 1, further comprising: determining, by a processor, an output pixel signal based on whether the photoelectric conversion region is saturated during the first exposure period, wherein the processor determines the output pixel signal according to Equation 2: Wherein V OPIX is the output pixel signal, V OPIX_DIF1 is the sampled portion of the first photogenerated charge, V TH — MIN is a minimum threshold voltage of the pixel circuit, V OPIX — DIF 2 is the sampled second photogenerated charge, and N The ratio of the first exposure period to the second exposure period.
  10. The method of claim 1, wherein sampling the first and second photogenerated charges further comprises performing a correlated double sampling of the at least a portion of the first photogenerated charge and the second photogenerated charge.
  11. A pixel circuit comprising: a photoelectric conversion region for generating a first photo-generated charge during a first exposure period and a second photo-generated charge during a second exposure period; a storage transistor, which will The photoelectric conversion region is coupled to a first storage region; a transfer transistor that connects the first storage region to a second storage region; and a readout circuit configured to read out corresponding to the first light a first voltage of at least a portion of the charge and a second voltage corresponding to the second photo-generated charge, wherein: the storage transistor is configured to: at least a portion of the first photo-generated charge after the first exposure period Transferring to the first storage region; the transfer transistor configured to transfer the at least a portion of the first photogenerated charge to the second storage region; The storage transistor is configured to transfer the second photo-generated charge to the first storage region after the second exposure period; the transfer transistor is configured to transfer the second photo-generated charge to the second storage region And the readout circuitry is configured to perform correlated double sampling of the first and second photogenerated charges.
  12. A pixel circuit as claimed in claim 11, further comprising: an anti-overflowing transistor that connects the photoelectric conversion region to a drain region, the anti-glare transistor configured to be transferred after the first exposure period One of the first photogenerated charges is an excess.
  13. A pixel circuit as claimed in claim 12, wherein the anti-glare transistor is configured to partially turn the excess portion.
  14. The pixel circuit of claim 13, wherein the anti-overfill transistor is configured to retain substantially all of the first photo-generated charge when the first photo-generated charge is less than or equal to a threshold voltage In the photoelectric conversion area.
  15. The pixel circuit of claim 13, wherein the anti-overfill transistor is configured to retain the first photo-generated charge to be equal to one of the threshold voltages in the first portion of the threshold voltage if the first photo-generated charge is greater than a threshold voltage And transferring, to the drain region, the second portion of the first photo-generated charge that is approximately equal to one of the amount of the first photo-generated charge exceeding the threshold voltage.
  16. The pixel circuit of claim 14, wherein the threshold voltage corresponds to a level of one of the anti-glare signals received at one of the gates of the anti-bright overflow transistor.
  17. A pixel circuit as claimed in claim 11, wherein the readout circuit is configured to read the first photogenerated charge during the second integration period.
  18. A pixel circuit as claimed in claim 11, wherein the pixel circuit is configured to operate in accordance with a dual exposure mode.
  19. The pixel circuit of claim 12, wherein the pixel circuit is configured to operate in accordance with a lateral overflow mode.
  20. An imager comprising: a pixel circuit comprising: a photoelectric conversion region for generating a first photo-generated charge during a first exposure period and a second photo-generated charge during a second exposure period; a storage transistor coupled to the first storage region; a transfer transistor coupled to the first storage region; and a readout circuit configured to read And a second voltage corresponding to at least a portion of the first photo-generated charge and a second voltage corresponding to the second photo-generated charge; a processor configured to determine and output corresponding to the first and second a pixel signal of a photogenerated charge; and a control circuit electrically coupled to the pixel circuit, the control circuit configured to: provide a first stored signal to one of the gates of the storage transistor for the first exposure The at least one of the first photogenerated charges after the cycle Partially transferring to the first storage region; providing a first transfer signal to one of the gates of the transfer transistor to transfer the at least a portion of the first photo-generated charge to the second storage region; Provided to the readout circuit, the readout circuit provides correlated double sampling of the at least a portion of the first photogenerated charge; providing a second stored signal to the gate of the storage transistor for the second exposure period And transferring the second photo-generated charge to the first storage region; providing a second transfer signal to the gate of the transfer transistor to transfer the second photo-generated charge to the second storage region; and A read signal is provided to the readout circuit, the readout circuit providing correlated double sampling of the second photogenerated charge.
  21. The imager of claim 20, wherein the processor is configured to output a pixel signal based on the first photo-generated charge when the photoelectric conversion region is not saturated during the first exposure period.
  22. The imager of claim 20, wherein the processor is configured to output a normalized pixel signal based on the second photo-generated charge when the photoelectric conversion region is saturated during the first exposure period.
  23. The imager of claim 20, wherein the processor is configured to output a normalized pixel signal based on the first and second photo-generated charges when the photoelectric conversion region is saturated during the first exposure period.
  24. The imager of claim 20, wherein the processor is configured to output a pixel signal according to Equation 2: Wherein V OPIX is the output pixel signal, V OPIX_DIF1 is the sampled portion of the first photogenerated charge, V TH — MIN is a minimum threshold voltage of the pixel circuit, V OPIX — DIF 2 is the sampled second photogenerated charge, and N The ratio of the first exposure period to the second exposure period.
  25. The imager of claim 20, wherein the pixel circuit further comprises an anti-overflow transistor that connects the photoelectric conversion region to a drain region, the control circuit being further configured to apply a primary antibody A highlight overflow signal is provided to one of the gates of the anti-overflow transistor to transfer an excess of the first photo-generated charge after the first exposure period, and the processor is configured to output a pixel signal according to Equation 1: Wherein V OPIX is the output pixel signal, V OPIX_DIF1 is the sampled portion of the first photogenerated charge, V TH — MIN is a minimum threshold voltage of the pixel circuit, V OPIX — DIF 2 is the sampled second photogenerated charge, and N The ratio of the first exposure period to the second exposure period.
  26. A method of operating an imager in a lateral overflow mode, the method comprising: And accumulating a first photo-generated charge in a photo-sensitizer during a first exposure period; if the first photo-generated charge exceeds a threshold voltage, transferring an excess of the first photo-generated charge to a high-intensity overflow a drain region of the transistor; transferring a remaining portion of the first photo-generated charge to a first storage region; accumulating a second photo-generated charge in the photo-sensitizer during a second exposure period; The remaining portion of the first photo-generated charge is sampled during a second exposure period; the second photo-generated charge is transferred to the first storage region; and the second photo-generated charge is sampled.
  27. The method of claim 26, wherein the remaining portion is substantially equal to the threshold voltage.
  28. The method of claim 26, wherein the remaining portion is substantially all of the first photogenerated charge.
  29. The method of claim 26, wherein the first exposure time is longer than the second exposure time.
  30. The method of claim 29, wherein the first exposure time is approximately twice as long as the second exposure time.
  31. The method of claim 26, further comprising: determining and outputting one of the remaining portions corresponding to the first photo-generated charge if the photoelectric conversion region is not saturated during the first exposure period Once the sample voltage is applied.
  32. The method of claim 26, further comprising: determining and outputting a normalized voltage if the photoelectric conversion region is saturated during the first exposure period.
  33. The method of claim 32, wherein determining the normalized voltage comprises: calculating a difference between the second sampled voltage corresponding to the sampled second photogenerated charge and the remaining portion of the sample; and using the first exposure The ratio of the period to the duration of the second exposure time is multiplied by the difference.
  34. A method of operating an imager in a dual exposure mode, the method comprising: accumulating a first photo-generated charge in a photo-electrical sensor during a first exposure period; transferring the first photo-generated charge to a first storage a region; accumulating a second photo-generated charge in the photo-sensitizer during a second exposure period; sampling the first photo-generated charge during the second exposure period; transferring the second photo-generated charge to the first a storage area; and sampling the second photogenerated charge.
  35. The method of claim 34, wherein the first exposure time is longer than the second exposure time.
  36. The method of claim 34, wherein the first exposure time is approximately twice as long as the second exposure time.
  37. The method of claim 34, further comprising: If the photoelectric conversion region is not saturated during the first exposure period, a first sampled voltage corresponding to one of the first photogenerated charges is output.
  38. The method of claim 34, further comprising: determining and outputting a normalized voltage if the photoelectric conversion region is saturated during the first exposure period.
  39. The method of claim 38, wherein determining the normalized voltage comprises multiplying a second sampled voltage corresponding to one of the second photo-generated charges by a ratio of one of the first exposure period to the duration of the second exposure period.
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