TWI424742B - Methods and apparatus for high dynamic operation of a pixel cell - Google Patents
Methods and apparatus for high dynamic operation of a pixel cell Download PDFInfo
- Publication number
- TWI424742B TWI424742B TW099106674A TW99106674A TWI424742B TW I424742 B TWI424742 B TW I424742B TW 099106674 A TW099106674 A TW 099106674A TW 99106674 A TW99106674 A TW 99106674A TW I424742 B TWI424742 B TW I424742B
- Authority
- TW
- Taiwan
- Prior art keywords
- photo
- charge
- exposure period
- transistor
- generated charge
- Prior art date
Links
- 238000000034 method Methods 0.000 title claims description 58
- 238000012546 transfer Methods 0.000 claims description 53
- 238000006243 chemical reaction Methods 0.000 claims description 29
- 230000000875 corresponding effect Effects 0.000 claims description 24
- 238000005070 sampling Methods 0.000 claims description 23
- 229920006395 saturated elastomer Polymers 0.000 claims description 14
- 230000009977 dual effect Effects 0.000 claims description 7
- 230000002596 correlated effect Effects 0.000 claims description 5
- 230000010354 integration Effects 0.000 claims description 4
- 239000003504 photosensitizing agent Substances 0.000 claims 3
- 238000009792 diffusion process Methods 0.000 description 36
- 230000003213 activating effect Effects 0.000 description 7
- 238000010586 diagram Methods 0.000 description 7
- 238000012545 processing Methods 0.000 description 6
- 239000000872 buffer Substances 0.000 description 4
- 238000003384 imaging method Methods 0.000 description 4
- 230000004044 response Effects 0.000 description 3
- 230000007704 transition Effects 0.000 description 3
- VZEUMRXJWIAEOK-UHFFFAOYSA-N 1-(3,5-dichloro-2,6-dihydroxy-4-methoxyphenyl)pentan-1-one Chemical compound CCCCC(=O)C1=C(O)C(Cl)=C(OC)C(Cl)=C1O VZEUMRXJWIAEOK-UHFFFAOYSA-N 0.000 description 2
- 238000009825 accumulation Methods 0.000 description 2
- 230000001413 cellular effect Effects 0.000 description 2
- 238000007599 discharging Methods 0.000 description 2
- 230000006870 function Effects 0.000 description 2
- 230000008569 process Effects 0.000 description 2
- 238000005096 rolling process Methods 0.000 description 2
- 239000000758 substrate Substances 0.000 description 2
- 101100420776 Arabidopsis thaliana SYN1 gene Proteins 0.000 description 1
- VUDQSRFCCHQIIU-UHFFFAOYSA-N DIF1 Natural products CCCCCC(=O)C1=C(O)C(Cl)=C(OC)C(Cl)=C1O VUDQSRFCCHQIIU-UHFFFAOYSA-N 0.000 description 1
- 101150001108 DIF1 gene Proteins 0.000 description 1
- 101100396286 Homo sapiens IER3 gene Proteins 0.000 description 1
- 102100036900 Radiation-inducible immediate-early gene IEX-1 Human genes 0.000 description 1
- 230000003321 amplification Effects 0.000 description 1
- 238000003491 array Methods 0.000 description 1
- 230000004888 barrier function Effects 0.000 description 1
- 210000000746 body region Anatomy 0.000 description 1
- 230000008859 change Effects 0.000 description 1
- 238000004891 communication Methods 0.000 description 1
- 230000000295 complement effect Effects 0.000 description 1
- 230000001186 cumulative effect Effects 0.000 description 1
- 238000013461 design Methods 0.000 description 1
- 238000001514 detection method Methods 0.000 description 1
- 230000005055 memory storage Effects 0.000 description 1
- 229910044991 metal oxide Inorganic materials 0.000 description 1
- 150000004706 metal oxides Chemical class 0.000 description 1
- 238000003199 nucleic acid amplification method Methods 0.000 description 1
- 230000003287 optical effect Effects 0.000 description 1
- 230000001151 other effect Effects 0.000 description 1
- 238000013139 quantization Methods 0.000 description 1
- 239000004065 semiconductor Substances 0.000 description 1
- 238000003530 single readout Methods 0.000 description 1
- 230000006641 stabilisation Effects 0.000 description 1
- 238000011105 stabilization Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
- H04N25/00—Circuitry of solid-state image sensors [SSIS]; Control thereof
- H04N25/50—Control of the SSIS exposure
- H04N25/57—Control of the dynamic range
- H04N25/58—Control of the dynamic range involving two or more exposures
- H04N25/587—Control of the dynamic range involving two or more exposures acquired sequentially, e.g. using the combination of odd and even image fields
- H04N25/589—Control of the dynamic range involving two or more exposures acquired sequentially, e.g. using the combination of odd and even image fields with different integration times, e.g. short and long exposures
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
- H04N25/00—Circuitry of solid-state image sensors [SSIS]; Control thereof
- H04N25/70—SSIS architectures; Circuits associated therewith
- H04N25/76—Addressed sensors, e.g. MOS or CMOS sensors
- H04N25/77—Pixel circuitry, e.g. memories, A/D converters, pixel amplifiers, shared circuits or shared components
- H04N25/771—Pixel circuitry, e.g. memories, A/D converters, pixel amplifiers, shared circuits or shared components comprising storage means other than floating diffusion
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
- H04N25/00—Circuitry of solid-state image sensors [SSIS]; Control thereof
- H04N25/70—SSIS architectures; Circuits associated therewith
- H04N25/71—Charge-coupled device [CCD] sensors; Charge-transfer registers specially adapted for CCD sensors
- H04N25/75—Circuitry for providing, modifying or processing image signals from the pixel array
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
- H04N25/00—Circuitry of solid-state image sensors [SSIS]; Control thereof
- H04N25/70—SSIS architectures; Circuits associated therewith
- H04N25/76—Addressed sensors, e.g. MOS or CMOS sensors
- H04N25/77—Pixel circuitry, e.g. memories, A/D converters, pixel amplifiers, shared circuits or shared components
- H04N25/778—Pixel circuitry, e.g. memories, A/D converters, pixel amplifiers, shared circuits or shared components comprising amplifiers shared between a plurality of pixels, i.e. at least one part of the amplifier must be on the sensor array itself
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
- H04N25/00—Circuitry of solid-state image sensors [SSIS]; Control thereof
- H04N25/70—SSIS architectures; Circuits associated therewith
- H04N25/76—Addressed sensors, e.g. MOS or CMOS sensors
- H04N25/78—Readout circuits for addressed sensors, e.g. output amplifiers or A/D converters
Landscapes
- Engineering & Computer Science (AREA)
- Multimedia (AREA)
- Signal Processing (AREA)
- Transforming Light Signals Into Electric Signals (AREA)
- Solid State Image Pick-Up Elements (AREA)
Description
本文中所闡述之實施例大體而言係關於成像器件,且更特定而言係關於用於提供一成像器件之高動態運作之方法及裝置。The embodiments set forth herein are generally directed to imaging devices and, more particularly, to methods and apparatus for providing high dynamic operation of an imaging device.
諸多可攜式電子器件(例如相機、蜂巢式電話、個人數位助理(PDA)、MP3播放器、電腦及其他器件)包含用於捕獲影像之一成像器。一成像器之一個實例係一互補金屬氧化物半導體(「CMOS」)成像器。一CMOS成像器包含像素之一聚焦平面陣列,該等像素中之每一者包含上覆一基板用於在該基板之下伏部分中累積光生電荷之至少一個光電感測器。每一像素可包含用於將電荷自該光電感測器轉移至一儲存區域之至少一個電子器件(例如一電晶體)。Many portable electronic devices, such as cameras, cellular phones, personal digital assistants (PDAs), MP3 players, computers, and other devices, contain an imager for capturing images. An example of an imager is a complementary metal oxide semiconductor ("CMOS") imager. A CMOS imager includes a focus plane array of pixels, each of the pixels including at least one photo-electric sensor overlying a substrate for accumulating photo-generated charges in a lower portion of the substrate. Each pixel can include at least one electronic device (eg, a transistor) for transferring charge from the photo-electrical sensor to a storage region.
每一像素具有對應讀出電路,該對應讀出電路包含:至少一電荷儲存區域,其連接至輸出電晶體之閘極;一輸出源極隨耦器電晶體;一重設電晶體,其用於將該電荷儲存區域重設至一預定電荷位準;及一列控制電晶體,其用於選擇性地將該讀出電路連接至一行線路。該電荷儲存區域可構造為一浮動擴散區域。每一像素可具有獨立的讀出電路,或可採用共同元件像素架構(CEPA),其可包含共享一單個讀出電路組之多個像素。Each pixel has a corresponding readout circuit, the corresponding readout circuit comprising: at least one charge storage region connected to the gate of the output transistor; an output source follower transistor; and a reset transistor for The charge storage region is reset to a predetermined charge level; and a column of control transistors for selectively connecting the readout circuit to a row of lines. The charge storage region can be constructed as a floating diffusion region. Each pixel may have a separate readout circuit, or may employ a common element pixel architecture (CEPA), which may include multiple pixels that share a single readout circuit group.
一像素(包含一光電感測器)及其對應讀出電路在本文中統稱為一「像素電路」。在一CMOS成像器中,一像素電路之主動元件執行如下必要功能:(1)光子至電荷轉換;(2)累積影像電荷;(3)將儲存區域重設至一已知狀態;(4)伴隨電荷放大將電荷轉移至儲存區域;(5)選擇一像素電路用於讀出;及(6)輸出並放大表示一重設位準及像素電荷之一信號。可在光電荷自初始電荷累積區域移至儲存區域時放大該電荷。儲存區域處之電荷通常由一源極隨耦器輸出電晶體轉換為一像素輸出電壓。A pixel (including a photo-electric detector) and its corresponding readout circuitry are collectively referred to herein as a "pixel circuit." In a CMOS imager, the active components of a pixel circuit perform the following necessary functions: (1) photon to charge conversion; (2) cumulative image charge; (3) resetting the storage area to a known state; (4) The charge is transferred to the storage region along with the charge amplification; (5) a pixel circuit is selected for reading; and (6) the output signal is amplified and represents one of a reset level and a pixel charge. The charge can be amplified as it moves from the initial charge accumulation region to the storage region. The charge at the storage area is typically converted to a pixel output voltage by a source follower output transistor.
圖1圖解說明用於一成像器(例如一CMOS成像器)之一像素陣列中之一典型四個電晶體(4T)像素電路100。像素電路100包含具有一光電感測器102(例如,一光電感測器、光電二極體、光閘或光電導體)及一轉移電晶體120之一像素。像素電路100亦包含讀出電路,其包含組態為一浮動擴散區域106之一儲存區域、一重設電晶體130、一源極隨耦器電晶體140及一列選擇電晶體150。當藉由一轉移控制信號TX啟動轉移電晶體120時,該至少一個光電感測器102藉由轉移電晶體120連接至浮動擴散區域106。重設電晶體130連接於浮動擴散區域106與一陣列像素供應電壓VAA 之間。一重設控制信號RST用於啟動重設電晶體130,該重設電晶體將浮動擴散區域106重設至對應於陣列像素供應電壓VAA 之一預定重設電壓,如此項技術中所熟知。1 illustrates a typical four transistor (4T) pixel circuit 100 for use in a pixel array of an imager (eg, a CMOS imager). The pixel circuit 100 includes a pixel having a photo-electric detector 102 (for example, a photo-electric detector, a photodiode, a shutter or a photoconductor) and a transfer transistor 120. The pixel circuit 100 also includes a readout circuit including a storage region configured as a floating diffusion region 106, a reset transistor 130, a source follower transistor 140, and a column of select transistors 150. When the transfer transistor 120 is activated by a transfer control signal TX, the at least one photo-electric detector 102 is connected to the floating diffusion region 106 by the transfer transistor 120. The reset transistor 130 is connected between the floating diffusion region 106 and an array of pixel supply voltages V AA . A reset control signal RST is used to activate reset transistor 130, which resets floating diffusion region 106 to a predetermined reset voltage corresponding to one of array pixel supply voltages V AA , as is well known in the art.
源極隨耦器電晶體140使其閘極連接至浮動擴散區域106且連接於陣列像素供應電壓VAA 與列選擇電晶體150之間。源極隨耦器電晶體140將儲存於浮動擴散區域106處之電荷轉換成一電輸出信號。列選擇電晶體150可由一列選擇信號RS控制用於選擇性地將一輸出信號VOPIX 自源極隨耦器電晶體140輸出至行線路108上。在一CMOS成像器中,傳統地針對每一像素電路產生兩個輸出信號;一個輸出信號係在重設浮動擴散區域106之後所產生之一重設信號VOPIX_RST ,另一輸出信號係在電荷自光電感測器102轉移至浮動擴散區域106之後所產生之一影像或光信號VOPIX_SIG 。此過程通常稱為「相關雙重取樣」或「CDS」。輸出信號VOPIX_RST 、VOPIX_SIG 選擇性地儲存於一取樣及保持電路(未顯示)中。The source follower transistor 140 has its gate connected to the floating diffusion region 106 and connected between the array pixel supply voltage V AA and the column selection transistor 150. The source follower transistor 140 converts the charge stored at the floating diffusion region 106 into an electrical output signal. Column select transistor 150 can be controlled by a column of select signals RS for selectively outputting an output signal V OPIX from source follower transistor 140 to row line 108. In a CMOS imager, conventionally two output signals for each pixel circuit; a signal output line reset signal V OPIX_RST one generated after the reset floating diffusion region 106, the output signal is further based on the charge from the photoelectric One of the image or optical signals V OPIX — SIG generated after the sensor 102 transitions to the floating diffusion region 106 . This process is often referred to as "related double sampling" or "CDS." The output signals V OPIX_RST , V OPIX_SIG are selectively stored in a sample and hold circuit (not shown).
影像感測器(例如採用習用像素電路100之一影像感測器)具有一特性動態範圍。動態範圍係指可由一影像感測器容納於一單個像素資料訊框中的入射光之範圍。期望具有一影像感測器,該影像感測器具有一高動態範圍以成像產生高動態範圍入射信號之場景,例如具有向外的窗戶之室內房間、具有混合陰影及明亮太陽光之戶外場景、組合人工照明及陰影之夜間場景及諸多其他場景。The image sensor (eg, one of the image sensors of conventional pixel circuit 100) has a characteristic dynamic range. Dynamic range refers to the range of incident light that can be contained in a single pixel data frame by an image sensor. It is desirable to have an image sensor having a high dynamic range for imaging scenes that produce high dynamic range incident signals, such as indoor rooms with outward windows, outdoor scenes with mixed shadows and bright sunlight, combinations Night scenes with artificial lighting and shadows and many other scenes.
一影像感測器之動態範圍通常界定為其最大非飽和信號對其雜訊在黑暗條件下之標準偏差之比率。該動態範圍由該感測器之電荷飽和位準限制在一上限,且由用於產生數位影像之類比至數位轉換器之雜訊所施加限制及/或量化限定限制在一下限。當一影像感測器之動態範圍太小而不能容納經成像場景之光強度之變化(例如,因具有一低飽和位準)時,可發生影像失真。The dynamic range of an image sensor is typically defined as the ratio of its maximum unsaturated signal to the standard deviation of its noise in dark conditions. The dynamic range is limited by an upper limit of the charge saturation level of the sensor and is limited by a limit and/or quantization limit imposed by the analog to digital converter used to generate the digital image to a lower limit. Image distortion can occur when the dynamic range of an image sensor is too small to accommodate changes in the intensity of the imaged scene (eg, due to a low saturation level).
當於一整合週期期間所捕獲且轉換成電荷之入射光大於光電感測器之電荷儲存容量時發生與習用像素電路中之電荷產生相關聯之一問題。在一像素電路之一光電感測器曝光至大量入射光(其產生超出該光電感測器之容量之一電荷)之情形下,任何額外光子至電荷轉換將需要某一電荷洩漏逃離光電二極體區域102。通常,此洩漏導致電荷遷移至毗鄰像素電路,從而引起串擾。One problem associated with charge generation in conventional pixel circuits occurs when the incident light captured during an integration period and converted to charge is greater than the charge storage capacity of the photo-electrical sensor. In the case where one photo-inductor of a pixel circuit is exposed to a large amount of incident light (which generates a charge that exceeds the capacity of the photo-inductor), any additional photon-to-charge conversion will require some charge leakage to escape the photodiode Body region 102. Typically, this leakage causes the charge to migrate to adjacent pixel circuits, causing crosstalk.
另外,當在一整合週期期間所產生之電荷於轉移期間自光電感測器輸出至浮動擴散區域106時,少量殘餘電荷可仍留在光電感測器中。該殘餘電荷導致一後續所捕獲影像中之電荷累積過量且可導致光電感測器更快速地超出其最大容量,藉此導致過量電荷溢流至毗鄰像素。此不期望之光電感測器處之電荷溢流現象稱為高光溢出(blooming)且可在所得輸出影像中產生若干垂直及/或水平條紋。Additionally, when charge generated during an integration cycle is output from the photodetector to the floating diffusion region 106 during transfer, a small amount of residual charge may remain in the photodetector. This residual charge causes an accumulation of charge in a subsequent captured image to be excessive and can cause the photoinductor to exceed its maximum capacity more quickly, thereby causing excess charge to overflow to adjacent pixels. The phenomenon of charge overflow at this undesired photo-inductor is referred to as blooming and can produce several vertical and/or horizontal stripes in the resulting output image.
已對此高光溢出問題提出之一個解決方案係一多個曝光模式,其中取樣並組合於多個曝光週期期間於一光電感測器區域中產生之電荷。舉例而言,可以一雙重曝光模式運作一像素,其中在一第一取樣運作期間經由像素電路之輸出電路輸出於一第一曝光週期T1期間於一光電感測器區域(例如,舉例而言,圖1之光電二極體102)中產生之一第一電荷V1。接著,重設該光電感測器區域,且在一第二取樣運作期間經由像素電路之輸出電路輸出於一第二曝光週期T2期間於光電感測器區域中產生之一第二電荷V2。雖然一多個曝光運作允許像素電路100之一較高動態範圍,但多個電荷產生及取樣循環導致訊框速率降低。此外,需要用於儲存多個取樣電荷之線緩衝器,從而導致像素電路之一較高所需晶粒大小及/或一較低填充率。One solution that has been proposed for this blooming problem is a plurality of exposure modes in which the charge generated in a photodetector region during a plurality of exposure periods is sampled and combined. For example, a pixel can be operated in a double exposure mode, wherein an output circuit of the pixel circuit is output during a first sampling operation during a first exposure period T1 in a photodetector region (eg, for example, One of the first charges V1 is generated in the photodiode 102) of FIG. Then, the photodetector region is reset, and a second charge V2 is generated in the photodetector region during a second exposure period T2 via the output circuit of the pixel circuit during a second sampling operation. While a plurality of exposure operations allow for a higher dynamic range of one of the pixel circuits 100, multiple charge generation and sampling cycles result in a reduced frame rate. In addition, a line buffer for storing a plurality of sampled charges is required, resulting in a higher desired grain size and/or a lower fill rate for one of the pixel circuits.
已提出之又一解決方案係一橫向溢流模式,其中光生電荷產生於一光電轉換區域(例如,舉例而言,光電二極體102)中,且若該光生電荷超出該光電轉換區域之一預定臨限值,則該光生電荷之一過量部分在一第一曝光週期T1之後轉移至像素電路之一浮動擴散區域(舉例而言,圖1之浮動擴散區域106)。可藉由將一「軟轉移」信號施加至將該光電轉換區域與該浮動擴散區域分開之一轉移電晶體(例如,圖1之轉移電晶體120)之一閘極來轉移該過量部分,其中該軟轉移信號係小於跨越該轉移電晶體完全轉移電荷所需之電壓的一電壓。Yet another solution that has been proposed is a lateral overflow mode in which photogenerated charges are generated in a photoelectric conversion region (e.g., photodiode 102), and if the photogenerated charge exceeds one of the photoelectric conversion regions When a threshold is predetermined, an excess of the photo-generated charge is transferred to a floating diffusion region of the pixel circuit (for example, the floating diffusion region 106 of FIG. 1) after a first exposure period T1. The excess portion can be transferred by applying a "soft transfer" signal to one of the gates of the transfer transistor (e.g., transfer transistor 120 of FIG. 1) separating the photoelectric conversion region from the floating diffusion region, wherein The soft transfer signal is less than a voltage across the voltage required to fully transfer charge across the transfer transistor.
可藉由重設浮動擴散區域(例如藉由將一重設信號施加至圖1中之重設電晶體130)丟棄該過量電荷,或另一選擇為,可對該過量電荷取樣。將於第一曝光週期T1期間產生之剩餘電荷以及於一第二曝光週期T2期間產生之任一額外電荷轉移至浮動擴散區域中且經取樣以產生一輸出像素信號VOPIX_SIG 。不管是丟棄還是取樣過量電荷V1,為計及過量電荷,當以橫向溢流模式運作時必須根據像素電路之一「拐點」計算輸出像素信號VOPIX_SIG ,該拐點係轉移電晶體之軟轉移信號及/或所得臨限電壓VTH 之一因子。雖然一橫向轉移模式增加像素之動態範圍,但必須校準像素電路之該拐點(與臨限電壓VTH 相關),從而需要像素電路之一額外讀出循環,且因此導致一降低之訊框速率及/或添加之雜訊。The excess charge can be discarded by resetting the floating diffusion region (e.g., by applying a reset signal to reset transistor 130 in Figure 1), or alternatively, the excess charge can be sampled. The remaining charge generated during the first exposure period T1 and any additional charge generated during a second exposure period T2 are transferred to the floating diffusion region and sampled to produce an output pixel signal V OPIX_SIG . Regardless of whether the excess charge V1 is discarded or sampled, in order to account for the excess charge, when operating in the lateral overflow mode, the output pixel signal V OPIX_SIG must be calculated according to one of the pixel circuits "inflection point", which is the soft transfer signal of the transfer transistor and / or one of the resulting threshold voltages V TH . Although a lateral transfer mode increases the dynamic range of the pixel, the inflection point of the pixel circuit must be calibrated (associated with the threshold voltage VTH ), requiring an additional readout cycle of one of the pixel circuits, and thus resulting in a reduced frame rate and / or add noise.
已提議用於克服上述問題之又一解決方案(如圖2中所顯示且如(舉例而言)讓予給美光科技股份有限公司之美國專利第7,238,977 B2號中所闡述,該美國專利之揭示內容以全文引用的方式併入本文中)係提供具有一抗高光溢出電晶體260之一像素電路200。如圖2中所顯示,像素電路200類似於圖1之4T像素電路100,但具有一額外電晶體260。A further solution has been proposed for overcoming the above-mentioned problems (as disclosed in U.S. Patent No. 7,238,977, issued to U.S. Patent No. 7, 238, 977 The content is incorporated herein by reference in its entirety to the extent that it is provided to one of the pixel circuits 200 having an anti-overflow transistor 260. As shown in FIG. 2, pixel circuit 200 is similar to 4T pixel circuit 100 of FIG. 1, but has an additional transistor 260.
在像素電路200之一整合週期期間,當光電轉換區域102(其可係一光電感測器、光電二極體、光閘或光電導體中之任一者)變得電荷飽和時,抗高光溢出(AB)電晶體260將一些過量電荷轉移至與AB電晶體260相關聯之一汲極區262。汲極區262可(舉例而言)連接至一像素電壓VAA ,且過量電荷在不被取樣之情形下係丟棄至AB電晶體260之汲極區262中。所提出之像素電路200設計相比於習用像素電路100(圖1)有效地增加動態範圍,然而,所提出之像素電路200亦具有缺點。由於過量電荷未被取樣,因此若欲完全計及過量電荷,則讀出電壓VOPIX_SIG 必須計及跨越AB電晶體260之汲極區262轉移之過量電荷。CMOS電晶體(例如AB電晶體260)在晶圓與晶圓之間且通常在電晶體與電晶體之間具有一高的臨限電壓偏差。此偏差導致像素電路與像素電路之間所儲存電荷之量的一不確定乃因每一電晶體(包含抗高光溢出電晶體)之臨限電壓可不同。像素電路與像素電路之間電荷儲存之不同由於像素與像素之間電晶體260之障壁高度之不一致性而導致一成像器陣列中之固定型樣雜訊(FPN),從而導致降低之影像品質。During one integration period of the pixel circuit 200, when the photoelectric conversion region 102 (which may be any one of a photo-electrical sensor, a photodiode, a shutter, or a photoconductor) becomes charged saturated, it is resistant to blooming (AB) The transistor 260 transfers some excess charge to one of the drain regions 262 associated with the AB transistor 260. The drain region 262 can be connected, for example, to a pixel voltage V AA , and the excess charge is discarded into the drain region 262 of the AB transistor 260 without being sampled. The proposed pixel circuit 200 design effectively increases the dynamic range compared to the conventional pixel circuit 100 (FIG. 1), however, the proposed pixel circuit 200 also has disadvantages. Since the excess charge is not sampled, the readout voltage V OPIX_SIG must account for the excess charge transferred across the drain region 262 of the AB transistor 260 if the excess charge is to be fully accounted for. A CMOS transistor (e.g., AB transistor 260) has a high threshold voltage deviation between the wafer and the wafer and typically between the transistor and the transistor. This bias causes an uncertainty in the amount of charge stored between the pixel circuit and the pixel circuit because the threshold voltage of each transistor (including the anti-brightout transistor) can be different. The difference in charge storage between the pixel circuit and the pixel circuit results in a fixed pattern noise (FPN) in the imager array due to the inconsistency in the barrier height of the transistor 260 between the pixel and the pixel, resulting in reduced image quality.
一最佳像素電路具有一高動態範圍(其具有一可預測回應)、一低晶粒大小及高填充率、一高訊框速率之潛在可能及低雜訊。因此,需要具有經改良飽和回應及較低高光溢出潛在可能但具有降低之由上文所闡述之先前所提出解決方案導致其他效應之潛在可能之一像素電路。An optimal pixel circuit has a high dynamic range (which has a predictable response), a low die size and high fill rate, a high frame rate potential, and low noise. Therefore, there is a need for a pixel circuit that has the potential for improved saturation response and lower blooming potential but that has the potential to cause other effects resulting from the previously proposed solutions set forth above.
於以下詳細說明中,參照其中可實踐本發明之各種具體實施例。為使熟習此項技術者能夠實踐本發明,充分詳細地闡述此等實施例,且應理解,亦可採用其他實施例,且可在不背離本發明之精神或範疇之情形下作出結構及邏輯改變。In the following detailed description, reference is made to the specific embodiments The embodiments are described in sufficient detail to enable those skilled in the art to practice the invention. It is understood that other embodiments may be employed, and the structure and logic may be made without departing from the spirit or scope of the invention. change.
本揭示內容包含經組態用於改良高動態範圍運作之一像素電路之實施例。該像素電路及運作本文中所闡述之像素電路之方法藉由以下方式來提供增加之動態範圍:取樣可超出一光電轉換區域之一容量之一光生電荷,同時不需要臨限值校準(如上文所闡述之橫向溢流模式中所要求)或者額外線緩衝器或多個非重疊取樣週期(如上文所闡述之雙重曝光模式中所要求)。實施例包含:一像素電路,其具有位於光電轉換區域與另一儲存區域之間的經組態以由一儲存電晶體連接之一儲存區域;以及以橫向溢流及雙重曝光模式運作該像素電路之方法。The present disclosure includes embodiments of a pixel circuit configured to improve high dynamic range operation. The pixel circuit and method of operating the pixel circuit described herein provide an increased dynamic range by sampling a photo-generated charge that exceeds one of the capacitances of one of the photoelectric conversion regions without the need for threshold calibration (eg, The required horizontal buffer mode or the additional line buffer or multiple non-overlapping sampling periods (as required in the double exposure mode set forth above). Embodiments include: a pixel circuit having a storage region between a photoelectric conversion region and another storage region configured to be connected by a storage transistor; and operating the pixel circuit in a lateral overflow and double exposure mode The method.
圖3顯示經組態用於根據本文中所闡述之實施例運作之一像素電路300。像素電路300包含一光電感測器302(例如,一光電感測器、光電二極體、光閘或光電導體)及一轉移電晶體320。像素電路300亦包含讀出電路,其包含組態為一浮動擴散區域306之一讀出儲存區域、一重設電晶體330、一源極隨耦器電晶體340及一列選擇電晶體350。像素電路300亦包含用於儲存來自光電感測器302之光生電荷之一儲存區域304。像素電路300亦可包含一抗高光溢出電晶體360,該抗高光溢出電晶體在一抗高光溢出信號施加至抗高光溢出電晶體360之閘極AB時將光電感測器302連接至一抗高光溢出汲極區域362。抗高光溢出汲極區域362可連接至一陣列像素供應電壓VAA 或在電荷方面與產生於光電感測器302中之光生電荷相反之另一電壓。FIG. 3 shows a pixel circuit 300 configured to operate in accordance with the embodiments set forth herein. The pixel circuit 300 includes a photo-electric detector 302 (for example, a photo-electric detector, a photodiode, a shutter or a photoconductor) and a transfer transistor 320. The pixel circuit 300 also includes a readout circuit that includes a readout storage region configured as a floating diffusion region 306, a reset transistor 330, a source follower transistor 340, and a column of select transistors 350. The pixel circuit 300 also includes a storage area 304 for storing photo-generated charges from the photo-inductor 302. The pixel circuit 300 can also include an anti-bright overflow transistor 360 that connects the photo-inductor 302 to a high-intensity highlight when an anti-brightness signal is applied to the gate AB of the anti-overflow transistor 360. Overflow bungee area 362. The anti-bright drain drain region 362 can be connected to an array of pixel supply voltages V AA or another voltage that is opposite in charge to the photogenerated charge generated in photodetector 302.
儲存區域304藉由儲存電晶體310(其可組態為一全域快門電晶體)與光電感測器302分開。光電感測器302在施加至閘極SG之一儲存控制信號啟動儲存電晶體310時連接至儲存區域304。儲存電晶體310之閘極SG可組態為一全域快門閘極,其中同時運作一陣列之所有像素之所有快門閘極310。儲存區域304在施加至閘極TX之一轉移控制信號啟動轉移電晶體320時藉由轉移電晶體320連接至浮動擴散區域306。重設電晶體330連接於浮動擴散區域306與陣列像素供應電壓VAA 之間。施加至閘極RST之一重設控制信號用於啟動重設電晶體330,該重設電晶體將浮動擴散區域306重設至一已知狀態(亦即,至對應於陣列像素供應電壓VAA 之一預定重設電壓)。The storage area 304 is separated from the photodetector 302 by a storage transistor 310 (which can be configured as a global shutter transistor). Photodetector 302 is coupled to storage region 304 when a storage control signal is applied to one of the gates SG to activate storage transistor 310. The gate SG of the storage transistor 310 can be configured as a global shutter gate in which all shutter gates 310 of all pixels of an array are simultaneously operated. The storage region 304 is coupled to the floating diffusion region 306 by the transfer transistor 320 when a transfer control signal is applied to the gate TX TX to activate the transfer transistor 320. Reset transistor 330 is connected between the floating diffusion region 306 and array pixel supply voltage V AA. A reset control signal applied to one of the gates RST is used to activate the reset transistor 330, which resets the floating diffusion region 306 to a known state (ie, to correspond to the array pixel supply voltage V AA ) A predetermined reset voltage).
源極隨耦器電晶體340使其閘極連接至浮動擴散區域306且連接於陣列像素供應電壓VAA 與列選擇電晶體350之間。源極隨耦器電晶體340將儲存於浮動擴散區域306處之電荷轉換成一電輸出信號。列選擇電晶體350可藉由將一列選擇信號施加至閘極RS控制以便選擇性地將輸出信號VOPIX (其可包含下文所闡述之運作之方法中之輸出信號VOPIX_1 或VOPIX_2 中之一者或多者)自源極隨耦器電晶體340輸出至行線路308上。可使用「相關雙重取樣」或「CDS」(如此項技術中所熟知)取樣行線路308上之輸出信號VOPIX 。The source follower transistor 340 has its gate connected to the floating diffusion region 306 and connected between the array pixel supply voltage V AA and the column selection transistor 350. Source follower transistor 340 converts the charge stored at floating diffusion region 306 into an electrical output signal. The column select transistor 350 can be controlled by applying a column of select signals to the gate RS to selectively output the output signal V OPIX (which can include one of the output signals V OPIX_1 or V OPIX_2 in the method of operation described below) One or more of the output from the source follower transistor 340 to the line 308. The output signal V OPIX on the line line 308 can be sampled using "Related Double Sampling" or "CDS" (as is well known in the art).
圖4至7圖解說明運作一像素電路(例如像素電路300)及對應成像器組件(下文參照圖8進一步闡述)之方法,其中施加信號以運作該像素電路之組件。一成像器控制電路1076(圖8)可經組態以控制列及行驅動器電路1072、1078以使得驅動電壓可施加至儲存電晶體310之閘極SG及轉移電晶體320之閘極TX(圖3)以及可選抗高光溢出電晶體360之閘極AB。閘極SG、TX及RS可經組態以用於滾動快門運作或全域快門運作。然而,下文所闡述之方法不限於其中由一控制電路控制運作之實施例,且可根據用於控制像素電路及熟習此項技術者所熟知之對應成像器組件之運作之任一器件或過程來運作。4 through 7 illustrate a method of operating a pixel circuit (e.g., pixel circuit 300) and a corresponding imager assembly (described further below with respect to Figure 8) in which a signal is applied to operate the components of the pixel circuit. An imager control circuit 1076 (Fig. 8) can be configured to control the column and row driver circuits 1072, 1078 such that a drive voltage can be applied to the gate SG of the storage transistor 310 and the gate TX of the transfer transistor 320 (Fig. 3) and optional gate AB of the anti-overflow transistor 360. The gates SG, TX, and RS can be configured for rolling shutter operation or global shutter operation. However, the methods set forth below are not limited to embodiments in which operation is controlled by a control circuit, and may be in accordance with any of the devices or processes used to control the operation of the pixel circuitry and corresponding imager components well known to those skilled in the art. Operation.
圖4圖解說明以一橫向溢流模式運作像素電路300之一方法400。圖5顯示像素電路300之對應於像素電路300根據方法400之橫向溢流模式之運作之一時序圖。FIG. 4 illustrates a method 400 of operating pixel circuit 300 in a lateral overflow mode. 5 shows a timing diagram of pixel circuit 300 corresponding to operation of pixel circuit 300 in accordance with the lateral overflow mode of method 400.
在方法400之步驟402中(圖4),在一第一曝光週期T1期間於光電感測器302處累積一第一光生電荷。第一曝光週期T1具有比下文進一步闡述之一後續第二曝光週期T2長之一持續時間。舉例而言,第一曝光週期T1可係第二曝光週期T2的兩倍長。如圖5中所顯示,在第一曝光週期T1期間(自時間t1 持續至時間t2 ),閘極SG、AB及TX係關斷的。In step 402 of method 400 (FIG. 4), a first photogenerated charge is accumulated at photodetector 302 during a first exposure period T1. The first exposure period T1 has a duration that is longer than one of the subsequent second exposure periods T2 as further explained below. For example, the first exposure period T1 may be twice as long as the second exposure period T2. FIG. 5 shows (duration from times t 1 to time t 2), a first gate SG during the exposure period T1, AB and TX lines off.
累積第一光生電荷直至第一曝光週期T1之結束(此時,如步驟404中所顯示,將一「軟轉移」信號施加至抗高光溢出電晶體360之閘極AB(圖5))。該軟轉移信號係小於完全允許電荷跨越抗高光溢出電晶體360轉移所需之量之一電壓,因此產生欲轉移至抗高光溢出電晶體360之汲極區域之一電壓量的一最小臨限電壓VTH 。若儲存於光電感測器302中之第一光生電荷低於臨限電壓VTH ,則將不跨越抗電暈電晶體360轉移電荷。若儲存於光電感測器302中之第一光生電荷大於臨限電壓VTH ,則儲存於光電感測器302中之第一光生電荷之一過量部分將轉移至抗電暈電晶體360之汲極區域,例如至陣列像素供應電壓VAA 。The first photo-generated charge is accumulated until the end of the first exposure period T1 (at this time, as shown in step 404, a "soft transfer" signal is applied to the gate AB of the anti-overfill transistor 360 (Fig. 5)). The soft transfer signal is less than one of the amount required to fully transfer the charge across the anti-overflow transistor 360, thereby producing a minimum threshold voltage to be transferred to one of the drain regions of the anti-overflow transistor 360. V TH . If the first photogenerated charge stored in photodetector 302 is below the threshold voltage VTH , the charge will not be transferred across anti-corona transistor 360. If the first photo-generated charge stored in the photo-detector 302 is greater than the threshold voltage V TH , then an excess of the first photo-generated charge stored in the photo-detector 302 will be transferred to the anti-corona transistor 360. The pole region, for example to the array pixel supply voltage V AA .
在步驟406中,藉由將一信號(亦即,一「儲存信號」)施加至儲存電晶體310之閘極SG(圖5)而將第一光生電荷之剩餘部分(亦即,原始第一光生電荷(若光生電荷小於臨限電壓VTH )或大約等於臨限電壓VTH 之一部分(若原始光生電荷大於臨限電壓VTH ))(稱為電荷V1)轉移至儲存區域。閘極SG可經組態以用於全域快門運作。In step 406, the remaining portion of the first photo-generated charge (ie, the original first) is applied to the gate SG (FIG. 5) of the storage transistor 310 by applying a signal (ie, a "storage signal"). The photogenerated charge (if the photogenerated charge is less than the threshold voltage VTH ) or approximately equal to a portion of the threshold voltage VTH (if the original photogenerated charge is greater than the threshold voltage VTH )) (referred to as charge V1) is transferred to the storage region. The gate SG can be configured for global shutter operation.
同樣在步驟406期間(或,另一選擇為,在步驟402、404或步驟402、404、406中之多於一個步驟期間),藉由將一重設信號施加至重設閘極RST來重設浮動擴散區域306,且藉由以下方式來取樣像素重設信號VOPIX_RST :跨越源極隨耦器電晶體340放大儲存於浮動擴散區域306中之重設電壓、藉由將一轉移信號施加至列選擇電晶體350之閘極RS而選擇像素電路用於輸出及將像素重設信號VOPIX_RST_1 輸出至行線路308上。藉由啟動一第一取樣及保持信號SH1(如圖5中所顯示)由取樣及保持電路1082(圖8)對像素重設信號VOPIX_RST_1 進行取樣。Also during step 406 (or, alternatively, during more than one of steps 402, 404 or steps 402, 404, 406), resetting is performed by applying a reset signal to the reset gate RST. Floating diffusion region 306, and sampling pixel reset signal V OPIX_RST by amplifying the reset voltage stored in floating diffusion region 306 across source follower transistor 340 by applying a transfer signal to the column The gate RS of the transistor 350 is selected and the pixel circuit is selected for output and the pixel reset signal V OPIX_RST_1 is output to the line line 308. The pixel reset signal V OPIX_RST_1 is sampled by the sample and hold circuit 1082 (FIG. 8) by activating a first sample and hold signal SH1 (as shown in FIG. 5).
在步驟408中,藉由以下方式來對電荷V1進行取樣:將一信號(亦即,一「轉移信號」)施加至轉移電晶體320之閘極TX以將電荷V1轉移至浮動擴散區域306、跨越源極隨耦器電晶體340放大電荷V1、藉由將一信號施加至列選擇電晶體350之閘極RS而選擇像素電路300用於輸出及將電荷V1輸出至行線路308上。取樣及保持電路1082(圖8)藉由啟動一第二取樣及保持信號SH2(如圖5中所顯示)來儲存經放大第一像素信號VOPIX_SIG1 且將差動電壓信號VOPIX_DIF1 =(VOPIX_RST_1 -VOPIX_SIG1 )輸出至一類比至數位轉換器1086(圖8)。類比至數位轉換器1086數位化差動信號VOPIX_DIF1 ,且將經數位化像素信號VOPIX_DIF1 供應至一影像處理器1088(圖8)。若光電感測器302中之原始第一光生電荷小於臨限電壓VTH ,則差動信號VOPIX_DIF1 表示對應於光電感測器302處所偵測之光量之一真實取樣電壓。若光電感測器302中之原始第一光生電荷大於臨限電壓VTH (且因此在步驟404期間跨越抗高光溢出電晶體360轉移超出臨限電壓VTH 的量),則差動信號VOPIX_DIF1 表示對應於臨限電壓VTH 之一取樣電壓。In step 408, the charge V1 is sampled by applying a signal (ie, a "transfer signal") to the gate TX of the transfer transistor 320 to transfer the charge V1 to the floating diffusion region 306, Amplifying the charge V1 across the source follower transistor 340 selects the pixel circuit 300 for outputting and outputting the charge V1 to the line line 308 by applying a signal to the gate RS of the column select transistor 350. The sample and hold circuit 1082 (FIG. 8) stores the amplified first pixel signal V OPIX_SIG1 by a second sample and hold signal SH2 (as shown in FIG. 5) and sets the differential voltage signal V OPIX_DIF1 = (V OPIX_RST_1 -V OPIX_SIG1) outputs to an analog to digital converter 1086 (FIG. 8). The analog to digital converter 1086 digitizes the differential signal V OPIX_DIF1 and supplies the digitized pixel signal V OPIX_DIF1 to an image processor 1088 (FIG. 8). If the original first photogenerated charge in the photodetector 302 is less than the threshold voltage V TH , the differential signal V OPIX — DIF1 represents a true sampled voltage corresponding to the amount of light detected at the photodetector 302 . If the original first photogenerated charge in the photodetector 302 is greater than the threshold voltage VTH (and thus transitions across the anti-overflow transistor 360 beyond the threshold voltage VTH during step 404), then the differential signal V OPIX_DIF1 Indicates a sampling voltage corresponding to one of the threshold voltages V TH .
同樣在步驟408中,且與電荷VOPIX_DIF1 之轉移及取樣同時,在一第二曝光週期T2期間於光電感測器302處累積一第二光生電荷(稱為V2)。如圖5中所顯示,第二曝光週期T2具有比第一曝光週期T1短之一持續時間(例如,T2可係T1之一半長),且因此,在第二曝光週期T2期間通常較少電荷累積於光電感測器302上,且光電感測器302不可能達到一飽和點。由於光電感測器302在第二曝光週期T2期間將通常不達到一飽和點,因此在第二曝光週期T2期間或緊接著第二曝光週期T2之後不將「軟轉移」信號施加至抗高光溢出電晶體360之閘極AB(圖5)。Also in step 408, and simultaneously with the transfer and sampling of the charge V OPIX_DIF1 , a second photogenerated charge (referred to as V2) is accumulated at the photodetector 302 during a second exposure period T2. As shown in FIG. 5, the second exposure period T2 has a duration shorter than the first exposure period T1 (eg, T2 may be one-half length of T1), and thus, generally less charge during the second exposure period T2. Accumulated on the photodetector 302, and the photodetector 302 is unlikely to reach a saturation point. Since the photodetector 302 will typically not reach a saturation point during the second exposure period T2, the "soft transition" signal is not applied to the anti-highlight overflow during the second exposure period T2 or immediately after the second exposure period T2. Gate AB of transistor 360 (Fig. 5).
在步驟410中,藉由將一信號施加至儲存電晶體310之閘極SG而將第二光生電荷V2轉移至儲存區域304。同樣在步驟410期間,藉由啟動重設電晶體330之閘極RST(圖5)來重設浮動擴散區域306,且藉由以下方式來對像素重設信號VOPIX_RST_2 進行取樣:跨越源極隨耦器電晶體340放大儲存於浮動擴散區域306中之重設電壓、藉由將一信號施加至列選擇電晶體350之閘極RS而選擇像素電路用於輸出及將像素重設信號VOPIX_RST_2 輸出至行線路308上。藉由啟動第一取樣及保持信號SH1(如圖5中所顯示)由取樣及保持電路1082(圖8)來對像素重設信號VOPIX_RST_2 進行取樣。In step 410, the second photogenerated charge V2 is transferred to the storage region 304 by applying a signal to the gate SG of the storage transistor 310. Also during step 410, the floating diffusion region 306 is reset by activating the gate RST (FIG. 5) of the reset transistor 330, and the pixel reset signal V OPIX_RST_2 is sampled by: crossing the source The coupler transistor 340 amplifies the reset voltage stored in the floating diffusion region 306, selects a pixel circuit for outputting and outputs the pixel reset signal V OPIX_RST_2 by applying a signal to the gate RS of the column selection transistor 350. On line 308. The pixel reset signal V OPIX_RST_2 is sampled by the sample and hold circuit 1082 (FIG. 8) by activating the first sample and hold signal SH1 (as shown in FIG. 5).
在步驟412中,類似於一典型線性像素,藉由以下方式來對第二光生電荷V2進行取樣:藉由將一信號施加至轉移電晶體320之閘極TX而將電荷V2轉移至浮動擴散區域306、跨越源極隨耦器電晶體340放大儲存於浮動擴散區域306中之電荷V2、藉由將一信號施加至列選擇電晶體350之閘極RS而選擇像素電路用於輸出及將電荷V2輸出至行線路308上。藉由啟動第二取樣及保持信號SH2(如圖5中所顯示)由取樣及保持電路1082(圖8)來儲存經放大第二像素重設信號VOPIX_SIG2 ,且將差動電壓信號VOPIX_DIF2 =(VOPIX_RST_2 -VOPIX_SIG2 )輸出至一類比至數位轉換器1086(圖8)。類比至數位轉換器1086數位化差動信號VOPIX_DIF2 ,且將該經數位化像素信號供應至一影像處理器1088(圖8)。In step 412, similar to a typical linear pixel, the second photogenerated charge V2 is sampled by transferring a charge V2 to the floating diffusion region by applying a signal to the gate TX of the transfer transistor 320. 306. Amplifying the charge V2 stored in the floating diffusion region 306 across the source follower transistor 340, and selecting a pixel circuit for outputting and discharging the charge V2 by applying a signal to the gate RS of the column selection transistor 350. Output to line 308. The amplified second pixel reset signal V OPIX_SIG2 is stored by the sample and hold circuit 1082 (FIG. 8) by activating the second sample and hold signal SH2 (as shown in FIG. 5), and the differential voltage signal V OPIX_DIF2 is (V OPIX_RST_2 -V OPIX_SIG2 ) is output to an analog to digital converter 1086 (Fig. 8). The analog to digital converter 1086 digitizes the differential signal V OPIX_DIF2 and supplies the digitized pixel signal to an image processor 1088 (FIG. 8).
在步驟414中,影像處理器1088(圖8)根據方程式1來確定像素值VOPIX :In step 414, image processor 1088 (FIG. 8) determines pixel value V OPIX according to Equation 1:
方程式1:Equation 1:
其中N 係曝光週期T1/T2之比率,且VTH_MIN 係像素電路300(圖3)之一最小臨限電壓。如方程式1中所顯示,所計算像素信號VOPIX 並不直接受自抗高光溢出電晶體360得出之臨限電壓VTH 影響。而是,若在第一曝光週期T1期間不存在光電感測器302之飽和,則VOPIX = VOPIX_DIF1 。若VOPIX_DIF1 小於最小臨限電壓VTH_MIN ,則在第一曝光週期T1期間不存在光電感測器302之飽和。若VOPIX_DIF1 大於最小臨限電壓VTH_MIN ,但VOPIX_DIF2 之正規化值(亦即,N *VOPIX_DIF2 )小於VOPIX_DIF1 ,則在第一曝光週期T1期間亦不存在光電感測器302之飽和,乃因此指示光感測器302在整個曝光週期T1期間繼續產生電荷。Wherein N is the ratio of the exposure period T1/T2, and VTH_MIN is one of the minimum threshold voltages of the pixel circuit 300 (FIG. 3). As shown in Equation 1, the calculated pixel signal V OPIX is not directly affected by the threshold voltage V TH derived from the anti-bright overflow transistor 360. Rather, if there is no saturation of the photodetector 302 during the first exposure period T1, then V OPIX = V OPIX_DIF1 . If V OPIX_DIF1 is less than the minimum threshold voltage V TH — MIN , there is no saturation of the photodetector 302 during the first exposure period T1 . If V OPIX_DIF1 is greater than the minimum threshold voltage V TH_MIN , but the normalized value of V OPIX_DIF 2 (ie, N *V OPIX_DIF2 ) is less than V OPIX_DIF1 , then there is no saturation of the photodetector 302 during the first exposure period T1 . It is thus indicated that the photo sensor 302 continues to generate charge during the entire exposure period T1.
然而,若VOPIX_DIF2 之正規化值(亦即,N *VOPIX_DIF2 )大於VOPIX_DIF1 ,則此指示飽和在第一曝光週期T1期間確實發生於光電感測器302中,且經取樣電壓VOPIX_DIF1 表示自抗高光溢出電晶體360得出之光電感測器302之臨限電壓VTH 。因此針對第一曝光週期T1正規化經取樣電壓VOPIX_DIF1 與VOPIX_DIF2 之間的差。不存在對臨限電壓VTH 之校準之需要(如先前技術之橫向溢流方法中所要求)。此外,由於在第二曝光週期T2期間對V1進行取樣,因此總運作時間小於此項技術中所熟知之雙重曝光模式。在一替代實施例中,可在數位化差動信號VOPIX_DIF2 之前在類比域中確定像素值VOPIX 。However, if the normalized value of V OPIX_DIF2 (ie, N *V OPIX_DIF2 ) is greater than V OPIX_DIF1 , then this indication saturation does occur in photodetector 302 during the first exposure period T1 and is represented by sampled voltage V OPIX_DIF1 The threshold voltage V TH of the photo-inductor 302 derived from the anti-bright overflow transistor 360. The difference between the sampled voltages V OPIX_DIF1 and V OPIX_DIF2 is thus normalized for the first exposure period T1. There is no need for calibration of the threshold voltage VTH (as required in the prior art lateral flooding method). Furthermore, since V1 is sampled during the second exposure period T2, the total operating time is less than the double exposure mode well known in the art. In an alternate embodiment, the pixel value V OPIX may be determined in the analog domain prior to digitizing the differential signal V OPIX — DIF2 .
圖6圖解說明以一雙重曝光模式運作像素電路300之一第二方法600。圖7顯示像素電路300對應於根據方法600之雙重曝光模式之運作之一時序圖。雖然抗高光溢出電晶體360對於方法600之雙重曝光模式未必必要,但經組態以根據方法600之雙重曝光模式運作之像素電路300之實施例亦可包含抗高光溢出電晶體360(其保持關斷(如圖7中所顯示))以提供運作之靈活性,例如經組態以根據方法400之橫向溢流模式運作之選項。FIG. 6 illustrates a second method 600 of operating pixel circuit 300 in a dual exposure mode. FIG. 7 shows a timing diagram of pixel circuit 300 corresponding to operation of the dual exposure mode in accordance with method 600. While the anti-overfill transistor 360 is not necessary for the dual exposure mode of method 600, embodiments of pixel circuit 300 configured to operate in accordance with the dual exposure mode of method 600 may also include an anti-overfill transistor 360 (which remains off) Broken (as shown in Figure 7)) to provide operational flexibility, such as an option configured to operate in accordance with the lateral overflow mode of method 400.
在方法600之步驟602中(圖6),在一第一曝光週期T1期間於光電感測器302處累積一第一光生電荷。第一曝光週期T1係比下文進一步闡述之一後續第二曝光週期T2長之一曝光週期。舉例而言,第一曝光週期T1可係第二曝光週期T2的兩倍長。在T1期間,如圖7中所顯示,閘極SG、AB及TX係關斷的。In step 602 of method 600 (FIG. 6), a first photogenerated charge is accumulated at photodetector 302 during a first exposure period T1. The first exposure period T1 is one exposure period longer than one of the subsequent second exposure periods T2 as further explained below. For example, the first exposure period T1 may be twice as long as the second exposure period T2. During T1, as shown in Figure 7, the gates SG, AB, and TX are turned off.
同樣在步驟602期間(或,在下文所闡述之步驟604期間),藉由將一重設信號施加至重設閘極RST來重設浮動擴散區域306,且藉由以下方式來對像素重設信號VOPIX_RST_1 進行取樣:跨越源極隨耦器電晶體340放大儲存於浮動擴散區域306中之重設電壓、藉由將一信號施加至列選擇電晶體350之閘極RS而選擇像素電路300用於輸出及將像素重設信號VOPIX_RST_1 輸出至行線路308上。藉由啟動一第一取樣及保持信號SH1(如圖7中所顯示)由取樣及保持電路1082(圖8)來對像素重設信號VOPIX_RST_1 進行取樣及儲存。Also during step 602 (or during step 604, described below), the floating diffusion region 306 is reset by applying a reset signal to the reset gate RST, and the pixel is reset by the following means V OPIX_RST_1 performs sampling: amplifying the reset voltage stored in the floating diffusion region 306 across the source follower transistor 340, and selecting the pixel circuit 300 by applying a signal to the gate RS of the column selection transistor 350 for The output and output of the pixel reset signal V OPIX_RST_1 to the line line 308. By starting a first sample and hold signal SH1 (shown in FIG. 7) by the sample and hold circuit 1082 (FIG. 8) to reset the signal V OPIX_RST_1 sampled and stored pixel.
在方法600之步驟604中,將一信號(亦即,一「儲存信號」)施加至儲存電晶體310之閘極SG(圖7)以將第一光生電荷(稱為電荷V1)自光電感測器302轉移至儲存區域304。閘極SG可經組態以用於全域快門運作。In step 604 of method 600, a signal (ie, a "storage signal") is applied to gate SG (FIG. 7) of storage transistor 310 to convert the first photo-generated charge (referred to as charge V1) from the photo-inductor. The detector 302 is transferred to the storage area 304. The gate SG can be configured for global shutter operation.
在步驟606中,藉由以下方式來對電荷V1進行取樣:將一信號(亦即,一「轉移信號」)施加至轉移電晶體320之閘極TX以將電荷V1轉移至浮動擴散區域306、跨越源極隨耦器電晶體340放大電荷V1、藉由將一信號施加至列選擇電晶體350之閘極RS而選擇像素電路300用於輸出及將電荷(表示電荷V1之一信號VOPIX_SIG1 )輸出至行線路308上。取樣及保持電路1082(圖8)藉由啟動一第二取樣及保持信號SH2(如圖7中所顯示)來儲存經放大第一像素信號VOPIX_SIG1 且將差動電壓信號VOPIX_DIF1 =(VOPIX_RST_1 -VOPIX_SIG1 )輸出至一類比至數位轉換器1086(圖8)。類比至數位轉換器1086數位化差動信號VOPIX_DIF1 ,且將經數位化像素信號VOPIX_DIF1 供應至一影像處理器1088(圖8)。In step 606, the charge V1 is sampled by applying a signal (ie, a "transfer signal") to the gate TX of the transfer transistor 320 to transfer the charge V1 to the floating diffusion region 306, Amplifying the charge V1 across the source follower transistor 340, selecting a pixel circuit 300 for outputting and discharging a charge (representing a signal V OPIX_SIG1 of the charge V1) by applying a signal to the gate RS of the column selection transistor 350 Output to line 308. The sample and hold circuit 1082 (FIG. 8) stores the amplified first pixel signal V OPIX_SIG1 by a second sample and hold signal SH2 (as shown in FIG. 7) and sets the differential voltage signal V OPIX_DIF1 = (V OPIX_RST_1 -V OPIX_SIG1 ) Output to a analog to digital converter 1086 (Figure 8). Analog to digital converter 1086 digitized differential signal V OPIX_DIF1, and the supply via the digitized pixel signals to an image processor V OPIX_DIF1 1088 (FIG. 8).
同樣在步驟606期間,且與VOPIX_DIF1 之轉移及取樣同時,在一第二曝光週期T2期間於光電感測器302處累積一第二光生電荷(稱為V2)。如圖7中所顯示,第二曝光週期T2具有比第一曝光週期T1短之一持續時間,且因此,在第二曝光週期T2期間通常較少電荷累積於光電感測器302上。Also during step 606, and simultaneously with the transfer and sampling of V OPIX_DIF1 , a second photogenerated charge (referred to as V2) is accumulated at photodetector 302 during a second exposure period T2. As shown in FIG. 7, the second exposure period T2 has a duration that is shorter than the first exposure period T1, and thus, less charge is typically accumulated on the photodetector 302 during the second exposure period T2.
在步驟608中,藉由將一信號施加至儲存電晶體310之閘極SG而將第二光生電荷V2轉移至儲存區域310。同樣在步驟608期間,藉由啟動重設電晶體330之閘極RST來重設浮動擴散區域306,且藉由以下方式來對像素重設信號VOPIX_RST_2 進行取樣:跨越源極隨耦器電晶體340放大儲存於浮動擴散區域306中之重設電壓、藉由將一信號施加至列選擇電晶體350之閘極RS而選擇像素電路300用於輸出及將像素重設信號VOPIX_RST_2 輸出至行線路308上。藉由啟動第一取樣及保持信號SH1(如圖7中所顯示)由取樣及保持電路1082(圖8)來對像素重設信號VOPIX_RST_2 進行取樣及儲存。In step 608, the second photo-generated charge V2 is transferred to the storage region 310 by applying a signal to the gate SG of the storage transistor 310. Also during step 608, the floating diffusion region 306 is reset by activating the gate RST of the reset transistor 330, and the pixel reset signal V OPIX_RST_2 is sampled by crossing the source follower transistor 340 amplifies the reset voltage stored in the floating diffusion region 306, and selects the pixel circuit 300 for outputting and outputting the pixel reset signal V OPIX_RST_2 to the row line by applying a signal to the gate RS of the column selection transistor 350. On 308. By activating the first sample and hold signal SH1 (shown in FIG. 7) by the sample and hold circuit 1082 (FIG. 8) to reset the signal V OPIX_RST_2 sampled and stored pixel.
在步驟610中,類似於一典型線性像素,藉由以下方式來對第二光生電荷V2進行取樣:將一信號施加至轉移電晶體320之閘極TX以將電荷V2轉移至浮動擴散區域306、跨越源極隨耦器電晶體340放大電荷V2、藉由將一信號施加至列選擇電晶體350之閘極RS而選擇像素電路300用於輸出及將電荷V2輸出至行線路308上。取樣及保持電路1082(圖8)藉由啟動第二取樣及保持信號SH2(如圖7中所顯示)來儲存經放大第二像素重設信號VOPIX_SIG2 ,且將差動電壓信號VOPIX_DIF2 =(VOPIX_RST_2 -VOPIX_SIG2 )輸出至一類比至數位轉換器1086(圖8)。類比至數位轉換器1086數位化差動信號VOPIX_DIF2 ,且將該經數位化像素信號供應至一影像處理器1088(圖8)。In step 610, similar to a typical linear pixel, the second photogenerated charge V2 is sampled by applying a signal to the gate TX of the transfer transistor 320 to transfer the charge V2 to the floating diffusion region 306, The charge V2 is amplified across the source follower transistor 340, and the pixel circuit 300 is selected for output and output of the charge V2 to the line 308 by applying a signal to the gate RS of the column select transistor 350. Sample and hold circuits 1082 (FIG. 8) by activating the second sample and hold signal SH2 (shown in FIG. 7) for storing the amplified second pixel reset signal V OPIX_SIG2, and the differential voltage signal V OPIX_DIF2 = ( V OPIX_RST_2 -V OPIX_SIG2 ) is output to a analog to digital converter 1086 (Fig. 8). The analog to digital converter 1086 digitizes the differential signal V OPIX_DIF2 and supplies the digitized pixel signal to an image processor 1088 (FIG. 8).
在步驟612中,影像處理器1088根據方程式2來確定像素值VOPIX :In step 612, image processor 1088 determines pixel value V OPIX according to Equation 2:
其中N 係曝光週期T1/T2之比率,且VTH_MIN 係像素電路300(圖3)之一最小臨限電壓。因此,如方程式2中所顯示,若在第一曝光週期T1期間不存在光電感測器302之飽和,則VOPIX =VOPIX_DIF1 。若VOPIX_DIF1 小於最小臨限電壓VTH_MIN ,則在第一曝光週期T1期間不存在光電感測器302之飽和。若VOPIX_DIF1 大於最小臨限電壓VTH_MIN ,但VOPIX_DIF2 之正規化值(亦即,N *VOPIX_DIF2 )小於VOPIX_DIF1 ,則在第一曝光週期T1期間亦不存在光電感測器302之飽和,乃因此指示光電感測器302在整個曝光週期T1期間繼續產生電荷。Wherein N is the ratio of the exposure period T1/T2, and VTH_MIN is one of the minimum threshold voltages of the pixel circuit 300 (FIG. 3). Therefore, as shown in Equation 2, if there is no saturation of the photodetector 302 during the first exposure period T1, then V OPIX =V OPIX_DIF1 . If V OPIX_DIF1 is less than the minimum threshold voltage V TH — MIN , there is no saturation of the photodetector 302 during the first exposure period T1 . If V OPIX_DIF1 is greater than the minimum threshold voltage V TH_MIN , but the normalized value of V OPIX_DIF 2 (ie, N *V OPIX_DIF2 ) is less than V OPIX_DIF1 , then there is no saturation of the photodetector 302 during the first exposure period T1 . It is thus indicated that the photodetector 302 continues to generate charge during the entire exposure period T1.
然而,若VOPIX_DIF2 之正規化值(亦即,N *VOPIX_DIF2 )大於VOPIX_DIF1 ,則此指示飽和在第一曝光週期T1期間確實發生於光電感測器302中。針對第一曝光週期T1正規化對應於第二光生電荷V2之經取樣電壓VOPIX_DIF2 。因此,不需要線緩衝器及對產生於兩個曝光週期中之電荷之非重疊取樣(如先前技術之雙重曝光模式中所要求)。在一替代實施例中,可在數位化差動信號VOPIX_DIF1,2 之前在類比域中確定像素值VOPIX 。However, if the normalized value of V OPIX_DIF2 (i.e., N *V OPIX_DIF2 ) is greater than V OPIX_DIF1 , then this indication saturation does occur in photodetector 302 during the first exposure period T1. The sampled voltage V OPIX_DIF2 corresponding to the second photo-generated charge V2 is normalized for the first exposure period T1. Thus, no line buffers and non-overlapping samples of the charge generated during the two exposure periods are required (as required in the prior art dual exposure mode). In an alternative embodiment, may be determined in pixel value V OPIX analog domain before digitization differential signal V OPIX_DIF1,2.
運作方法400、600提供像素電路300之高動態範圍運作。像素電路300及相關聯使用方法(包含方法400及600)可實施為一成像器或成像器系統之一部分。圖8圖解說明具有一像素陣列1070之一CMOS成像器1000之一方塊圖,像素陣列1070包含配置成預定數目個行及列之複數個像素。每一像素(其中之至少一者包含一光電感測器302、儲存區域304、儲存電晶體310、轉移電晶體320及視情況抗高光溢出電晶體360,如圖3中所顯示)亦具有對應讀出電路,如圖3之像素電路300中所顯示。另一選擇為,如此項技術中所熟知,像素可共享讀出電路,例如呈一共同元件像素陣列(「CEPA」)組態。根據上文所闡述之任一實施例組態像素陣列1070中之像素電路。The operational methods 400, 600 provide high dynamic range operation of the pixel circuit 300. Pixel circuit 300 and associated methods of use (including methods 400 and 600) can be implemented as part of an imager or imager system. FIG. 8 illustrates a block diagram of a CMOS imager 1000 having a pixel array 1070 that includes a plurality of pixels configured in a predetermined number of rows and columns. Each pixel (at least one of which includes a photo-electrical sensor 302, a storage region 304, a storage transistor 310, a transfer transistor 320, and optionally an anti-overflow transistor 360, as shown in FIG. 3) also has a corresponding The readout circuitry is shown in pixel circuit 300 of FIG. Alternatively, as is well known in the art, the pixels can share readout circuitry, such as in a common component pixel array ("CEPA") configuration. The pixel circuits in pixel array 1070 are configured in accordance with any of the embodiments set forth above.
當回應於一列位址解碼器1074被來自列驅動器1072之控制信號啟動時逐列輸出像素陣列1070之如上文闡述於方法400及600中之一者中所產生之像素值。行驅動器1078及行位址解碼器1080亦用於藉由將信號施加至相應列選擇電晶體350(圖3)之閘極RS而選擇性地啟動個別像素行。一成像器控制電路1076控制位址解碼器1074、1080以便選擇適當列及行線路用於像素值讀出。控制電路1076亦控制列及行驅動器電路1072、1078以使得可將驅動電壓施加至儲存電晶體310之閘極SG及轉移電晶體320之閘極TX(圖3)以及可選抗電暈電晶體360之閘極AB。閘極SG、TX及RS可經組態以用於滾動快門運作或全域快門運作。The pixel values generated as described above in one of methods 400 and 600 are outputted column by column in response to a list of address decoders 1074 being activated by control signals from column drivers 1072. Row driver 1078 and row address decoder 1080 are also used to selectively activate individual pixel rows by applying a signal to the gate RS of corresponding column select transistor 350 (Fig. 3). An imager control circuit 1076 controls the address decoders 1074, 1080 to select the appropriate columns and row lines for pixel value readout. Control circuit 1076 also controls column and row driver circuits 1072, 1078 such that a drive voltage can be applied to gate SG of storage transistor 310 and gate TX of transfer transistor 320 (FIG. 3) and optional anti-corona transistor The gate of 360 is AB. The gates SG, TX, and RS can be configured for rolling shutter operation or global shutter operation.
如上文相對於方法400及600所闡述,在上文所闡述實施例中,與每一像素相關聯之讀出電路輸出重設信號VOPIX_RST_1,2 與各別第一及第二經取樣電荷VOPIX_SIG1,2 兩者。由一取樣及保持電路1082根據一相關雙重取樣(「CDS」)方案來對該等輸出進行取樣、保持及放大。取樣及保持電路1082輸出經放大像素重設及影像信號VOPIX_RST1 、VOPIX_SIG1 、VOPIX_RST2 、VOPIX_SIG2 。每一各別輸出VOPIX_RST_1,2 與VOPIX_SIG1,2 之間的差VOPIX_DIF2 =(VOPIX_RST_2 -VOPIX_SIG1,2 )表示共同模式雜訊被消除之實際像素輸出。差動放大器1084針對自像素陣列1070讀出之每一電壓產生差動信號VOPIX_DIF1,2 。由類比至數位轉換器1086數位化該等差動信號。類比至數位轉換器1086將該等經數位化像素信號供應至影像處理器1088,其分別根據上文與方法400及600相關闡述之方程式1或方程式2確定每一像素值VOPIX_SIG ,且形成及輸出一數位影像。As explained above with respect to methods 400 and 600, in the embodiments set forth above, the readout circuitry associated with each pixel outputs a reset signal V OPIX_RST_1, 2 and a respective first and second sampled charge V. OPIX_SIG1, 2 both. The samples are sampled, held, and amplified by a sample and hold circuit 1082 in accordance with a correlated double sampling ("CDS") scheme. The sample and hold circuit 1082 outputs the amplified pixel reset and video signals V OPIX_RST1 , V OPIX_SIG1 , V OPIX_RST2 , V OPIX_SIG2 . The difference V OPIX_DIF2 = (V OPIX_RST_2 - V OPIX_SIG1, 2 ) between each individual output V OPIX_RST_1, 2 and V OPIX_SIG1 , 2 represents the actual pixel output in which the common mode noise is eliminated. The differential amplifier 1084 generates a differential signal V OPIX_DIF1,2 for each voltage read from the pixel array 1070. The differential signals are digitized by analog to digital converter 1086. Analog to digital converter 1086 supplies the digitized pixel signals to image processor 1088, which determines each pixel value V OPIX_SIG according to Equation 1 or Equation 2 set forth above in connection with methods 400 and 600, respectively, and forms Output a digital image.
上文所闡述之成像器1000及相關聯使用方法可用於採用一CMOS成像器器件之任一系統中,包含但不限於一電腦系統、相機系統、掃描儀、機器視覺、車輛導航、視訊電話、監視系統、自動聚焦系統、星體追蹤系統、運動偵測系統、影像穩定化系統及其他成像系統。其中可使用上文之實施例之實例性數位相機系統包含靜止數位相機及視訊數位相機兩者、蜂巢式電話相機、手持式個人數位助理(PDA)相機及其他類型之相機。The imager 1000 and associated methods of use described above can be used in any system employing a CMOS imager device, including but not limited to a computer system, camera system, scanner, machine vision, vehicle navigation, video telephony, Surveillance systems, autofocus systems, star tracking systems, motion detection systems, image stabilization systems, and other imaging systems. Exemplary digital camera systems in which the above embodiments may be used include both still digital cameras and video digital cameras, cellular telephone cameras, handheld personal digital assistant (PDA) cameras, and other types of cameras.
圖9顯示一個此系統1100,其係一數位相機1191之一部分。系統1100包含成像器1000,該成像器包含具有至少一個像素電路(例如像素電路300)之一像素陣列,該像素電路經組態用於根據如上文所闡述之方法400及/或600中之至少一者運作。系統1100一般而言包括一處理單元1192(例如一微處理器),其控制系統功能且經由一匯流排1193與一輸入/輸出(I/O)裝置1196通信。成像器1000亦經由匯流排1193與處理單元1192通信。系統1100亦包含隨機存取記憶體(RAM)1194,且可包含可抽換記憶體1198(例如快閃記憶體),其亦經由匯流排1193與處理單元1192通信。當按下快門釋放按鈕1190時透鏡1195在成像器1000之一像素陣列1070上聚焦一影像。FIG. 9 shows one such system 1100 that is part of a digital camera 1191. System 1100 includes an imager 1000 that includes a pixel array having at least one pixel circuit (eg, pixel circuit 300) configured to be used according to at least one of methods 400 and/or 600 as set forth above One operates. System 1100 generally includes a processing unit 1192 (e.g., a microprocessor) that controls system functions and communicates with an input/output (I/O) device 1196 via a bus 1193. Imager 1000 is also in communication with processing unit 1192 via bus bar 1193. System 1100 also includes random access memory (RAM) 1194 and may include removable memory 1198 (eg, flash memory) that also communicates with processing unit 1192 via bus 1193. Lens 1195 focuses an image on one of pixel arrays 1070 of imager 1000 when shutter release button 1190 is pressed.
系統1100可替代地係一較大處理系統(例如一電腦)之一部分。經由匯流排1193,系統1100以圖解說明方式與其他電腦組件通信,包含但不限於一硬驅動器(未顯示)及/或一個或多個可抽換媒體器件1198。成像器1000可與一處理器(例如一中央處理單元、數位信號處理器或微處理器)組合,該處理器具有或不具有一單個積體電路上或與該處理器不同之一晶片上之記憶體儲存。System 1100 can alternatively be part of a larger processing system (eg, a computer). Via bus 1193, system 1100 communicates with other computer components in an illustrative manner, including but not limited to a hard drive (not shown) and/or one or more removable media devices 1198. The imager 1000 can be combined with a processor (eg, a central processing unit, a digital signal processor, or a microprocessor) with or without a single integrated circuit or on a different wafer than the processor. Memory storage.
100...像素電路100. . . Pixel circuit
102...光電感測器102. . . Photoelectric detector
106...浮動擴散區域106. . . Floating diffusion area
108...行線路108. . . Line
120...轉移電晶體120. . . Transfer transistor
130...重設電晶體130. . . Reset transistor
140...源極隨耦器電晶體140. . . Source follower transistor
150...列選擇電晶體150. . . Column selection transistor
200...像素電路200. . . Pixel circuit
260...抗高光溢出電晶體260. . . Anti-bright overflow transistor
262...汲極區262. . . Bungee area
300...像素電路300. . . Pixel circuit
302...光電感測器302. . . Photoelectric detector
304...儲存區域304. . . Storage area
306...浮動擴散區域306. . . Floating diffusion area
308...行線路308. . . Line
310...儲存電晶體310. . . Storage transistor
320...轉移電晶體320. . . Transfer transistor
330...重設電晶體330. . . Reset transistor
340...源極隨耦器電晶體340. . . Source follower transistor
350...列選擇電晶體350. . . Column selection transistor
360...抗高光溢出電晶體360. . . Anti-bright overflow transistor
362...抗高光溢出汲極區域362. . . Anti-high light overflow bungee area
1000...成像器1000. . . Imager
1070...像素陣列1070. . . Pixel array
1072...列驅動器1072. . . Column driver
1074...列位址解碼器1074. . . Column address decoder
1076...成像器控制電路1076. . . Imager control circuit
1078...行驅動器1078. . . Line driver
1080...行位址解碼器1080. . . Row address decoder
1082...取樣及保持電路1082. . . Sampling and holding circuit
1084...差動放大器1084. . . Differential amplifier
1086...類比至數位轉換器1086. . . Analog to digital converter
1088...影像處理器1088. . . Image processor
1100...系統1100. . . system
1190...快門釋放按鈕1190. . . Shutter release button
1191...數位相機1191. . . Digital camera
1192...處理單元1192. . . Processing unit
1193...匯流排1193. . . Busbar
1194...隨機存取記憶體(RAM)1194. . . Random access memory (RAM)
1195...透鏡1195. . . lens
1196...輸入/輸出(I/O)裝置1196. . . Input/output (I/O) device
1198...可抽換記憶體1198. . . Removable memory
AB...閘極AB. . . Gate
RST...閘極RST. . . Gate
RS...閘極RS. . . Gate
SG...閘極SG. . . Gate
SH1...第一取樣及保持信號SH1. . . First sample and hold signal
SH2...第二取樣及保持信號SH2. . . Second sample and hold signal
TX...閘極TX. . . Gate
VAA ...陣列像素供應電壓V AA . . . Array pixel supply voltage
VOPIX ...輸出信號V OPIX . . . output signal
圖1顯示一習用4T像素電路;Figure 1 shows a conventional 4T pixel circuit;
圖2顯示具有一抗高光溢出電晶體之一習用5T像素電路;Figure 2 shows a conventional 5T pixel circuit with a high-reflective transistor;
圖3顯示經組態以根據本文中所闡述之實施例運作之具有一儲存電晶體及一可選抗高光溢出電晶體之一像素電路;3 shows a pixel circuit having a storage transistor and an optional anti-overfill transistor that is configured to operate in accordance with the embodiments set forth herein;
圖4圖解說明根據本文中所闡述之一實施例運作具有用於改良高動態運作之一儲存電晶體及一抗高光溢出電晶體之一像素電路之一方法;4 illustrates a method of operating a pixel circuit having one of a storage transistor and an anti-high-gloss transistor for improving high dynamic operation in accordance with one embodiment set forth herein;
圖5圖解說明一像素電路根據圖4中所闡述方法運作之一時序圖;Figure 5 illustrates a timing diagram of a pixel circuit operating in accordance with the method illustrated in Figure 4;
圖6圖解說明根據本文中所闡述之一實施例運作具有用於改良高動態運作之一儲存電晶體之一像素電路之一方法;6 illustrates a method of operating one of the pixel circuits of one of the storage transistors for improving high dynamic operation in accordance with one embodiment set forth herein;
圖7圖解說明一像素電路根據圖6中所闡述方法運作之一時序圖;Figure 7 illustrates a timing diagram of a pixel circuit operating in accordance with the method illustrated in Figure 6;
圖8係根據所揭示實施例之一成像器之一方塊圖;及Figure 8 is a block diagram of an imager in accordance with one embodiment of the disclosed embodiment;
圖9係根據所揭示實施例之一相機系統之一方塊圖。9 is a block diagram of one of the camera systems in accordance with one disclosed embodiment.
(無元件符號說明)(no component symbol description)
Claims (39)
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US12/402,933 US8184188B2 (en) | 2009-03-12 | 2009-03-12 | Methods and apparatus for high dynamic operation of a pixel cell |
Publications (2)
Publication Number | Publication Date |
---|---|
TW201106690A TW201106690A (en) | 2011-02-16 |
TWI424742B true TWI424742B (en) | 2014-01-21 |
Family
ID=42730387
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
TW099106674A TWI424742B (en) | 2009-03-12 | 2010-03-08 | Methods and apparatus for high dynamic operation of a pixel cell |
Country Status (2)
Country | Link |
---|---|
US (1) | US8184188B2 (en) |
TW (1) | TWI424742B (en) |
Families Citing this family (62)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US7616256B2 (en) * | 2005-03-21 | 2009-11-10 | Dolby Laboratories Licensing Corporation | Multiple exposure methods and apparatus for electronic cameras |
JP4494492B2 (en) * | 2008-04-09 | 2010-06-30 | キヤノン株式会社 | Solid-state imaging device and driving method of solid-state imaging device |
US20110019045A1 (en) * | 2009-07-26 | 2011-01-27 | Chi-Shao Lin | Method and apparatus for simultaneous electronic shutter action frame storage and correlated double sampling in image sensor |
KR101605046B1 (en) * | 2009-07-29 | 2016-03-21 | 삼성전자주식회사 | Single gate pixel and operating method for single gate pixel |
US9426390B2 (en) * | 2010-03-04 | 2016-08-23 | BAE Systems Imaging Solutions Inc. | CMOS imaging array with improved noise characteristics |
JP5516960B2 (en) * | 2010-04-02 | 2014-06-11 | ソニー株式会社 | Solid-state imaging device, driving method of solid-state imaging device, and electronic apparatus |
JP5460465B2 (en) * | 2010-05-25 | 2014-04-02 | キヤノン株式会社 | Photoelectric conversion device and imaging system |
JP5634194B2 (en) * | 2010-09-28 | 2014-12-03 | キヤノン株式会社 | Radiation imaging apparatus and control method thereof |
KR101728713B1 (en) * | 2010-10-08 | 2017-04-21 | (주) 지안 | Wide Dynamic Range CMOS Image Sensor and Image Sensing Method |
DE102011002824A1 (en) * | 2011-01-18 | 2012-07-19 | Fraunhofer-Gesellschaft zur Förderung der angewandten Forschung e.V. | Image sensor, imaging system and method of taking an image |
US8723975B2 (en) * | 2011-01-24 | 2014-05-13 | Aptina Imaging Corporation | High-dynamic-range imaging devices |
US8873882B2 (en) * | 2011-02-28 | 2014-10-28 | Aptina Imaging Corporation | Blooming filter for multiple exposure high dynamic range image sensors |
JP2013172210A (en) * | 2012-02-17 | 2013-09-02 | Canon Inc | Imaging device |
US9549158B2 (en) | 2012-04-18 | 2017-01-17 | Brightway Vision Ltd. | Controllable single pixel sensors |
US9723233B2 (en) | 2012-04-18 | 2017-08-01 | Brightway Vision Ltd. | Controllable gated sensor |
WO2013157001A1 (en) | 2012-04-18 | 2013-10-24 | Brightway Vision Ltd. | Mulitple gated pixel per readout |
JP6103859B2 (en) * | 2012-09-05 | 2017-03-29 | キヤノン株式会社 | Photoelectric conversion device |
US9481301B2 (en) * | 2012-12-05 | 2016-11-01 | Magna Electronics Inc. | Vehicle vision system utilizing camera synchronization |
US8773562B1 (en) * | 2013-01-31 | 2014-07-08 | Apple Inc. | Vertically stacked image sensor |
US9293500B2 (en) * | 2013-03-01 | 2016-03-22 | Apple Inc. | Exposure control for image sensors |
US9276031B2 (en) | 2013-03-04 | 2016-03-01 | Apple Inc. | Photodiode with different electric potential regions for image sensors |
US9041837B2 (en) | 2013-03-05 | 2015-05-26 | Apple Inc. | Image sensor with reduced blooming |
US9741754B2 (en) | 2013-03-06 | 2017-08-22 | Apple Inc. | Charge transfer circuit with storage nodes in image sensors |
US9549099B2 (en) * | 2013-03-12 | 2017-01-17 | Apple Inc. | Hybrid image sensor |
US9319611B2 (en) | 2013-03-14 | 2016-04-19 | Apple Inc. | Image sensor with flexible pixel summing |
US9596423B1 (en) | 2013-11-21 | 2017-03-14 | Apple Inc. | Charge summing in an image sensor |
US9596420B2 (en) | 2013-12-05 | 2017-03-14 | Apple Inc. | Image sensor having pixels with different integration periods |
US9473706B2 (en) | 2013-12-09 | 2016-10-18 | Apple Inc. | Image sensor flicker detection |
US9654710B2 (en) * | 2013-12-10 | 2017-05-16 | Gvbb Holdings S.A.R.L. | Photodiode limiter |
US10285626B1 (en) | 2014-02-14 | 2019-05-14 | Apple Inc. | Activity identification using an optical heart rate monitor |
US9277144B2 (en) | 2014-03-12 | 2016-03-01 | Apple Inc. | System and method for estimating an ambient light condition using an image sensor and field-of-view compensation |
US9232150B2 (en) | 2014-03-12 | 2016-01-05 | Apple Inc. | System and method for estimating an ambient light condition using an image sensor |
US9584743B1 (en) | 2014-03-13 | 2017-02-28 | Apple Inc. | Image sensor with auto-focus and pixel cross-talk compensation |
US9497397B1 (en) | 2014-04-08 | 2016-11-15 | Apple Inc. | Image sensor with auto-focus and color ratio cross-talk comparison |
US9538106B2 (en) | 2014-04-25 | 2017-01-03 | Apple Inc. | Image sensor having a uniform digital power signature |
US9686485B2 (en) | 2014-05-30 | 2017-06-20 | Apple Inc. | Pixel binning in an image sensor |
US10097780B2 (en) | 2014-06-05 | 2018-10-09 | Invisage Technologies, Inc. | Sensors and systems for the capture of scenes and events in space and time |
JP6525694B2 (en) * | 2015-04-08 | 2019-06-05 | キヤノン株式会社 | Imaging device, imaging system, and driving method of imaging device |
KR102465212B1 (en) | 2015-10-30 | 2022-11-10 | 삼성전자주식회사 | Photographing apparatus using multiple exposure sensor and photographing method thereof |
US10044948B2 (en) * | 2015-11-12 | 2018-08-07 | Omnivision Technologies, Inc. | Image sensor global shutter supply circuit with variable bandwidth |
US9838623B2 (en) * | 2015-11-12 | 2017-12-05 | Omnivision Technologies, Inc. | Global shutter control signal generator with reduced driving requirements |
US9912883B1 (en) | 2016-05-10 | 2018-03-06 | Apple Inc. | Image sensor with calibrated column analog-to-digital converters |
US10658419B2 (en) | 2016-09-23 | 2020-05-19 | Apple Inc. | Stacked backside illuminated SPAD array |
WO2018075997A1 (en) * | 2016-10-21 | 2018-04-26 | Invisage Technologies, Inc. | Motion tracking using multiple exposures |
US11194221B2 (en) * | 2017-01-24 | 2021-12-07 | Lg Innotek Co., Ltd. | Liquid lens, liquid lens module including the lens, camera module including the same, and method for controlling the lens |
CN110235024B (en) | 2017-01-25 | 2022-10-28 | 苹果公司 | SPAD detector with modulation sensitivity |
US10656251B1 (en) | 2017-01-25 | 2020-05-19 | Apple Inc. | Signal acquisition in a SPAD detector |
US10962628B1 (en) | 2017-01-26 | 2021-03-30 | Apple Inc. | Spatial temporal weighting in a SPAD detector |
US10469775B2 (en) * | 2017-03-31 | 2019-11-05 | Semiconductor Components Industries, Llc | High dynamic range storage gate pixel circuitry |
US10622538B2 (en) | 2017-07-18 | 2020-04-14 | Apple Inc. | Techniques for providing a haptic output and sensing a haptic input using a piezoelectric body |
US10440301B2 (en) | 2017-09-08 | 2019-10-08 | Apple Inc. | Image capture device, pixel, and method providing improved phase detection auto-focus performance |
CN108280425B (en) * | 2018-01-23 | 2021-10-29 | 北京思比科微电子技术股份有限公司 | Rapid photometry implementation method based on in-screen optical fingerprint sensor |
US10848693B2 (en) | 2018-07-18 | 2020-11-24 | Apple Inc. | Image flare detection using asymmetric pixels |
US11019294B2 (en) | 2018-07-18 | 2021-05-25 | Apple Inc. | Seamless readout mode transitions in image sensors |
US11233966B1 (en) | 2018-11-29 | 2022-01-25 | Apple Inc. | Breakdown voltage monitoring for avalanche diodes |
CN109639993B (en) * | 2018-12-28 | 2020-10-23 | 北京思比科微电子技术股份有限公司 | Multi-window exposure control method |
US11468146B2 (en) | 2019-12-06 | 2022-10-11 | Globalfoundries U.S. Inc. | Array of integrated pixel and memory cells for deep in-sensor, in-memory computing |
US11195580B2 (en) * | 2020-02-26 | 2021-12-07 | Globalfoundries U.S. Inc. | Integrated pixel and two-terminal non-volatile memory cell and an array of cells for deep in-sensor, in-memory computing |
US11563910B2 (en) | 2020-08-04 | 2023-01-24 | Apple Inc. | Image capture devices having phase detection auto-focus pixels |
US11968639B2 (en) | 2020-11-11 | 2024-04-23 | Magna Electronics Inc. | Vehicular control system with synchronized communication between control units |
US11546532B1 (en) | 2021-03-16 | 2023-01-03 | Apple Inc. | Dynamic correlated double sampling for noise rejection in image sensors |
US12069384B2 (en) | 2021-09-23 | 2024-08-20 | Apple Inc. | Image capture devices having phase detection auto-focus pixels |
Citations (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US4924316A (en) * | 1986-04-07 | 1990-05-08 | Fuji Photo Film Co., Ltd. | Solid color pickup apparatus |
US4977312A (en) * | 1988-10-18 | 1990-12-11 | Nikon Corporation | Photometric apparatus employing solid-state imaging device |
US6252217B1 (en) * | 1997-12-18 | 2001-06-26 | Simage Oy | Device for imaging radiation |
US6552319B2 (en) * | 1997-12-18 | 2003-04-22 | Simage Oy | Device for imaging radiation |
US7238977B2 (en) * | 2004-08-19 | 2007-07-03 | Micron Technology, Inc. | Wide dynamic range sensor having a pinned diode with multiple pinned voltages |
Family Cites Families (11)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US6859227B1 (en) | 1999-04-23 | 2005-02-22 | Micron Technology, Inc. | Active pixel sensor with reduced fixed pattern noise |
US7362365B1 (en) * | 2002-06-26 | 2008-04-22 | Pixim, Inc. | Digital image capture having an ultra-high dynamic range |
US7115923B2 (en) * | 2003-08-22 | 2006-10-03 | Micron Technology, Inc. | Imaging with gate controlled charge storage |
US7196304B2 (en) * | 2004-01-29 | 2007-03-27 | Micron Technology, Inc. | Row driver for selectively supplying operating power to imager pixel |
US7332703B2 (en) * | 2004-03-22 | 2008-02-19 | Micron Technology, Inc. | Imaging structure including a pixel with multiple signal readout circuits and methods of operation for imaging structure |
US7259413B2 (en) * | 2004-09-28 | 2007-08-21 | Micron Technology, Inc. | High dynamic range image sensor |
US7791663B2 (en) * | 2004-10-15 | 2010-09-07 | Omnivision Technologies, Inc. | Image sensor and pixel that has positive transfer gate voltage during integration period |
US7345330B2 (en) * | 2004-12-09 | 2008-03-18 | Omnivision Technologies, Inc. | Local interconnect structure and method for a CMOS image sensor |
US7344910B2 (en) * | 2005-09-27 | 2008-03-18 | Omnivision Technologies, Inc. | Self-aligned photodiode for CMOS image sensor and method of making |
US7427736B2 (en) * | 2006-03-23 | 2008-09-23 | Micron Technology, Inc. | Method and apparatus for providing a rolling double reset timing for global storage in image sensors |
US7514716B2 (en) * | 2006-08-29 | 2009-04-07 | Aptina Imaging Corporation | In-pixel analog memory with non-destructive read sense circuit for high dynamic range global shutter pixel operation |
-
2009
- 2009-03-12 US US12/402,933 patent/US8184188B2/en active Active
-
2010
- 2010-03-08 TW TW099106674A patent/TWI424742B/en active
Patent Citations (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US4924316A (en) * | 1986-04-07 | 1990-05-08 | Fuji Photo Film Co., Ltd. | Solid color pickup apparatus |
US4977312A (en) * | 1988-10-18 | 1990-12-11 | Nikon Corporation | Photometric apparatus employing solid-state imaging device |
US6252217B1 (en) * | 1997-12-18 | 2001-06-26 | Simage Oy | Device for imaging radiation |
US6552319B2 (en) * | 1997-12-18 | 2003-04-22 | Simage Oy | Device for imaging radiation |
US7238977B2 (en) * | 2004-08-19 | 2007-07-03 | Micron Technology, Inc. | Wide dynamic range sensor having a pinned diode with multiple pinned voltages |
Also Published As
Publication number | Publication date |
---|---|
TW201106690A (en) | 2011-02-16 |
US8184188B2 (en) | 2012-05-22 |
US20100231771A1 (en) | 2010-09-16 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
TWI424742B (en) | Methods and apparatus for high dynamic operation of a pixel cell | |
US9900528B2 (en) | Method, apparatus and system providing a storage gate pixel with high dynamic range | |
US9749557B2 (en) | Solid-state image pickup device in which charges overflowing a memory during a charge transfer period are directed to a floating diffusion and method of driving same | |
US9185273B2 (en) | Imaging pixels with improved dynamic range | |
US8908065B2 (en) | Solid state imaging processing systems and method for providing signal correction of pixel saturation errors | |
US8130302B2 (en) | Methods and apparatus providing selective binning of pixel circuits | |
JP5614993B2 (en) | Imaging apparatus and solid-state imaging device driving method | |
US7969494B2 (en) | Imager and system utilizing pixel with internal reset control and method of operating same | |
WO2019036237A1 (en) | Detection circuit for photo sensor with stacked substrates | |
US9363450B2 (en) | Imaging systems and methods for image signal gain adjustment | |
US20120044396A1 (en) | Dual pinned diode pixel with shutter | |
US20100039543A1 (en) | Solid-state image sensor and driving method thereof, and image sensor | |
JP2008042679A (en) | Photoelectric conversion device and imaging apparatus | |
US9794497B2 (en) | Solid-state imaging device controlling read-out of signals from pixels in first and second areas | |
KR102690091B1 (en) | Solid-state image pickup device and driving method therefor, and electronic apparatus | |
US20090321799A1 (en) | Method and apparatus for increasing conversion gain in imagers | |
JP6734649B2 (en) | IMAGING DEVICE, IMAGING SYSTEM, AND METHOD OF CONTROLLING IMAGING DEVICE | |
US10051216B2 (en) | Imaging apparatus and imaging method thereof using correlated double sampling | |
US7889256B2 (en) | Method and apparatus for reducing temporal row-wise noise in imagers | |
US8908071B2 (en) | Pixel to pixel charge copier circuit apparatus, systems, and methods | |
JP2009188650A (en) | Imaging apparatus | |
JP2007324873A (en) | Solid-state imaging apparatus, and its driving method | |
JP2015211329A (en) | Imaging apparatus and driving method of imaging apparatus | |
JP2008042677A (en) | Photoelectric conversion apparatus and imaging apparatus | |
JP2012068253A (en) | Photoelectric conversion device, and imaging device |