JP7098462B2 - Image pickup device and control method of image pickup device - Google Patents

Description

The present invention relates to an image pickup apparatus and a control method for the image pickup apparatus.

In a CMOS image pickup device, there is an AD multisampling method that suppresses random noise contained in a signal by performing analog-to-digital (AD) conversion on the same signal multiple times and then averaging the same signal when reading the signal of the pixel. .. Since this AD multisampling method performs AD conversion a plurality of times, there is a problem that the reading speed is significantly reduced. However, recently, a method for suppressing a decrease in reading speed has appeared.

Patent Document 1 discloses a method in which an n-bit AD conversion process is repeated W times (W is a positive integer of 2 or more) in the reference signal comparison type AD conversion process. According to Patent Document 1, as the number of times W increases, the bit accuracy n is reduced to shorten the AD conversion time per one time and suppress the decrease in the reading speed.

Japanese Unexamined Patent Publication No. 2009-296423

However, when the bit accuracy n is extremely reduced, a false signal is generated due to the quantization error. Further, since the error is W times integrated, there is a problem that the image quality is deteriorated.

An object of the present invention is to provide an image pickup apparatus and a control method for an image pickup apparatus capable of suppressing deterioration of image quality due to quantization error and suppressing random noise at high speed.

The image pickup apparatus of the present invention is based on the photoelectric conversion by comparing a plurality of pixels, each of which outputs a signal based on the photoelectric conversion, a signal based on the photoelectric conversion, and a reference signal that changes with time. An analog-digital conversion unit that converts a signal from analog to digital, and a gradient of the reference signal and a signal based on the photoelectric conversion are converted from analog to digital according to the amount of random noise contained in the signal based on the photoelectric conversion. It has a control unit that controls the number of times.

According to the present invention, it is possible to suppress deterioration of image quality due to quantization error and to generate a digital signal in which random noise is suppressed at high speed.

It is a figure which shows the structural example of a pixel. It is a figure which shows the structural example of the image pickup apparatus. It is a timing chart which shows the 1st read operation. It is a timing chart which shows the 2nd read operation. It is a figure for demonstrating the signal input to a comparator. It is a figure for demonstrating the operation of a noise prediction part. It is a figure which shows the configuration example of an image pickup system. It is a figure which shows the structural example of the image pickup apparatus. It is a flowchart for demonstrating the reading operation of 1 frame.

Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings.
(First Embodiment)
Hereinafter, the first embodiment of the present invention will be described with reference to FIGS. 1 to 7.
FIG. 1 is a circuit diagram showing a configuration example of a pixel 10 according to the first embodiment of the present invention. The pixel 10 includes a photodiode 11, a transfer switch 12, a floating diffusion (hereinafter referred to as FD) 13, an amplification MOS transistor 14, a row selection switch 15, and a reset switch 16.

The photodiode 11 is a photoelectric conversion unit, and converts light incident through an optical system into electric charges. The transfer switch 12 transfers the charge converted by the photodiode 11 to the FD 13 according to the transfer pulse PTX input to the gate terminal. The FD 13 accumulates an electric charge and converts the accumulated electric charge into a voltage. The amplification MOS transistor 14 functions as a source follower together with the constant current circuit 22 of FIG. The amplification MOS transistor 14 amplifies the voltage of the FD 13 connected to the gate, and outputs the amplified voltage. The row selection switch 15 is driven by the row selection pulse MOSFET input to its gate, its drain is connected to the source of the amplification MOS transistor 14, and its source is connected to the output line 21.

The row selection switch 15 in which the row selection pulse MOSFET has reached the active level (high level) is in a conductive state, and the source of the corresponding amplification MOS transistor 14 is connected to the output line 21. The output line 21 is shared by a plurality of pixels 10 in the same row and is connected to the constant current circuit 22 and the signal amplification circuit 23 in FIG. The reset switch 16 has its drain connected to the power supply line VDD and is driven by the reset pulse PRESS input to the gate to reset the charge stored in the FD 13.

First, the reset switch 16 resets the FD 13 by the reset pulse PRESS, and then releases the reset of the FD 13. In that case, the amplification MOS transistor 14 outputs an N signal based on the reset release of the FD 13 to the output line 21.

Next, the transfer switch 12 transfers the charge converted by the photodiode 11 to the FD 13 by the transfer pulse PTX. In that case, the amplification MOS transistor 14 outputs an S signal based on the photoelectric conversion of the photodiode 11 to the output line 21.

FIG. 2 is a diagram showing a configuration example of the image pickup apparatus 1 according to the present embodiment. The image pickup device 1 is a CMSO image pickup device, and has a plurality of pixels 10 arranged in a two-dimensional matrix. A plurality of output lines 21 are provided for each pixel 10 in each row. Each of the pixels 10 in each row is connected to the output line 21 in each row. A constant current circuit 22 is connected to each of the plurality of output lines 21. The constant current circuit 22 functions as a source follower together with the amplification MOS transistor 14 of FIG. The amplification MOS transistor 14 outputs a voltage corresponding to the voltage of the FD 13 to the output line 21. The plurality of pixels 10 output a signal to the output line 21 in units of rows.

Each of the signal amplification circuits 23 in each column is an amplification unit, and the gain set value Gain can be changed, and the signal of the output line 21 in each column is amplified by the gain set value Gain. It is desirable to provide the signal amplification circuit 23 in order to reduce noise, but it is not always necessary.

The reference signal generation unit 31 outputs a reference signal Vram (FIG. 3) that changes with time. The reference signal generation unit 31 can change the slope of the output reference signal Vramp. Each of the comparators 24 in each row is a comparison unit, compares the signal output from the signal amplification circuit 23 in each row with the reference signal Vram, and outputs the comparison result signal.

The noise prediction unit 32 predicts the random noise amount of the N signal or the S signal input from the signal amplification circuit 23 to the comparator 24, and the reference signal generated by the reference signal generation unit 31 according to the predicted random noise amount. Controls Vramp. The information used for predicting the amount of random noise is a set value or condition of the image pickup device 1, for example, a gain set value of the signal amplification circuit 23, temperature information of the image pickup device 1 by the temperature sensor 1012 (FIG. 7), or an outpatient. It is the drive information of the noise source.
Further, in the case of a configuration in which the capacitance value of the FD 13 can be switched, the setting value information of the capacitance also corresponds to the information used for predicting the random noise amount. Further, the noise prediction unit 32 may actually measure the random noise amount and determine the slope of the reference signal Vram of the reference signal generation unit 31, and the configuration and method thereof will be described in the second embodiment.

The counter circuit 25 is a counter unit, and a reference clock signal CLK is input, and up-counting or down-counting is performed based on the CLK. Further, the counter circuit 25 in each column starts counting the count value when the level change of the reference signal Vram is started, and counts the count value when the comparison result signal of the comparator 24 in each column is inverted. To stop. AD conversion is performed by these operations.
The count value of the counter circuit 25 represents a digital value obtained by converting the signal output by the signal amplification circuit 23 from analog to digital. The comparator 24 and the counter circuit 25 are analog-to-digital conversion units that convert the signal output by the signal amplification circuit 23 from analog to digital.

First, the pixel 10 outputs an N signal based on reset release via the signal amplification circuit 23. The comparator 24 compares the N signal output by the signal amplification circuit 23 with the reference signal Vram. The counter circuit 25 counts the digital value of the N signal. The CDS circuit 26 holds the digital value of the N signal.

Next, the pixel 10 outputs an S signal based on photoelectric conversion via the signal amplification circuit 23. The comparator 24 compares the S signal output by the signal amplification circuit 23 with the reference signal Vram. The counter circuit 25 counts the digital value of the S signal. The CDS circuit 26 holds the digital value of the S signal. The CDS circuit 26 in each column subtracts the digital value of the N signal from the digital value of the S signal, and outputs the pixel signal to the horizontal transfer memory 27.

The output line 21, constant current circuit 22, signal amplifier circuit 23, comparator 24, counter circuit 25, and CDS circuit 26 are provided in each row. The horizontal transfer memory 27 holds the pixel signals of the CDS circuits 26 in each row and sequentially outputs them to the outside of the image pickup apparatus 1.

FIG. 3 is a timing chart showing the first read operation. Here, the "nth row selection pulse PSEL" is referred to as a "row selection pulse PSEL (n)" with a subscript n. This also applies to the transfer pulse PTX and the reset pulse PRES.

At time t1, the row selection pulse PSEL (n) becomes high level, the row selection switch 15 on the nth row is turned on, and each of the pixels 10 on the nth row is connected to the corresponding output line 21.

Further, at the same time t1, the reset pulse PRES (n) becomes a high level, and in the nth row, the reset switch 16 resets the voltage of the FD 13. After that, the reset pulse PRESS (n) becomes low level, and in the nth line, the reset switch 16 releases the reset of the FD 13. At this time, the pixel 10 on the nth row outputs an N signal based on the reset release to the output line 21. The N signal is reflected on the output line 21 over a static time, and is input to the comparator 24 via the signal amplification circuit 23.

At time t2, the reference signal generation unit 31 starts the level change of the reference signal Vramp1. The reference signal Vram1 corresponds to the reference signal Vram in FIG. The comparator 24 compares the N signal output by the signal amplification circuit 23 with the reference signal Vram1, and if the reference signal Vram1 is larger than the N signal, outputs a high-level comparison result signal Comp.

Further, at the same time t2, the generation of the reference clock signal CLK is started. The counter circuit 25 starts counting the count value in synchronization with the reference clock signal CLK. As a result, AD conversion of the N signal is started.

Then, at time t3, the comparator 24 inverts the comparison result signal Comp from high level to low level when the reference signal Vram1 becomes smaller than the N signal. The counter circuit 25 stops the counting operation of the count value when the comparison result signal Comp of the comparator 24 is inverted. This completes the AD conversion of the N signal. The count value of the counter circuit 25 represents the digital value of the N signal.

At time t4, when the reference signal Vramp1 reaches a predetermined potential, the reference signal generation unit 31 resets the reference signal Vramp1 to the initial value, and the generation of the reference clock signal CLK is stopped.

At time t5, the transfer pulse PTX (n) becomes high level, and at the nth line, the transfer switch 12 transfers the charge converted by the photodiode 11 to the FD 13. After that, the transfer pulse PTX (n) becomes low level, and at the nth line, the transfer switch 12 ends the charge transfer from the photodiode 11 to the FD 13. The pixel 10 on the nth line outputs an S signal based on the photoelectric conversion of the photodiode 11 to the output line 21. The S signal is reflected on the output line 21 over a statically determinate time.

Further, at the same time t5, the signal RST becomes high level, and the counter circuit 25 in each column outputs the digital value of the N signal to the CDS circuit 26 in each column, and then resets the count value. At this time, the CDS circuit 26 holds the digital value of the N signal.

At time t6, the reference signal generation unit 31 starts the level change of the reference signal Vramp1. The comparator 24 compares the S signal output by the signal amplification circuit 23 with the reference signal Vram1, and if the reference signal Vram1 is larger than the S signal, outputs a high-level comparison result signal Comp.

Further, at the same time t6, the generation of the reference clock signal CLK is started. The counter circuit 25 starts counting the count value in synchronization with the reference clock signal CLK. As a result, AD conversion of the S signal is started.

After that, at time t7, when the reference signal Vram1 becomes smaller than the S signal, the comparator 24 inverts the comparison result signal Comp from the high level to the low level. The counter circuit 25 stops the counting operation of the count value when the comparison result signal Comp of the comparator 24 is inverted. This completes the AD conversion of the S signal. The count value of the counter circuit 25 represents the digital value of the S signal.

At time t8, when the reference signal Vramp1 reaches a predetermined potential, the reference signal generation unit 31 resets the reference signal Vramp1 to the initial value, and the generation of the reference clock signal CLK is stopped.

At time t9, the row selection pulse PSEL (n) becomes low level, the row selection switch 15 on the nth row is turned off, and each of the pixels 10 on the nth row is cut off with respect to the corresponding output line 21. ..

Further, at the same time t9, the signal RST becomes high level, and the counter circuit 25 in each column outputs the digital value of the S signal to the CDS circuit 26 in each column, and then resets the count value. At this time, the CDS circuit 26 subtracts the digital value of the N signal held at time t5 from the digital value of the S signal, and outputs the subtraction result as a pixel signal to the horizontal transfer memory 27. The horizontal transfer memory 27 holds the pixel signals of the CDS circuits 26 in each row and sequentially outputs them to the outside of the image pickup apparatus 1. By these operations, the first read operation is performed.

FIG. 4 is a timing chart showing the second read operation. At time t11, the row selection pulse PSEL (n) becomes high level, the row selection switch 15 on the nth row is turned on, and each of the pixels 10 on the nth row is connected to the corresponding output line 21.

Further, at the same time t11, the reset pulse PRES (n) becomes a high level, and in the nth row, the reset switch 16 resets the voltage of the FD 13. After that, the reset pulse PRESS (n) becomes low level, and in the nth line, the reset switch 16 releases the reset of the FD 13. At this time, the pixel 10 on the nth row outputs an N signal based on the reset release to the output line 21. The N signal is reflected on the output line 21 over a static time, and is input to the comparator 24 via the signal amplification circuit 23.

At time t12, the reference signal generation unit 31 starts the level change of the reference signal VrampN. The reference signal VrampN corresponds to the reference signal Vramp in FIG. The slope of the reference signal VrampN is N times the slope of the reference signal Vramp1 in FIG. In the following description, the case of N = 2 will be described as an example. The comparator 24 compares the N signal output by the signal amplification circuit 23 with the reference signal VrampN, and if the reference signal VrampN is larger than the N signal, outputs a high-level comparison result signal Comp.

Further, at the same time t12, the generation of the reference clock signal CLK is started. The counter circuit 25 starts counting the count value in synchronization with the reference clock signal CLK. As a result, AD conversion of the N signal is started.

After that, at time t13, when the reference signal VrampN becomes smaller than the N signal, the comparator 24 inverts the comparison result signal Comp from the high level to the low level. When the comparison result signal Comp of the comparator 24 is inverted, the counter circuit 25 temporarily stops the counting operation of the count value. The count value of the counter circuit 25 represents the digital value of the N signal. When the magnitudes of the N signals in FIGS. 3 and 4 are the same, the slope of the reference signal VrampN is N times the slope of the reference signal Vramp1, so that the count value of the counter circuit 25 in FIG. 4 is the counter circuit 25 in FIG. It becomes 1 / N (= 1/2) of the count value of. By using the reference signal VrampN whose slope is N times, the AD conversion time can be shortened to 1 / N.

At time t14, when the reference signal VrampN reaches a predetermined potential, the reference signal generation unit 31 resets the reference signal VrampN to the initial value, and the generation of the reference clock signal CLK is stopped. At this point, the signal RST does not reach the high level but maintains the low level. The counter circuit 25 in each column maintains the count value without resetting it.

At time t15, similarly to time t12, the reference signal generation unit 31 starts the level change of the reference signal VrampN. The comparator 24 compares the N signal output by the signal amplification circuit 23 with the reference signal VrampN, and if the reference signal VrampN is larger than the N signal, outputs a high-level comparison result signal Comp.

Further, at the same time t15, the generation of the reference clock signal CLK is restarted. The counter circuit 25 restarts counting of the count value in synchronization with the reference clock signal CLK. As a result, the second AD conversion of the N signal is started.

Then, at time t16, the comparator 24 inverts the comparison result signal Comp from high level to low level when the reference signal VrampN becomes smaller than the N signal. The counter circuit 25 stops the counting operation of the count value when the comparison result signal Comp of the comparator 24 is inverted. The count value of the counter circuit 25 represents the digital value of the N signal.

At time t17, when the reference signal VrampN reaches a predetermined potential, the reference signal generation unit 31 resets the reference signal VrampN to the initial value, and the generation of the reference clock signal CLK is stopped.

From time t12 to t17, AD conversion of the N signal is performed twice, and the counter circuit 25 accumulates and counts the count values corresponding to the two AD conversions. The count value obtained by one AD conversion is 1/2 of the count value when the reference signal Vramp1 is used. The counter circuit 25 counts the counts twice in succession and accumulates the count values, whereby a count value equivalent to the count value when the reference signal Vramp1 is used can be obtained. When N is 3 or more, the operation at times t15 to t17 is repeated so that the AD conversion is performed N times.

At time t18, the transfer pulse PTX (n) becomes high level, and at the nth line, the transfer switch 12 transfers the charge converted by the photodiode 11 to the FD 13. After that, the transfer pulse PTX (n) becomes low level, and at the nth line, the transfer switch 12 ends the charge transfer from the photodiode 11 to the FD 13. The pixel 10 on the nth line outputs an S signal based on the photoelectric conversion of the photodiode 11 to the output line 21. The S signal is reflected on the output line 21 over a statically determinate time.

Further, at the same time t18, the signal RST becomes high level, and the counter circuit 25 in each column outputs the digital value of the N signal to the CDS circuit 26 in each column, and then resets the count value. At this time, the CDS circuit 26 holds the digital value of the N signal.

At time t19, the reference signal generation unit 31 starts the level change of the reference signal VrampN. The comparator 24 compares the S signal output by the signal amplification circuit 23 with the reference signal VrampN, and if the reference signal VrampN is larger than the S signal, outputs a high-level comparison result signal Comp.

Further, at the same time t19, the generation of the reference clock signal CLK is started. The counter circuit 25 starts counting the count value in synchronization with the reference clock signal CLK. As a result, AD conversion of the S signal is started.

After that, at time t20, when the reference signal VrampN becomes smaller than the S signal, the comparator 24 inverts the comparison result signal Comp from the high level to the low level. When the comparison result signal Comp of the comparator 24 is inverted, the counter circuit 25 temporarily stops the counting operation of the count value. The count value of the counter circuit 25 represents the digital value of the S signal. When the magnitudes of the S signals in FIGS. 3 and 4 are the same, the slope of the reference signal VrampN is N times the slope of the reference signal Vramp1, so that the count value of the counter circuit 25 in FIG. 4 is the counter circuit 25 in FIG. It becomes 1 / N (= 1/2) of the count value of.

At time t21, when the reference signal VrampN reaches a predetermined potential, the reference signal generation unit 31 resets the reference signal VrampN to the initial value, and the generation of the reference clock signal CLK is stopped. At this point, the signal RST does not reach the high level but maintains the low level. The counter circuit 25 in each column maintains the count value without resetting it.

At time t22, similarly to time t19, the reference signal generation unit 31 starts the level change of the reference signal VrampN. The comparator 24 compares the S signal output by the signal amplification circuit 23 with the reference signal VrampN, and if the reference signal VrampN is larger than the S signal, outputs a high-level comparison result signal Comp.

Further, at the same time t22, the generation of the reference clock signal CLK is restarted. The counter circuit 25 restarts counting of the count value in synchronization with the reference clock signal CLK. As a result, the second AD conversion of the S signal is started.

After that, at time t23, when the reference signal VrampN becomes smaller than the S signal, the comparator 24 inverts the comparison result signal Comp from the high level to the low level. The counter circuit 25 stops the counting operation of the count value when the comparison result signal Comp of the comparator 24 is inverted. The count value of the counter circuit 25 represents the digital value of the S signal.

At time t24, when the reference signal VrampN reaches a predetermined potential, the reference signal generation unit 31 resets the reference signal VrampN to the initial value, and the generation of the reference clock signal CLK is stopped.

From time t19 to t24, AD conversion of the S signal is performed twice, and the counter circuit 25 accumulates and counts the count values corresponding to the two AD conversions. The count value obtained by one AD conversion is 1/2 of the count value when the reference signal Vramp1 is used. The counter circuit 25 counts the counts twice in succession and accumulates the count values, whereby a count value equivalent to the count value when the reference signal Vramp1 is used can be obtained. When N is 3 or more, the operation at times t22 to t24 is repeated so that the AD conversion is performed N times.

At time t25, the row selection pulse PSEL (n) becomes low level, the row selection switch 15 on the nth row is turned off, and each of the pixels 10 on the nth row is cut off with respect to the corresponding output line 21. ..

Further, at the same time t25, the signal RST becomes high level, and the counter circuit 25 in each column outputs the digital value of the S signal to the CDS circuit 26 in each column, and then resets the count value. At this time, the CDS circuit 26 subtracts the digital value of the N signal held at time t18 from the digital value of the S signal, and outputs the subtraction result as a pixel signal to the horizontal transfer memory 27. The horizontal transfer memory 27 holds the pixel signals of the CDS circuits 26 in each row and sequentially outputs them to the outside of the image pickup apparatus 1. By these operations, the second read operation is performed.

The second read operation has a high effect of reducing random noise with respect to the first read operation by performing the AD conversion of the N signal and the AD conversion of the S signal N times each, but on the other hand, it occurs. The quantization error also increases. If the amount of random noise of the N signal or S signal input to the comparator 24 is large, this quantization error will be random in the direction in which the error occurs, and is expected in the process of executing AD conversion multiple times and accumulating it. Converges to the value.

On the other hand, if the random noise amount of the N signal or the S signal is small and the directions in which the quantization error occurs are aligned on one side, the error is accumulated in the process of performing the AD conversion a plurality of times and appears as a false signal.

Therefore, in order to obtain the optimum image quality, the random noise is reduced by switching between the first read operation and the second read operation or determining N of the second read operation according to the amount of random noise. , It is necessary to suppress false signals due to quantization error. The noise prediction unit 32 predicts the random noise amount of the N signal or the S signal input to the comparator 24, and switches between the first read operation and the second read operation according to the predicted random noise amount, or The N of the second read operation is determined. That is, the noise prediction unit 32 is a control unit, and controls the slope of the reference signal Vlamp corresponding to the N value and the number of AD conversions according to the predicted random noise amount.

FIG. 5 is a diagram for explaining a signal input to the comparator 24. The comparator 24 compares the N signal or the S signal with the reference signal VrampN. Here, assuming that the amount of potential change of the reference clock signal CLK of the reference signal Vramp1 per cycle is ΔVclk, the amount of potential change of the reference clock signal CLK of the reference signal VrampN per cycle is N × ΔVclk. Further, the standard deviation of the random noise amount of the N signal or the S signal input to the comparator 24 is set to Vrms, and the coefficient used for the prediction is set to Kth. At this time, the noise prediction unit 32 determines the maximum value Nmax of the natural numbers N satisfying the equation (1).
N × ΔVclk ≦ Kth × Vrms ・ ・ ・ (1)

When Nmax is 1, the image pickup apparatus 1 performs a first read operation, and when Nmax is 2 or more, it performs a second read operation of N = Nmax.

Further, Kth takes various values depending on the probability density function of the random noise of the N signal or the S signal input to the comparator 24, but if it is Gaussian noise of the effective value as a guide, if Kth is √2, it is assumed. False signals due to quantization error are extremely negligible values.

It should be noted that this Kth determination method is determined by considering not only the probability density function of random noise but also the balance between prioritizing the effect of reducing random noise and prioritizing the suppression of false signals due to quantization error. It is suitable and is not limited to the above method.

FIG. 6 is a diagram for explaining the operation of the noise prediction unit 32. The noise prediction unit 32 determines the maximum value Nmax based on the random noise prediction table storing the values of the standard deviation Vrms of the random noise amount under various conditions. The reference signal generation unit 31 controls the reference signal VrampN according to the maximum value Nmax determined by the noise prediction unit 32.

The noise prediction unit 32 has a random noise prediction table that inputs the gain set value Gain of the signal amplification circuit 23 and the temperature information Temp of the image pickup device 1 and outputs the standard deviation Vrms of the random noise amount. The random noise prediction table shall be written at the time of shipment, and the value may be a value predicted from the design value or a value based on actual measurement.

First, the noise prediction unit 32 acquires the gain setting value Gain of the signal amplification circuit 23 from the shooting mode timing generation unit 1006 (FIG. 7), and acquires the temperature information Temp of the image pickup device 1 from the temperature sensor 1012 (FIG. 7). do. Next, the noise prediction unit 32 refers to the random noise prediction table, and determines the standard deviation Vrms of the random noise amount based on the acquired gain setting value Gain and the temperature information Temp. Next, the noise prediction unit 32 calculates the maximum value Nmax of the natural numbers N satisfying the equation (1) based on the standard deviation Vrms of the random noise amount. Next, the noise prediction unit 32 controls the slope of the reference signal VrampN and the AD conversion number N (= Nmax) with respect to the reference signal generation unit 31 based on the calculated maximum value Nmax.

The noise prediction unit 32 predicts the standard deviation Vrms of the random noise amount, and the larger the standard deviation Vrms of the predicted random noise amount, the larger the absolute value of the slope of the reference signal VrampN, and the number of AD conversions N (= Nmax). To increase. As a result, the image pickup apparatus 1 can obtain good image quality in which the amount of random noise is suppressed and the false signal due to the quantization error is suppressed according to various amounts of random noise.

FIG. 7 is a diagram showing a configuration example of an image pickup system 1000 having an image pickup apparatus 1 according to the present embodiment. The lens unit 1001 forms an optical image of the subject on the image pickup apparatus 1. Further, the lens unit 1001 performs zoom control, focus control, aperture control, and the like under the control of the lens driving device 1002. The mechanical shutter 1003 controls the exposure / shading of the image pickup device 1 by the control of the shutter drive device 1004. As described above, the image pickup apparatus 1 generates an image signal by photoelectric conversion.

The image pickup signal processing circuit 1005 performs various corrections, data compression, composition processing of a plurality of images for obtaining a wide dynamic range image, and the like on the image signal generated by the image pickup device 1. The shooting mode timing generation unit 1006 outputs a shooting mode instruction signal and various timing signals to the image pickup device 1 and the image pickup signal processing circuit 1005.

The shooting mode timing generation unit 1006 outputs the gain setting value Gain of the signal amplification circuit 23 to the image pickup apparatus 1. The noise prediction unit 32 in the image pickup apparatus 1 acquires the gain set value Gain of the signal amplification circuit 23 from the shooting mode timing generation unit 1006. The temperature sensor 1012 measures the temperature Temp of the image pickup device 1 and outputs the measured temperature information Temp to the image pickup device 1. The noise prediction unit 32 in the image pickup device 1 acquires the temperature Temp of the image pickup device 1 from the temperature sensor 1012.

The memory unit 1007 is a memory for temporarily storing image data. The overall control calculation unit 1008 is a circuit that performs various calculations and overall control of the image pickup system 1000. The recording medium control I / F unit 1009 is an interface for recording or reading from the recording medium 1010. The recording medium 1010 is a detachable semiconductor memory for recording or reading image data. The display unit 1011 is a device that displays various information and captured images.

Next, the operation of the image pickup system 1000 will be described. When the main power of the image pickup system 1000 is turned on, the power of the control system is turned on, and the power of the image pickup system circuit such as the image pickup signal processing circuit 1005 is turned on. Next, when the release button is pressed, the image pickup system 1000 starts a shooting operation.

The shooting mode / timing generation unit 1006 outputs setting information to the image pickup apparatus 1 and gives a shooting instruction. At this time, the noise prediction unit 32 determines the inclination of the reference signal VrampN and AD based on the gain setting value Gain of the signal amplification circuit 23 obtained from the shooting mode timing generation unit 1006 and the temperature information Temp obtained from the temperature sensor 1012. The number of conversions N (= Nmax) is determined. The image pickup apparatus 1 uses the reference signal Vram to generate a digital image signal.

When the photographing operation is completed, the photographing signal processing circuit 1005 performs image processing on the image signal generated by the image pickup apparatus 1. The overall control calculation unit 1008 writes the image processed image data to the memory unit 1007. Then, the overall control calculation unit 1008 records the data written in the memory unit 1007 on the removable recording medium 1010 such as a semiconductor memory via the recording medium control I / F unit 1009. The image pickup system 1000 may directly output image data to a computer or the like via an external I / F unit (not shown) to process the image.

As described above, the image pickup apparatus 1 is capable of high-speed signal reading while suppressing deterioration of image quality due to quantization error and suppressing random noise. The image pickup device 1 can be applied to a smartphone, a tablet, an industrial camera, a medical camera, an in-vehicle camera, and the like, in addition to a digital camera and a video camera.

(Second embodiment)
Next, a second embodiment of the present invention will be described with reference to FIGS. 8 and 9. FIG. 8 is a diagram showing a configuration example of the image pickup apparatus 1 according to the second embodiment of the present invention. The image pickup apparatus 1 includes a column readout circuit 20, a reference signal generation unit 31, a noise prediction unit 32, a vertical scanning circuit 33, and a pixel unit 100.

As shown in FIG. 2, the pixel unit 100 has a plurality of pixels 10 arranged in a two-dimensional matrix. The pixel unit 100 is divided into a VOB area 101, a HOB area 102, and an opening area 103. The VOB region 101 and the HOB region 102 are light-shielding regions (Optical Black region: OB region) in which the pixels 10 are optically shaded, and have a plurality of pixels 10 that are shielded from light. The aperture region 103 is a region in which the pixel 10 receives light from the lens unit 1001 (FIG. 7), and has a plurality of pixels 10 that are not shielded from light.

The vertical scanning circuit 33 supplies the row selection pulse PSEL, the reset pulse PRES, and the transfer pulse PTX to the pixel unit 100 in row units, and controls the signal output operation of the pixel 10 in row units. Further, the vertical scanning circuit 33 selects the rows of the pixels 10 in order from the upper part to the lower part of the pixel unit 100 in the read operation of one frame. That is, in the one-frame read operation, reading is started from the VOB area 101.

The column readout circuit 20 includes a plurality of constant current circuits 22 provided in each column, a signal amplification circuit 23, a comparator 24, a counter circuit 25, and a CDS circuit 26, which are shown in FIG. It has a transfer memory 27. The column reading circuit 20 outputs the pixel signal of the VOB region 101 to the noise prediction unit 32 among the pixel signals read from the pixel unit 100, and outputs the pixel signal of the opening region 103 to the image pickup signal processing circuit 1005 (FIG. 7). Output to.

The noise prediction unit 32 measures the amount of random noise from the pixel signal in the VOB region 101, and determines the inclination of the reference signal of the reference signal generation unit 31 and the AD conversion number Nmax. Further, the image pickup apparatus 1 can suppress the quantization error at the time of reading out the VOB area 101 by setting the value of N to N = 1 when reading out the VOB area 101.

The value of N when reading the VOB region 101 is preferably determined by a method for measuring the random noise amount of the noise prediction unit 32 or a method for measuring the quantization error, and is not limited to the above value. For example, it is possible to observe the frequency of the pixel signal in the VOB region 101 and simply measure the quantization error by utilizing the property that the frequency is concentrated so that the quantization error occurs. In that case, N The value of may be set to a value larger than 1.

Further, in the present embodiment, the noise prediction unit 32 is said to be in the image pickup apparatus 1, but if the pixel signal in the VOB region 101 can be monitored, it is in the image pickup signal processing circuit 1005 shown in FIG. May be good. In that case, the image pickup signal processing circuit 1005 controls the reference signal generation unit 31 in the image pickup device 1 by outputting the value of Nmax determined by the image pickup signal processing circuit 1005 to the image pickup device 1.

FIG. 9 is a flowchart showing a read operation of one frame. When the reading of one frame is started, in step S901, the noise prediction unit 32 sets N = 1 for the reference signal generation unit 31. The vertical scanning circuit 33 selects and reads out the pixel rows in the VOB region 101. The pixels in the VOB region 101 output N signals and S signals in order. At this time, the reference signal generation unit 31 outputs the reference signal Vramp1 to the comparator 24 as shown in FIG. The column readout circuit 20 performs AD conversion of the N signal and the S signal of the VOB area 101 in order, and outputs the pixel signal of the VOB area 101 to the noise prediction unit 32.

In step S902, the noise prediction unit 32 measures the standard deviation Vrms of the random noise amount from the pixel signal in the VOB region 101, determines Nmax as the N value using the equation (1), and determines the reference signal generation unit 31. Control. The noise prediction unit 32 controls the slope of the reference signal VrampN and the number of AD conversions with Nmax as the N value.

In step S903, the vertical scanning circuit 33 sequentially selects and reads out the HOB region 102 and the aperture region 103 in pixel row units. At this time, the reference signal generation unit 31 outputs the controlled reference signal VrampN to the comparator 24. The image pickup apparatus 1 AD-converts the N signal and the S signal of the HOB region 102 and the aperture region 103 by the number of AD conversions after control using the reference signal VrampN, and generates a pixel signal of the HOB region 102 and the aperture region 103. do. By these operations, the reading operation of one frame is completed.

As described above, the noise prediction unit 32 can more accurately measure the random noise amount by actually measuring the standard deviation Vrms of the random noise amount using the pixel signal of the VOB area 101 immediately before reading the opening area 103. It can be grasped and the optimum Nmax can be determined. As a result, the image pickup apparatus 1 can obtain good image quality in which false signals due to quantization error are suppressed while suppressing the amount of random noise.

Although the preferred embodiments of the present invention have been described above, the present invention is not limited to these embodiments, and various modifications and modifications can be made within the scope of the gist thereof.

1: Image pickup device, 10: Pixel, 23: Signal amplification circuit, 24: Comparator, 25: Counter circuit, 26: CDS circuit, 27: Horizontal transfer memory, 31: Reference signal generation unit, 32: Noise prediction unit

Claims (12)

Multiple pixels, each of which outputs a signal based on photoelectric conversion,
An analog-to-digital conversion unit that converts a signal based on the photoelectric conversion from analog to digital by comparing the signal based on the photoelectric conversion with a reference signal that changes with time.
It is characterized by having a control unit that controls the inclination of the reference signal and the number of times the signal based on the photoelectric conversion is converted from analog to digital according to the amount of random noise included in the signal based on the photoelectric conversion. Imaging device. The control unit predicts the amount of random noise contained in the signal based on the photoelectric conversion, and converts the inclination of the reference signal and the signal based on the photoelectric conversion from analog to digital according to the predicted random noise amount. The image pickup apparatus according to claim 1, wherein the number of times of noise generation is controlled. 1. 2. The imaging device according to 2. It further has an amplification unit that amplifies the signal based on the photoelectric conversion at the gain set value.
One of claims 1 to 3, wherein the control unit controls the slope of the reference signal and the number of times the signal based on the photoelectric conversion is converted from analog to digital according to the gain set value. The image pickup apparatus according to item 1. The control unit is any of claims 1 to 3, wherein the control unit controls the inclination of the reference signal and the number of times the signal based on the photoelectric conversion is converted from analog to digital according to the temperature of the image pickup apparatus. The image pickup apparatus according to item 1. The control unit is characterized in that it controls the inclination of the reference signal and the number of times the signal based on the photoelectric conversion is converted from analog to digital according to the gain set value and the temperature of the image pickup apparatus. 4. The imaging device according to 4. The plurality of pixels have a light-shielded pixel and a non-light-shielded pixel.
The control unit determines the inclination of the reference signal and the signal based on the photoelectric conversion according to the value obtained by converting the signal based on the photoelectric conversion of the light-shielded pixel from analog to digital by the analog-digital conversion unit. Control the number of conversions from analog to digital,
The analog-to-digital conversion unit converts a signal based on the photoelectric conversion of the shaded pixel by the inclination of the reference signal controlled by the control unit and the number of times the signal based on the photoelectric conversion is converted from analog to digital. The image pickup apparatus according to claim 1, wherein the image pickup device is converted from analog to digital. Claim 1 is characterized in that, as the amount of random noise increases, the control unit increases the absolute value of the slope of the reference signal and increases the number of times the signal based on the photoelectric conversion is converted from analog to digital. The imaging device according to any one of 7 to 7. The analog-to-digital conversion unit is
A comparison unit that compares a signal based on the photoelectric conversion with a reference signal that changes with time.
It has a counter unit that counts the count value according to the result of the comparison.
The image pickup apparatus according to any one of claims 1 to 8, wherein the count value of the counter unit represents a value obtained by converting a signal based on the photoelectric conversion from analog to digital. The counter unit is characterized in that, when the number of times the signal based on the photoelectric conversion is converted from analog to digital is a plurality of times, the count value corresponding to the plurality of conversions is accumulated and counted. Item 9. The imaging device according to item 9. Each of the plurality of pixels outputs a signal based on reset release,
Any of claims 1 to 10, wherein the analog-to-digital conversion unit converts a signal based on the reset release from analog to digital by comparing the signal based on the reset release with the reference signal. The image pickup apparatus according to item 1. It is a control method of an image pickup apparatus having a plurality of pixels, each of which outputs a signal based on photoelectric conversion.
A conversion step of converting a signal based on the photoelectric conversion from analog to digital by comparing the signal based on the photoelectric conversion with a reference signal that changes with time.
It is characterized by having a slope of the reference signal and a control step of controlling the number of times the signal based on the photoelectric conversion is converted from analog to digital according to the amount of random noise included in the signal based on the photoelectric conversion. Control method of the image pickup device.

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