JP2013051575A - Solid-state imaging device, imaging device, and imaging method - Google Patents

Abstract

PROBLEM TO BE SOLVED: To enable accurate execution of AD conversion processing.SOLUTION: A reference signal of first gain and a reference signal of second gain different from the first gain that are reference signals for converting a level of an analog pixel signal obtained from a pixel into digital data are generated in reading a pixel reset level and in reading a pixel data level, the level of the analog pixel signal is compared with the reference signals, count processing is performed in parallel with the comparison processing, and a count value at the time of completion of the comparison processing with the reference signal of the first gain or the reference signal of the second gain is acquired as the digital data.

Description

  The present technology relates to a solid-state imaging device, an imaging device, and an imaging method, and more particularly, to a solid-state imaging device, an imaging device, and an imaging method that can accurately perform AD conversion processing.

  In recent years, MOS (Metal Oxide Semiconductor) and CMOS (Complementary Metal-Oxide Semiconductor) type image sensors that can overcome various problems of CCD (Charge Coupled Device) image sensors have attracted attention as examples of solid-state imaging devices. ing.

  For example, a CMOS image sensor has an amplifying circuit such as a floating diffusion amplifier for each pixel. When reading a pixel signal, one row in the pixel array unit is selected as an example of address control. A so-called column-parallel output type or column type is often used in which row signals are accessed simultaneously and in units of rows, that is, pixel signals are read from the pixel array unit simultaneously in parallel for all pixels in one row. ing.

  Further, in the solid-state imaging device, there is a method in which an analog pixel signal read from the pixel array unit is converted into digital data by an analog-digital conversion device (AD conversion device; Analog Digital Converter) and then output to the outside. Sometimes taken.

  The present applicant has previously proposed to perform AD conversion quickly in a CMOS image sensor (for example, Patent Document 1).

  In the previous proposal, as in the single slope column ADC system, the reset signal Srst is counted down as the P phase with the gain A and the count value becomes Trst, and then the signal level Ssig is counted up as the D phase with the gain A. The count value is Tsig_A. After the predetermined signal region, the D-phase signal level Ssig is counted up with a gain B lower than the gain A, and the count value becomes Tsig_B.

  In this specification, P-phase readout means readout of a pixel reset signal, and D-phase readout means readout of a pixel data signal.

JP 2008-136043 A

  However, in the previous proposal, there is a possibility that the data near the switching of the gain loses linearity and a gap is generated in the output image.

  The first factor is that the difference in comparator output delay time due to the difference in gain results in the difference in comparator delay between gains being included in the CDS result. The comparator output delay time is a delay time from when the two signals compared by the comparator match until the output of the comparator is inverted.

  In the count execution unit, the count operation is executed when the comparator output is in an inactive (normal rotation) state, and the count is stopped when the comparator output is in an active (inversion) state. One of the input signals of the comparator is a pixel signal voltage, which is ideally a constant voltage, and the other is a stepped reference signal, and the latter is changed to perform a comparison operation. That is, the comparator output is inverted when the two signals match.

  However, in practice, there is a comparator output delay time in which the output is inverted after a predetermined time after the magnitudes of the two signals coincide. Since the count operation is stopped after the delay time, the count value for the comparator output delay time is actually included in the P-phase count value and the D-phase count value. Further, the comparator output delay time varies depending on the amount of change of the reference signal, that is, the gain.

  Therefore, in the conventional method, in the area where the pixel data level is read with the gain A, the count numbers corresponding to the comparator output delay times included in the count value Trst_A and the count value Tsig are the same. Accordingly, the comparator output delay time of the count values of the P phase and the D phase is canceled by the countdown / up of the CDS. However, when switching to gain B, the comparator output delay time of gain A and gain B is different, so the difference in delay time remains in the count value, and the AD conversion value for the pixel signal value at the gain switching point The continuity of will be lost.

  As a second factor, there is a phenomenon that the continuity of data is lost because the slope of the reference signal becomes dull at the time of gain switching and the linearity is not maintained as the characteristic of the DAC generating the reference signal by switching the gain. .

  Normally, the slack of the slope occurs in both the P phase and the D phase within a short period of time immediately after the start of the generation of the reference signal. It is canceled by D-phase CDS calculation.

  However, in the case of the conventional method, since the gain is switched during the D-phase count, the count value corresponding to the dullness of the gain A and the gain B is included in the D-phase data, and the dulling amount corresponding to the gain A by the CDS. However, the count value corresponding to the dullness of the gain B remains.

  The present technology has been made in view of such a situation, and an object thereof is to perform AD conversion processing more accurately.

  The solid-state imaging device according to the present technology is a reference signal for converting the level of an analog pixel signal obtained from a pixel into digital data, and is different from the reference signal of the first gain and the first gain. A generating unit configured to generate the reference signal having the second gain at the time of reading a pixel reset level and a pixel data level; a comparing unit that compares the level of the analog pixel signal with the reference signal; and A counting unit that performs a counting process in parallel with the comparison process and obtains a count value at a time when the comparison process of the reference signal of the first gain or the reference signal of the second gain is completed as the digital data A solid-state imaging device.

  A holding unit for holding the comparison result of the comparison unit is further provided, and the counting unit can select a count value obtained earlier and a count value obtained later based on the held comparison result.

  The generation unit outputs a first reference signal of the first gain from a first initial value and a second reference signal of the second gain from a second initial value at the time of reading the pixel reset level. When the pixel data level is generated and read, the third reference signal of the first gain from the first initial value and the fourth reference signal of the second gain from the second initial value are generated. Can be generated.

  When the second reference signal is generated between the one reference signal of the first gain and the other reference signal of the first gain, the count unit is one of the reference signals of the first gain. The count value based on the reference value can be held, and the count value can be used as an initial value when counting based on the other reference signal.

  Of the first gain and the second gain, the count processing at the time of reading the pixel reset level and the reading of the pixel data level by the larger reference signal can be performed at adjacent timings.

  Based on the gain of the count value selected by the count unit, a correction unit that corrects a difference in digital value resolution depending on the magnitude of the reference signal of the first gain and the reference signal of the second gain Can further be provided.

  The counting unit can perform the counting by multiplying by a ratio of the first gain and the second gain.

  The generation unit omits generation of one of the reference signal of the first gain and the reference signal of the second gain at the time of reading out the pixel data level, and generates only the other, Optical black level data can be subtracted from the count value based on the other reference signal generated.

  The imaging device according to the present technology is a reference signal for converting the level of an analog pixel signal obtained from a pixel into digital data, and the reference signal having a first gain is different from the first gain. A generating unit that generates the reference signal having a gain of 2 at the time of pixel reset level reading and pixel data level reading, a comparison unit that compares the level of the analog pixel signal and the reference signal, and A counting unit that performs a counting process in parallel with the comparison process, and obtains a count value at the time when the comparison process of the reference signal of the first gain or the reference signal of the second gain is completed as the digital data; It is.

  The imaging method according to the present technology is a reference signal for converting the level of an analog pixel signal obtained from a pixel into digital data, and the reference signal having a first gain is different from the first gain. The reference signal having a gain of 2 is generated when the pixel reset level is read and when the pixel data level is read, the level of the analog pixel signal is compared with the reference signal, and the count process is performed in parallel with the comparison process. In the imaging method, the count value at the time when the comparison process of the reference signal of the first gain or the reference signal of the second gain is completed is acquired as the digital data.

  In the solid-state imaging device according to the present technology, the generation unit is a reference signal for converting the level of the analog pixel signal obtained from the pixel into digital data, the reference signal having a first gain, and the first gain The reference signal having a second gain different from the gain of 1 is generated when the pixel reset level is read and the pixel data level is read, and the comparison unit compares the level of the analog pixel signal with the reference signal, and counts The unit performs a count process in parallel with the comparison process, and obtains the count value at the time when the comparison process of the reference signal of the first gain or the reference signal of the second gain is completed as the digital data To do.

  According to the present technology, it is possible to accurately perform AD conversion processing.

It is a schematic block diagram of the CMOS solid-state imaging device which is one embodiment of the solid-state imaging device according to the present technology. It is a figure which shows the structural example of a unit pixel. It is a block diagram which shows the structure of a voltage comparison part and a counter part. It is a block diagram which shows the structural example of a count execution part. 3 is a timing chart for explaining an operation in a column AD circuit. 3 is a timing chart for explaining an operation in a column AD circuit. 3 is a timing chart for explaining an operation in a column AD circuit. 3 is a timing chart for explaining an operation in a column AD circuit. 3 is a timing chart for explaining an operation in a column AD circuit. It is a block diagram which shows the structural example of a count execution part. 3 is a timing chart for explaining an operation in a column AD circuit. 3 is a timing chart for explaining an operation in a column AD circuit. 3 is a timing chart for explaining an operation in a column AD circuit. 3 is a timing chart for explaining an operation in a column AD circuit. 3 is a timing chart for explaining an operation in a column AD circuit. It is a figure showing the composition of the 1 embodiment of the imaging device concerning this art.

Hereinafter, modes for carrying out the present technology (hereinafter referred to as embodiments) will be described. The description will be given in the following order.
1 Overview of Solid-State Imaging Device 2 Details of Reference Signal Generation Unit and Column AD Circuit 3 Configuration of Pixel Unit 4 Configuration of Voltage Comparison Unit and Counter Unit 5 Configuration of Count Execution Unit 6 AD Conversion Operation 7 Imaging Device 8 Other

  The present technology relates to a solid-state imaging device which is an example of a semiconductor device for physical quantity distribution detection, and an imaging device using the solid-state imaging device. In the solid-state imaging device, for example, a plurality of unit components that are sensitive to electromagnetic waves input from the outside such as light and radiation are arranged. The physical quantity distribution converted into an electric signal by the unit component is read out as an analog electric signal, converted into digital data, and then output to the outside.

  Hereinafter, embodiments of the present technology will be described in detail with reference to the drawings. In the following, a case where a CMOS solid-state imaging device, which is an example of an XY address type solid-state imaging device, is used as a device will be described as an example. The CMOS solid-state imaging device will be described on the assumption that all pixels are made of NMOS.

  However, this is an example, and the target device is not limited to the MOS type solid-state imaging device. All the semiconductor device for physical quantity distribution detection in which a plurality of unit components that are sensitive to electromagnetic waves input from outside such as light and radiation are arranged in a line or matrix form, and all implementations described later. The form of can be similarly applied.

<Overview of solid-state imaging device>

  FIG. 1 is a schematic configuration diagram of a CMOS solid-state imaging device which is an embodiment of the solid-state imaging device of the present technology.

  The solid-state imaging device 1 includes a pixel unit in which a plurality of pixels including a light receiving element (an example of a charge generation unit) that outputs a signal corresponding to an incident light amount is arranged in rows and columns (that is, in a two-dimensional matrix). . In the solid-state imaging device 1, the signal output from each pixel is a voltage signal, and a CDS (Correlated Double Sampling) processing function unit, a digital conversion unit (ADC: Analog Digital Converter), and the like are arranged in parallel. It is provided.

  “A CDS processing function unit and a digital conversion unit are provided in parallel in a column” means that a plurality of CDS processing function units in substantially parallel to a vertical signal line (an example of a column signal line) 19 in a vertical column This means that a digital conversion unit is provided.

Each of the plurality of functional units is disposed only on one end side in the column direction with respect to the pixel array unit 10 (an output side disposed on the lower side in FIG. 1) when the device is viewed in plan. It may be in the form. Alternatively, the pixel array unit 10 is arranged separately on one edge side in the column direction (output side arranged on the lower side in FIG. 1) and the other edge side on the opposite side (upper side in FIG. 1). It may be in the form of being made. In the latter case, it is preferable that the horizontal scanning unit that performs readout scanning (horizontal scanning) in the row direction is also arranged separately on each edge side so that each can operate independently.

  For example, as a typical example in which a CDS processing function unit and a digital conversion unit are provided in parallel in a column, a CDS processing function unit and a digital conversion unit are arranged for each vertical column in a portion called a column area provided on the output side of the imaging unit. And is a column type that sequentially reads out to the output side. Further, not only the column type (column parallel type) but also a mode in which one CDS processing function unit or digital conversion unit is assigned to a plurality of adjacent (for example, two) vertical signal lines 19 (vertical columns). You can also. Further, one CDS processing function unit or digital conversion unit is allocated to every N vertical signal lines 19 (vertical columns) every N (N is a positive integer; N-1 in between). Forms can also be taken.

  Except for the column type, in any form, a plurality of vertical signal lines 19 (vertical columns) commonly use one CDS processing function unit and digital conversion unit. Therefore, a switching circuit (switch) that supplies pixel signals for a plurality of columns supplied from the pixel array unit 10 side to one CDS processing function unit or digital conversion unit is provided. Depending on the subsequent processing, it is necessary to take measures such as providing a memory for holding the output signal.

  In any case, it is possible to adopt a form in which one CDS processing function unit or digital conversion unit is assigned to a plurality of vertical signal lines 19 (vertical columns). Thereby, the signal processing of each pixel signal is performed after being read out in units of pixel columns, so that the configuration in each unit pixel can be simplified as compared with the case where similar signal processing is performed in each unit pixel. . In addition, it is possible to cope with the increase in the number of pixels, the size reduction, and the cost reduction of the image sensor.

  In addition, one row of pixel signals can be processed in parallel by a plurality of signal processing units arranged in parallel in a column, so that one CDS processing function unit or digital conversion unit can be provided on the output circuit side or outside the device. Therefore, the signal processing unit can be operated at a lower speed than when processing is performed. This is advantageous in terms of power consumption, bandwidth performance, noise, and the like. In other words, when the power consumption and bandwidth performance are the same, the entire sensor can be operated at high speed.

  In the case of a column type configuration, it can be operated at a low speed, which is advantageous in terms of power consumption, bandwidth performance, noise, and the like, and has an advantage that a switching circuit (switch) is unnecessary. In the following embodiments, this column type will be described unless otherwise specified.

  As shown in FIG. 1, the solid-state imaging device 1 according to the present embodiment includes a pixel array unit 10, which is also referred to as a pixel unit or an imaging unit in which a plurality of unit pixels 3 are arranged in rows and columns, and a pixel array unit 10. Drive control unit 7 provided outside the pixel, a read current source unit 24 for supplying an operation current (read current) for reading a pixel signal to the unit pixels 3 of the pixel array unit 10, and a column AD circuit arranged for each vertical column 25, a column processing unit 26, a reference signal generation unit 27 that generates a reference signal Vslop for AD conversion and supplies the reference signal Vslop to the column processing unit 26, and an output unit 29. Each of these functional units is provided on the same semiconductor substrate.

  The reference signal Vslop may be a signal having a waveform (for example, a ramp waveform) that changes linearly with a certain slope as a whole, and the change may have a smooth slope shape. It may be one that changes stepwise.

  The column AD circuit 25 according to the present embodiment has a function of an AD converter that converts the reset level Srst and the signal level Ssig, which are reference levels of the pixel signal So, into digital data independently. Further, the column AD circuit 25 has a function of a difference processing unit. That is, a function of acquiring digital data of a signal component indicated by a difference between the reset level Srst and the signal level Ssig by executing a difference process between the AD conversion result of the reset level Srst and the AD conversion result of the signal level Ssig. It has.

  In addition, an AGC (Auto Gain Control) circuit having a signal amplification function or the like can be provided in the same semiconductor region as the column processing unit 26 as needed before or after the column processing unit 26. When AGC is performed before the column processing unit 26, analog amplification is performed. When AGC is performed after the column processing unit 26, digital amplification is performed. If the n-bit digital data is simply amplified, the gradation may be lost. Therefore, it is preferable to perform digital conversion after amplification by analog.

  The drive control unit 7 has a control circuit function for sequentially reading signals from the pixel array unit 10. For example, the drive control unit 7 generates a horizontal scanning circuit (column scanning circuit) 12 that controls column addresses and column scanning, a vertical scanning circuit (row scanning circuit) 14 that controls row addresses and row scanning, and an internal clock. And a communication / timing control unit 20 having functions such as

  Although not shown in the drawing, a clock conversion unit that is an example of a high-speed clock generation unit and generates a pulse having a clock frequency faster than the input clock frequency may be provided. The communication / timing control unit 20 generates an internal clock based on the input clock (master clock) CLK0 input via the terminal 5a and the high-speed clock generated by the clock conversion unit.

  By using a signal derived from the high-speed clock generated by the clock converter, AD conversion processing and the like can be operated at high speed. Also, motion extraction and compression processing requiring high-speed calculation can be performed using a high-speed clock. Furthermore, the parallel data output from the column processing unit 26 can be converted into serial data and the video data D1 can be output outside the device. By doing so, it is possible to adopt a configuration in which high-speed operation output is performed with a smaller number of terminals than the number of bits of AD-converted digital data.

  In FIG. 1, some of the rows and columns are omitted for the sake of simplicity, but in reality, tens to thousands of unit pixels 3 are arranged in each row and each column. The unit pixel 3 is typically composed of a photodiode as a light receiving element (charge generation unit) and an in-pixel amplifier having an amplifying semiconductor element (for example, a transistor).

  The intra-pixel amplifier is not limited as long as it can output the signal charge generated and accumulated in the charge generation unit of the unit pixel 3 as an electric signal, and various configurations can be adopted. A floating diffusion amplifier configuration is used. For example, with respect to the charge generation unit, potentials of a read selection transistor that is an example of a charge readout unit (transfer gate unit / read gate unit), a reset transistor that is an example of a reset gate unit, a vertical selection transistor, and a floating diffusion A CMOS sensor having an amplifier transistor having a source follower configuration, which is an example of a detection element that detects a change, can be used as a CMOS sensor (see, for example, FIG. 2 described later).

  Alternatively, as described in Japanese Patent No. 2708455, an amplifying transistor connected to a drain line (DRN) for amplifying a signal voltage corresponding to the signal charge generated by the charge generating unit, and the charge generating unit It is also possible to use a transistor composed of three transistors, each having a reset transistor for resetting and a read selection transistor (transfer gate portion) scanned from a vertical shift register via a transfer wiring (TRF). .

  Note that the solid-state imaging device 1 can make the pixel array unit 10 compatible with color imaging by using a color separation (color separation) filter. That is, color separation comprising a combination of a plurality of color filters for capturing a color image on a light receiving surface on which electromagnetic waves (light in this example) of each charge generation unit (photodiode, etc.) in the pixel array unit 10 are incident. By providing any one of the color filters in, for example, a so-called Bayer array, it is possible to capture color images.

  The unit pixel 3 includes a vertical scanning unit 14 via a row control line 15 for row selection, a column processing unit 26 in which a column AD circuit 25 is provided for each vertical column via a vertical signal line 19, Each is connected. Here, the row control line 15 indicates the entire wiring that enters the pixel from the vertical scanning unit 14.

  The horizontal scanning circuit 12 has a function of a reading scanning unit that reads a count value from the column processing unit 26 to the horizontal signal line 18.

  Each element of the drive control unit 7 such as the horizontal scanning unit 12 and the vertical scanning circuit 14 is integrally formed with the pixel array unit 10 in a semiconductor region such as single crystal silicon using a technique similar to the semiconductor integrated circuit manufacturing technique. And configured as a solid-state imaging device which is an example of a semiconductor system.

  Each of these functional units is a so-called one-chip unit (provided on the same semiconductor substrate) integrally formed in a semiconductor region such as single crystal silicon using a technique similar to the semiconductor integrated circuit manufacturing technique. As a CMOS image sensor which is an example of a semiconductor system, the solid-state imaging device 1 according to the present embodiment is configured to form a part.

  In addition, the solid-state imaging device 1 may be configured as one chip in which each unit is integrally formed in the semiconductor region. Although not shown, in addition to various signal processing units such as the pixel array unit 10, the drive control unit 7, and the column processing unit 26, an optical system such as a photographing lens, an optical low-pass filter, or an infrared light cut filter. It is good also as a module-like form which has the imaging function packaged together in the state which also contains.

  The horizontal scanning unit 12 and the vertical scanning unit 14 include, for example, a decoder, and start a shift operation (scanning) in response to control signals CN1 and CN2 supplied from the communication / timing control unit 20. . Therefore, for example, the row control line 15 includes various pulse signals (for example, pixel reset pulse RST, transfer pulse TRG, drain line control pulse DRN, etc.) for driving the unit pixel 3.

  Although not shown, the communication / timing control unit 20 includes a functional block of a timing generator TG (an example of a read address control device) that supplies a clock signal necessary for the operation of each unit and a pulse signal having a predetermined timing. The communication / timing control unit 20 receives a master clock CLK0 supplied from an external main control unit (for example, a camera control unit 900 in FIG. 16 described later) via a terminal 5a, and receives an external main control signal via a terminal 5b. A function block of a communication interface that receives data instructing an operation mode supplied from the control unit and outputs data including information of the solid-state imaging device 1 to an external main control unit is provided.

  For example, the horizontal address signal is output to the horizontal decoder 12a and the vertical address signal is output to the vertical decoder 14a, and each decoder 12a, 14a receives it and selects a corresponding row or column.

  At this time, since the unit pixels 3 are arranged in a two-dimensional matrix, analog pixel signals generated by the pixel signal generation unit 5 and output in the column direction via the vertical signal lines 19 are arranged in a row unit (column parallel). (In) Access and capture (vertical) scan reading is performed. Then, by accessing the row direction, which is the arrangement direction of the vertical columns, and reading the pixel signal (in this example, digitized pixel data) to the output side (horizontal) scan reading, the pixel signal or It is preferable to increase the reading speed of pixel data. Of course, not only scanning reading but also random access for reading out only the information of the necessary unit pixel 3 is possible by directly addressing the unit pixel 3 to be read out.

  In the communication / timing control unit 20, the clock CLK1 having the same frequency as the input clock (master clock) CLK0 input via the terminal 5a, a clock obtained by dividing the clock CLK1, or a low-speed clock obtained by further dividing the device are used as devices. For example, the horizontal scanning unit 12, the vertical scanning unit 14, the column processing unit 26, and the like. Hereinafter, the clocks divided by two and the clocks with lower frequencies are collectively referred to as a low-speed clock CLK2.

  The vertical scanning unit 14 selects a row of the pixel array unit 10 and supplies a necessary pulse to the row. For example, a vertical decoder 14a that defines a readout row in the vertical direction (selects a row of the pixel array unit 10), and a row control line 15 for the unit pixel 3 on the readout address (in the row direction) defined by the vertical decoder 14a. And a vertical drive unit 14b for driving by supplying pulses. Note that the vertical decoder 14a selects a row for electronic shutter, in addition to a row from which a signal is read.

  The horizontal scanning unit 12 sequentially selects the column AD circuit 25 of the column processing unit 26 in synchronization with the low-speed clock CLK2, and guides the signal to a horizontal signal line (horizontal output line) 18. For example, the horizontal decoder 12a (which selects individual column AD circuits 25 in the column processing unit 26) that defines the horizontal readout column, and each of the column processing unit 26 according to the readout address that is defined by the horizontal decoder 12a. A horizontal drive unit 12b for guiding a signal to the horizontal signal line 18. For example, if the number of horizontal signal lines 18 is n (n is a positive integer) handled by the column AD circuit 25, for example, 10 (= n) bits, 10 horizontal signal lines 18 are arranged corresponding to the number of bits. .

  In the solid-state imaging device 1 having such a configuration, the pixel signal output from the unit pixel 3 is supplied to the column AD circuit 25 of the column processing unit 26 via the vertical signal line 19 for each vertical column.

  Each column AD circuit 25 of the column processing unit 26 receives the analog signal So of the pixels for one column and processes the analog signal So. For example, each column AD circuit 25 has an ADC circuit that converts an analog signal into, for example, a 10-bit digital signal using, for example, a low-speed clock CLK2.

  As the AD conversion processing in the column processing unit 26, a method is adopted in which analog signals held in parallel in units of rows are subjected to AD conversion in parallel for each row using the column AD circuit 25 provided for each column. At this time, a single slope integration type (or ramp signal comparison type) AD conversion technique is used. Since this method can realize an AD converter with a simple configuration, it has a feature that the circuit scale does not increase even if it is provided in parallel.

  In the single slope integration type AD conversion, the analog processing target signal is converted into a digital signal based on the time from the start of conversion until the reference signal Vslop matches the processing target signal voltage. As a mechanism for this, in principle, a ramp-like reference signal Vslop is supplied to the comparator (voltage comparison unit 252), and counting with the clock signal is started. Then, the analog pixel signal input via the vertical signal line 19 is compared with the reference signal Vslop, thereby performing AD conversion by counting the number of clocks until a pulse signal indicating the comparison result is obtained.

  At this time, by devising the circuit configuration, so-called CDS processing can be performed together with AD conversion. That is, for the voltage mode pixel signal input via the vertical signal line 19, the signal level immediately after pixel reset (referred to as noise level or reset level) and the true signal level Vsig (depending on the amount of received light) Can be processed. As a result, noise signal components called fixed pattern noise (FPN) and reset noise can be removed.

<Details of reference signal generator and column AD circuit>

  The reference signal generation unit 27 includes a DA conversion circuit (DAC: Digital Analog Converter) 27a. The reference signal generator 27 generates a reference signal Vslop, which is a stepped sawtooth wave, in synchronization with the count clock CKdac from the initial value indicated by the control data CN4 from the communication / timing controller 20. The generated stepped sawtooth reference signal Vslop is supplied to each column AD circuit 25 of the column processing unit 26 as a reference voltage (ADC standard signal) for AD conversion. Although not shown, a noise prevention filter may be provided.

  The reference signal Vslop is faster than the reference signal Vslop generated based on the master clock CLK0 input via the terminal 5a, for example, based on a high-speed clock generated based on the multiplied clock generated by the multiplier circuit. Can be changed.

  The control data CN4 supplied from the communication / timing control unit 20 to the DA conversion circuit 27a of the reference signal generation unit 27 is time-dependent so that the reference signal Vslop for each comparison process basically has the same slope (change rate). It also includes information that makes the rate of change of digital data the same. Specifically, in synchronization with the count clock CKdac, the count value is changed by one per unit time, and the count value is converted into a voltage signal by a current addition type DA converter circuit.

  The DA conversion circuit 27a of the present embodiment can change the change characteristic (specifically, the slope) of the reference signal Vslop under the control of the communication / timing control unit 20.

  The inclination of the reference signal Vslop can be adjusted with high accuracy by adopting, for example, a method of changing the frequency (clock period) of the count clock CKdac. For example, the count clock CKdac supplied to the DA converter circuit 27a is set to the same speed as the count clock CKO, or double speed or quadruple speed with respect to the count clock CKO. Can do. “^” Represents a power.

Note that the method of changing the slope of the reference signal Vslop shown here is an example, and the method is not limited to such a method. For example, while keeping the cycle of the count clock CKdac given to the reference signal generator 27, the counter output value is x, the slope (rate of change) of the reference signal Vslop included in the control data CN4 is β, and the initial potential value is As α, the potential y calculated by the following equation (1) can be output.
y = α−β * x (1)

  Further, an arbitrary circuit can be used such as adjusting the voltage change ΔSLP for each count clock CKdac based on the information indicating the slope (rate of change) of the lamp voltage included in the control data CN4. The adjustment of the slope of the reference signal Vslop can be realized by adjusting ΔSLP per clock by changing the current amount of the unit current source, for example, in addition to changing the clock cycle.

  The column AD circuit 25 includes a voltage comparison unit (comparator) 252 and a counter unit 254, and has an n-bit AD conversion function. The voltage comparison unit (comparator) 252 receives the reference signal Vslop generated by the DA conversion circuit 27a of the reference signal generation unit 27 and the vertical signal line 19 (from the unit pixel 3 for each row control line 15 (V0, V1,...). The analog pixel signals obtained via H0, H1,. The counter unit 254 counts the time until the voltage comparison unit 252 completes the comparison process, and holds the result.

  In the present embodiment, the reference signal Vslop is commonly supplied from the DA converter circuit 27a to the voltage comparison units 252 arranged for each column, and the pixel signal voltage Vx that each voltage comparison unit 252 takes charge of is used as a common reference. Comparison processing is performed using the signal Vslop.

  The communication / timing control unit 20 functions as a control unit that switches the count processing mode in the counter unit 254 according to which of the reset level Vrst and the signal component Vsig of the pixel signal the voltage comparison unit 252 is performing comparison processing. have. From this communication / timing control unit 20, a control signal CN5 for instructing whether the counter unit 254 operates in the down-count mode or the up-count mode is input to the counter unit 254 of each column AD circuit 25. ing. The control signal CN5 includes a count mode control signal UDC, a data holding control pulse HLDC, a count clock control signal TH, etc., which will be described later.

  One input terminal RAMP of the voltage comparison unit 252 is shared with the input terminal RAMP of the other voltage comparison unit 252. The stepped reference signal Vslop generated by the reference signal generation unit 27 is input to the input terminal RAMP, and the corresponding vertical column vertical signal lines 19 are connected to the other input terminals, respectively. Pixel signal voltages from 10 are individually input. The output signal of the voltage comparison unit 252 is supplied to the counter unit 254.

  The count clock CKO from the communication / timing control unit 20 is input to the clock terminal CK of the counter unit 254 in common with the clock terminals CK of the other counter units 254.

  The counter unit 254 is not shown in its configuration, but can be realized by changing the wiring form of the data storage unit 256 formed of a latch to a synchronous counter form. With the input of one count clock CKO, An internal count is performed. Similarly to the reference signal Vslop, the count clock CKO can also use a multiplied clock (high-speed clock) generated by a multiplier circuit. In this case, the count clock CKO is more than using the master clock CLK0 input through the terminal 5a. High resolution can be achieved.

  Regardless of the count mode, the counter unit 254 uses a common up / down counter (U / D CNT) to perform a count process by switching between a down count operation and an up count operation (specifically, alternately). It is configured to be possible.

  As the counter unit 254 of the present embodiment, it is preferable to use an asynchronous counter whose count output value is output without being synchronized with the count clock CKO. Basically, a synchronous counter can be used, but in the case of a synchronous counter, the operation of all flip-flops (counter basic elements, for example, flip-flop 511 in FIG. 4 described later) is limited by the count clock CKO. Is done. Therefore, when higher frequency operation is required, the counter unit 254 uses an asynchronous counter suitable for high speed operation because its operation limit frequency is determined only by the limit frequency of the first flip-flop (counter basic element). Is more preferable.

  A control pulse is input to the counter unit 254 from the horizontal scanning circuit 12 through the control line 12c. The counter unit 254 has a latch function for holding the count result, and holds the counter output value until an instruction by a control pulse through the control line 12c is given.

  On the output side of each column AD circuit 25, for example, the output of the counter unit 254 can be connected to the horizontal signal line 18. Alternatively, as shown in the figure, a data storage unit 256 as an n-bit memory device that holds the count result held by the counter unit 254, and the counter unit 254 and the data storage unit 256 are arranged at the subsequent stage of the counter unit 254. It is also possible to adopt a configuration comprising a switch 258 arranged in

  When the configuration including the data storage unit 256 is adopted, the switch 258 receives a memory transfer instruction pulse CN8 as a control pulse from the communication / timing control unit 20 at a predetermined timing in common with the switches 258 in the other vertical columns. Supplied. When the memory transfer instruction pulse CN8 is supplied, the switch 258 transfers the count value of the corresponding counter unit 254 to the data storage unit 256. The data storage unit 256 holds and stores the transferred count value.

  Note that the mechanism for holding the count value of the counter unit 254 in the data storage unit 256 at a predetermined timing is not limited to the configuration in which the switch 258 is arranged between them. For example, it can be realized by controlling the output enable of the counter unit 254 with the memory transfer instruction pulse CN8 while directly connecting the counter unit 254 and the data storage unit 256. Alternatively, it can also be realized by using the memory transfer instruction pulse CN8 as a latch clock for determining the data take-in timing of the data storage unit 256.

  A control pulse is input to the data storage unit 256 from the horizontal scanning circuit 12 through the control line 12c. The data storage unit 256 holds the count value fetched from the counter unit 254 until there is an instruction by a control pulse through the control line 12c.

  The horizontal scanning circuit 12 reads the count value held by each data storage unit 256 in parallel with the voltage comparison unit 252 and the counter unit 254 of the column processing unit 26 performing the processing that they are responsible for. It has the function of a readout scanning unit.

  The output of the data storage unit 256 is connected to the horizontal signal line 18. The horizontal signal line 18 has a signal line of an n-bit width which is the bit width of the column AD circuit 25, and is connected to the output circuit 28 via n sense circuits corresponding to the respective output lines (not shown). The

  In particular, if the data storage unit 256 is provided, the count result held by the counter unit 254 can be transferred to the data storage unit 256. Therefore, the counting operation of the counter unit 254, that is, the AD conversion process and the reading operation of the count result to the horizontal signal line 18 can be controlled independently, and the AD conversion process and the signal reading operation to the outside can be performed. Pipeline operations performed in parallel can be realized.

  In such a configuration, the column AD circuit 25 performs a count operation in the pixel signal readout period corresponding to the horizontal blanking period, and outputs a count result at a predetermined timing. That is, first, the voltage comparison unit 252 compares the reference signal of the ramp waveform voltage from the reference signal generation unit 27 with the pixel signal voltage input via the vertical signal line 19, and when both voltages are the same. The comparator output of the voltage comparator 252 is inverted. For example, the voltage comparison unit 252 sets the H level such as the power supply potential to the inactive state, and transitions to the L level active state when the pixel signal voltage matches the reference signal Vslop.

  The counter unit 254 starts the count operation in the down count mode or the up count mode in synchronization with the ramp waveform voltage generated from the reference signal generation unit 27. When the counter output is notified to the counter unit 254, the counter unit 254 stops the count operation and latches (holds / stores) the count value at that time as pixel data to complete the AD conversion. .

  Thereafter, the counter unit 254 sequentially stores the stored and held pixel data in the column based on the shift operation by the horizontal selection signal CH (i) input from the horizontal scanning circuit 12 through the control line 12c at a predetermined timing. The data is output from the output terminal 5c outside the processing unit 26 and outside the chip having the pixel array unit 10.

  Although not specifically illustrated because it is not directly related to the description of the present embodiment, other various signal processing circuits and the like are also included in the components of the solid-state imaging device 1.

<Configuration of pixel portion>

  FIG. 2 is a diagram illustrating a configuration example of the unit pixel 3 illustrated in FIG. The configuration of the unit pixel (pixel cell) 3 in the pixel array unit 10 is the same as that of a normal CMOS image sensor, and in this embodiment, a general-purpose 4TR configuration can be used as the CMOS sensor. Further, for example, as described in Japanese Patent No. 2708455, a 3TR configuration including three transistors can be used. Of course, these pixel configurations are merely examples, and any CMOS image sensor array configuration can be used.

  For example, a floating diffusion amplifier configuration is used as the intra-pixel amplifier. For example, with respect to the charge generation unit, potentials of a read selection transistor that is an example of a charge readout unit (transfer gate unit / read gate unit), a reset transistor that is an example of a reset gate unit, a vertical selection transistor, and a floating diffusion A CMOS sensor having a general-purpose four-transistor configuration (that is, a 4TR configuration) having an amplifying transistor having a source follower configuration, which is an example of a detection element for detecting a change, can be used.

  For example, the unit pixel 3 having a 4TR configuration illustrated in FIG. 2 includes a charge generation unit 32 having both a photoelectric conversion function of receiving light and converting the light into a charge, and a charge storage function of storing the charge. Then, with respect to the charge generation unit 32, a read selection transistor (transfer transistor) 34 which is an example of a charge readout unit (transfer gate unit / read gate unit), a reset transistor 36 which is an example of a reset gate unit, and a vertical selection The transistor 40 and the amplifying transistor 42 having a source follower configuration, which is an example of a detection element that detects a potential change of the floating diffusion 38, are included.

  The unit pixel 3 includes a pixel signal generation unit 5 having an FDA (Floating Diffusion Amp) configuration including a floating diffusion 38 which is an example of a charge injection unit having a function of a charge storage unit. The floating diffusion 38 is a diffusion layer having parasitic capacitance.

  The read selection transistor (second transfer unit) 34 is driven via a transfer wiring (read selection line TX) 55 by a transfer drive buffer BF1 to which a transfer signal φTRG is supplied. The reset transistor 36 is driven via a reset wiring (RST) 56 by a reset driving buffer BF2 to which a reset signal φRST is supplied. The vertical selection transistor 40 is driven via a vertical selection line (SEL) 52 by a selection drive buffer BF3 to which a vertical selection signal φVSEL is supplied. Each drive buffer can be driven by the vertical drive unit 14 b of the vertical scanning unit 14.

  The reset transistor 36 in the pixel signal generation unit 5 has a source connected to the floating diffusion 38 and a drain connected to the power supply Vdd, and a pixel reset pulse RST is input to the gate (reset gate RG) from the reset drive buffer.

  For example, in the vertical selection transistor 40, the drain is connected to the source of the amplification transistor 42, the source is connected to the pixel line 51, and the gate (particularly, the vertical selection gate SELV) is connected to the vertical selection line 52. The connection configuration is not limited to this, and the drain may be connected to the power supply Vdd, the source may be connected to the drain of the amplifying transistor 42, and the vertical selection gate SELV may be connected to the vertical selection line 52.

  A vertical selection signal SEL is applied to the vertical selection line 52. The amplification transistor 42 has a gate connected to the floating diffusion 38, a drain connected to the power source Vdd via the vertical selection transistor 40, a source connected to the pixel line 51, and further connected to the vertical signal line 53 (19). It is like that.

  Further, one end of the vertical signal line 53 extends to the column processing unit 26 side, and the read current source unit 24 is connected along the path, and a substantially constant operating current (read) is performed between the vertical signal line 53 and the amplifying transistor 42. A source follower configuration in which (current) is supplied is adopted.

  Specifically, the read current source unit 24 includes an NMOS type transistor (in particular, a load MOS transistor) 242 provided in each vertical column, a current generation unit 245 shared by all the vertical columns, and a gate and a drain. And a reference current source unit 244 having an NMOS type transistor 246 whose source is connected to the source line 248.

  Each load MOS transistor 242 has a drain connected to the vertical signal line 53 of the corresponding column and a source connected in common to a source line 248 that is a ground line. As a result, the load MOS transistors 242 in each vertical column are connected to each other so as to function as a current source with respect to the vertical signal line 19 by connecting the gates to the transistor 246 of the reference current source unit 244 to form a current mirror circuit. Has been.

  The source line 248 is connected to the ground (GND) which is the substrate bias at the end in the horizontal direction (the left and right vertical columns in FIG. 1), and the operating current (reading current) with respect to the ground of the load MOS transistor 242 is It is configured to be supplied from both ends.

  A load control signal SFLACT for outputting a predetermined current only when necessary is supplied to the current generation unit 245 from a load control unit (not shown). When the signal is read, the current generation unit 245 receives an active state of the load control signal SFLACT so that the load MOS transistor 242 connected to each amplification transistor 42 continues to flow a predetermined constant current. It has become. In other words, the load MOS transistor 242 makes a signal output to the vertical signal line 53 by assembling the amplifying transistor 42 and the source follower in the selected row and supplying the read current to the amplifying transistor 42.

  In such a 4TR configuration, the floating diffusion 38 is connected to the gate of the amplifying transistor 42. As a result, the amplifying transistor 42 outputs a signal corresponding to the potential of the floating diffusion 38 (hereinafter referred to as FD potential) to the vertical signal line 19 (53) via the pixel line 51 in the voltage mode.

  The reset transistor 36 resets the floating diffusion 38. The read selection transistor (transfer transistor) 34 transfers the signal charge generated by the charge generator 32 to the floating diffusion 38. A large number of pixels are connected to the vertical signal line 19. To select a pixel, the vertical selection transistor 40 is turned on only for the selected pixel. Then, only the selected pixel is connected to the vertical signal line 19, and the signal of the selected pixel is output to the vertical signal line 19.

<Configuration of voltage comparison unit and counter unit>

  FIG. 3 is a block diagram illustrating the configuration of the voltage comparison unit 252 and the counter unit 254.

  Each vertical signal line 19 shown in the horizontal direction in FIG. 3 is shown in the vertical direction in FIG. When the pixel signal voltage Vx read from the pixel array unit 10 matches the reference signal Vslope supplied from the reference signal generation unit 27, the voltage comparison unit 252 in each column corresponding to each vertical signal line 19 compares. Inverts the output VCO from the inactive state to the active state.

  The counter unit 254 includes a latch unit 501, a clock / clear control unit 502, and a count execution unit 503.

  In the present technology, different gains are read out. Which gain result is selected and output is controlled as follows. In other words, the latch unit 501 holds whether the comparator output VCO is inverted during the previous reading (with the first gain) during the reading of the D phase period. When the latch unit output Vrst is inverted before the subsequent reading (with the second gain) (in the active state), the result of the previous reading is output as the final result. On the other hand, when the latch unit output Vrst is not inverted (when inactive), the previous CDS result is reset and the D phase at the subsequent gain is read.

  At that time, it is necessary to perform a CDS operation for subtracting the P-phase signal from the D-phase signal, and the P-phase signal to be subtracted needs to be read with the same gain as the D-phase signal. In general, since the P-phase signal is read before the D-phase signal, it is necessary to store the P-phase signal having the same gain read earlier. For this purpose, the count execution unit 503 is provided with latch units (PREG) 513_00 to 513_09 (described later with reference to FIG. 4) that hold the count of the P-phase signal.

  The clock / clear control unit 502 controls the output of the count clock CKO and the clear signal CLR supplied from the AD conversion control unit 20A to the count execution unit 503 based on the output Vrst of the latch unit 501. The count execution unit 503 performs a count operation based on the count clock CIN and the clear signal CLR from the clock / clear control unit 502.

  The AD conversion control unit 20 </ b> A configured by the communication / timing control unit 20 supplies the gain change instruction signal CHNG to the reference signal generation unit 27. Further, the AD conversion control unit 20A supplies the count execution unit 503 with the count mode control signal UDC, the data holding control pulse HLDC, the count clock control signal TH, the through signal RT, and the hold signal RH.

  The gain change instruction signal CHNG uses a value for setting a gain suitable for the noise characteristics of the pixels and circuits, and the gain setting on / off timing is supplied from an external main control unit. In addition, on / off timings of other control signals are also supplied from an external main control unit.

  In the present technology, AD conversion of a plurality of gains is performed during 1H, that is, one horizontal scanning period. The AD conversion output result finally output from the counter unit 254 is an AD conversion result of one gain. Which gain result is output is determined by the state of the comparator output VCO at the time of the D-phase read executed first. For this purpose, the result of the comparator output VCO of the voltage comparison unit 252 is stored in the latch unit 501. Based on the output Vrst of the latch unit 501, the clock / clear control unit 502 controls the output of the count clock CKO and the clear signal CLO at the time of AD conversion operation with another gain to be executed later. Controls whether to operate.

  When the comparator output VCO (output Vrst of the latch unit 501) is in an inactive state, the clock / clear control unit 502 transmits the input count clock CKO as it is to the count execution unit 503 as the count clock CIN. On the other hand, when the comparator output VCO (the output Vrst of the latch unit 501) is inverted to the active state, the clock / clear control unit 502 stops the transmission of the count clock CKO (that is, the output of the count clock CIN).

  When the output of the count clock CIN is stopped, the count execution unit 503 stops the operation of the counter and holds a count value reflecting the pixel signal voltage Vx at that time. That is, the count execution unit 503 converts the pixel signal voltage Vx into digital data and holds it.

<Configuration of count execution unit>

  FIG. 4 is a diagram illustrating a configuration example of the count execution unit 503 of the counter unit 254. Here, a configuration corresponding to 10 bits is shown. In FIG. 4, one count execution unit 503 corresponding to one vertical signal line 19 is configured by a group of components shown in the horizontal direction including D-type flip-flops (FF) 511_00 to 511_09. . Note that the flip-flops 511_00 to 511_09 are simply referred to as flip-flops 511 when it is not necessary to distinguish them individually. The same applies to other components.

  The count execution unit 503 in each column corresponding to each vertical signal line 19 has, as a basic configuration, an asynchronous counter in which D-type flip-flops 511_00 to 511_09 are connected in cascade and the count output of the previous stage is input to the clock terminal CK of the subsequent stage. The structure is adopted.

  Further, each flip-flop 511 adopts a configuration capable of controlling on / off of the hold function for the inverted output NQ when returning its inverted output NQ to the D input terminal. In addition, between the stages, there is a function unit for switching the count mode to either up-counting or down-counting, and whether the count clock is a pulse based on the count output of the previous stage or the count clock CIN from the clock / clear control unit 502 And a function unit for switching whether to do.

  Specifically, the count execution unit 503 first includes flip-flops 511_00 to 511_09. Further, the count execution unit 503 can hold the data of the inverting output terminal NQ between the inverting output terminal NQ of the flip-flops 511_00 to 511_09 (indicated by a bar above Q in the figure) and the D input terminal. Data holding units (HOLD) 512_00 to 512_09. The data holding units 512_00 to 512_09 are controlled by respective data holding control pulses HLDC00 to 09. The data holding unit 512 has a function of holding the count output regardless of the input state of the flip-flop 511, and can be realized by, for example, exclusive OR.

  For example, the data holding unit 512 holds the input data (the inverted output NQ of the flip-flop 511) when the data holding control pulse HLDC is active H (H: high level), and is inactive L (L: low level). The holding operation is released, and the input data (inverted output NQ of the flip-flop 511) is directly transmitted to the D input terminal of the flip-flop 511.

  In addition, latch units 513_00 to 513_09 capable of holding data of the inverted output terminal NQ are provided between the inverted output terminals NQ and D input terminals of the flip-flops 511_00 to 511_09. The latch units 513_00 to 513_09 are controlled by respective hold signals RH00 to 09 and through signals RT00 to 09.

  The latch unit 513 holds input data (the inverted output NQ of the flip-flop 511) when the hold signal RH is input. When the through signal RT is input, the latch unit 513 cancels the holding operation and transmits the input data (the inverted output NQ of the flip-flop 511) to the D input terminal of the flip-flop 511 as it is. That is, the retained data is set as an initial value in the flip-flop 511.

  A reset control signal CLR is commonly input to the reset terminal R of each flip-flop 511. For example, when the reset control signal CLR is active H, the flip-flop 511 sets the non-inverted output Q to L level and the inverted output NQ to H level.

  In addition, the count execution unit 503 includes count mode switching units (U / D) 514_00 to 514_08 that switch the count mode to one of up-counting and down-counting between the stages of the flip-flops 511. The count mode switching unit 514 switches whether to output the data of the inverted output terminal NQ of the previous flip-flop 511 as it is or to invert the data based on the count mode control signal UDC. The count mode switching unit 514 can be realized by, for example, exclusive OR.

  For example, the count mode switching unit 514 has the inverted output terminal NQ of the flip-flop 511 so that the count execution unit 503 performs an up-count operation when the count mode control signal UDC is at a high level and performs a down-count operation when the count mode control signal UDC is at a low level. Toggles inversion / non-inversion of data.

  The count execution unit 503 includes count clock switching units (SEL) 515_00 to 515_08 in the subsequent stage of the count mode switching unit 514 between the stages of the flip-flops 511. Count clock switching units (SEL) 515_00 to 515_08 switch the output pulse of the count mode switching unit 514 and the count clock CIN from the clock / clear control unit 502 based on the count clock control signals TH00 to TH08. To the clock terminal CK of the flip-flop 511.

  The count clock switching units 515_00 to 515_08 are controlled by different count clock control signals TH00 to TH08. In the count clock control signals TH00 to TH08, the front side becomes active first, and the rear side becomes active at a predetermined timing sequentially delayed (details will be described later).

  For example, the count clock switching unit 515 transmits the output of the count mode switching unit 514 when the count clock control signal TH is inactive L. When the count clock control signal TH is switched to active H, the count clock switching unit 515 transmits the count clock CIN from the clock / clear control unit 502.

  In the example shown in FIG. 4, the count clock switching unit 515 is wired so as to handle the clock pulse input to the preceding flip-flop 511 for each column as a form of taking in the count clock CIN from the clock / clear control unit 502. ing.

  In the example shown in FIG. 4, when the count clock CIN is sequentially transmitted to the flip-flop 511 on the upper bit side, the data output itself of the lower flip-flop 511 is treated as invalid, but actually remains operating. It has become.

  The count execution unit 503 operates as an asynchronous binary counter. In addition, the count execution unit 503 operates the count clock switching unit 515 based on the count clock control signal TH. Thus, the count execution unit 503 has a function of transmitting the clock input of each flip-flop 511 to the clock input of the flip-flop 511 on the subsequent stage side (upper bit side).

  In other words, the higher-speed clock used for the lower-order bit output is sequentially transmitted to the subsequent stage (upper-bit side) at a predetermined timing, so that the high-order bit output frequency dividing operation with respect to the count clock CIN is sequentially performed at a higher speed. It is supposed to continue. For example, what has been divided by ¼ with respect to the count clock CIN before switching can be changed to perform ½ division with respect to the count clock CIN after switching.

  After the count clock is switched, the count operation (frequency division operation) is performed with a clock faster than the previous clock. Therefore, by adjusting the relationship with the slope of the reference signal Vslop, the linearity of the AD conversion can be improved. High-speed AD conversion is possible while maintaining. This point will be described in detail later.

  Note that the count clock CKO supplied to the counter unit 254 does not change the frequency, and adopts a mechanism for speeding up the frequency dividing operation for each bit by the above-described countermeasure in the counter unit 254. As a result, a situation in which the power consumption greatly increases in the counter unit 254 does not occur.

  Although it is conceivable to increase the frequency of the count clock CKO as a mechanism for speeding up the frequency division operation, in this case, the entire counter unit 254 operates at a high speed, resulting in an increase in power consumption. When increasing the slope of the reference signal Vslop, the frequency of the count clock CKdac supplied from the communication / timing controller 20 to the DAC 27a is increased. In this case as well, the power consumption increases in the reference signal generation unit 27, but the counter unit 254 is arranged in each column in the column processing unit 26. Therefore, the degree of “increase in power consumption” depends on the column processing. The unit 26 is larger than the reference signal generation unit 27 in comparison.

  Considering this, the reference signal generation unit 27 employs a method of increasing the frequency of the count clock CKdac to increase the inclination of the reference signal Vslop with high accuracy. It is preferable not to increase the power consumption. For this purpose, it is effective to take a mechanism for speeding up the frequency division operation for each bit by the above-described countermeasure in the counter unit 254 while keeping the frequency of the count clock CKO constant.

<Operation of AD conversion>

  FIG. 5 is a timing chart for explaining the operation in the column AD circuit 25. Hereinafter, with reference to FIG. 5, signal acquisition difference processing in the column AD circuit 25 during AD conversion operation will be described.

  At time t1, the vertical drive circuit 14b sets the pixel selection signal VSEL to active H and sets the pixel reset signal RST to active H, thereby resetting the readout pixel. The reset voltage of this pixel is Srst. At the same time, the AD conversion control unit 20A sets the clear signal CLO to active H and sets the count value of the count execution unit 503 to zero. That is, the clock / clear control unit 502 outputs a clear signal CLR and clears each flip-flop 511 when the clear signal CLO from the AD conversion control unit 20A becomes active H.

  Next, a process of reading the reset voltage with a gain a (a gain smaller than a gain b described later) is performed. That is, at time t10, the AD conversion control unit 20A outputs the gain change instruction signal CHNG to the reference signal generation unit 27, and generates a ramp wave of gain a from the voltage of the initial value SLP_ini_a as the reference signal. The counter operation is also synchronized with the ramp wave clock, so that the counter counts down the count clock CIN until the reference signal Vslop matches the pixel reset voltage Srst. In order to execute the countdown operation, the AD conversion control unit 20A outputs an inactive L count mode control signal UDC to the count mode switching unit 514.

  At this time, the AD conversion control unit 20A sets the data holding control pulse HLDC supplied to the data holding unit 512 to inactive L, does not hold the input data (inverted output NQ of the flip-flop 511), and directly inputs it to the D input terminal. Let them enter.

  When the reference signal Vslop coincides with the pixel reset voltage Srst at time t12, the comparator output VCO is inverted from the high level H to the low level L through a predetermined comparator output delay time. At this time, the clock / clear control unit 502 stops supplying the count clock CIN to the count execution unit 503. As a result, the count operation is stopped, and the pixel reset level Vrst_a is AD converted to the count value Drst_a. Since the countdown is performed, the count value Drst_a is a negative value.

  Next, at time t14, the AD conversion control unit 20A sets the hold signal RH to active H, and causes the latch unit 513 to store the reset level Drst_a. This stored value is read at time t36, which will be described later, and set in the flip-flop 511 as the initial value of the count value.

  As described above, the AD conversion processing with the P-phase gain a is performed.

  Next, a process of reading the reset voltage with a gain b (a gain larger than the above-described gain a, that is, a gain with a small inclination of the reference signal Vslop) is performed.

  At time t16, the AD conversion control unit 20A sets the counter clear signal CLO to active H. As a result, the counter is cleared and the count value becomes zero.

  When the lamp voltage reaches the initial value SLP_ini_b of gain b (a value different from the initial value SLP_ini_a of gain a), AD conversion control unit 20A outputs gain change instruction signal CHNG to reference signal generation unit 27 at time t20. The reference signal Vslop with the gain b is generated from the voltage of the initial value SLP_ini_b. The counter operation is also synchronized with the ramp wave clock, so that the counter counts down until the reference signal Vslop matches the pixel reset voltage Srst. In order to execute the countdown operation, the AD conversion control unit 20A outputs an inactive L count mode control signal UDC to the count mode switching unit 514.

  When the reference signal Vslop matches the pixel voltage Vx_0 at time t21, the comparator output VCO is inverted. At this time, the count is stopped, and the reset voltage level Vrst_b at the gain b is AD converted as the count value Drst_b. Since the countdown is performed, the count value Drst_b is a negative value.

  Thus, AD conversion processing with the P-phase gain b is performed.

  Next, a process of transferring the optical charge accumulated in the charge generation unit 32 to the floating diffusion 38 is performed. That is, D-phase reading is performed. Therefore, first, at time t22, the AD conversion control unit 20A sets the count mode control signal UDC of the count mode switching unit 514 to active H in order to cause the counter to perform a count-up operation.

  In the period from time t24 to t26, the vertical drive circuit 14b sets the pixel transfer signal TRG to active H. As a result, the pixel voltage Vx_0 changes by a voltage (Vsig) corresponding to the pixel light signal amount.

  At time t30, AD conversion processing with the same gain b as that at the time of reading the previous P phase is started. Also in this case, when the reference signal Vslop reaches the initial value SLP_ini_b of the gain b, the AD conversion control unit 20A sends the gain change instruction signal CHNG to the reference signal generation unit 27 when the reference signal Vslop reaches the initial value SLP_ini_b of the gain b. The reference signal Vslop of gain b is generated from the voltage of the initial value SLP_ini_b.

  Based on the concept of the quantization step, it is determined in advance which voltage of the pixel voltage is to be read with a large gain b, and counting is performed for the count up to that voltage. In the example of FIG. 5, since the pixel voltage Vx_0 has a voltage level higher than the total count value Dsig_b at the gain b, the reference signal Vslop does not match the pixel voltage Vx_0, and the count up for all counts is performed until time t32. Has been done. For this reason, the comparator output VCO is not inverted. In this case, as will be described later, since readout is further performed with a smaller gain a, a voltage with a predetermined threshold value becomes a gain switching point.

  As described above, AD conversion processing with the D-phase gain b is performed. However, the count value Dsig_b obtained at this time does not represent the pixel data level because the pixel voltage Vx_0 does not match the reference signal Vslop.

  At time t34 immediately after the end of the count operation, the AD conversion control unit 20A sets the latch signal VCOHL of the latch unit 501 to active H. Accordingly, the latch unit 501 latches the comparator output VCO of the voltage comparison unit 252. In this case, it is stored that the comparator output VCO is not inverted.

  At time t36, the AD conversion control unit 20A outputs the through signal RT to the latch unit 513. Now, the output Vrst of the latch unit 501 indicates that the comparator output VCO of the voltage comparison unit 252 is not inverted. Therefore, the count value Drst_a of the pixel reset level of gain a held in the latch unit 513 at time t14 is forcibly set in the flip-flop 511.

  At time t40, AD conversion processing with gain a is started. Also in this case, the AD conversion control unit 20A generates the gain change instruction signal CHNG as the reference signal when the ramp voltage reaches the initial value SLP_ini_a of the gain a, as in the case of reading the P phase with the first gain a. The reference signal Vslop with a gain a is generated from the voltage of the initial value SLP_ini_a.

  At time t42, the count up is performed until the reference signal Vslop coincides with the pixel voltage Vx_0 and the comparator output VCO is inverted after a predetermined comparator output delay time. As a result, the pixel data level Vrst_a is AD converted as the count value Dsig with the gain a. This count value Dsig is the count value that is finally output.

  Since the count-up starts from the pixel reset level Drst_a counted down by the gain a, the final count value Dsig is AD conversion of the differential voltage between the pixel reset level and the pixel data level at the gain a, that is, at the same gain. The value obtained by CDS. As a result, noise signal components such as fixed pattern noise and reset noise can be removed.

  Further, since the gain at the time of counting the count value Drst_a of the pixel reset level and the count value Dsig of the pixel data level is the gain a, the comparator output delay time is the same. Therefore, the comparator output delay time is canceled by the CDS processing. In addition, the influence of the slack of the slope immediately after the generation of the reference signal Vslop is canceled out by the CDS processing.

  On the other hand, FIG. 6 shows the case where the value of the pixel voltage Vx_0 when reading the pixel data level started from time t30 is small and the magnitude of the gain b is within the reading region in the same AD conversion operation as that of FIG. An example is shown.

  In the case of the example of FIG. 6, AD conversion processing with the gain b is started at time t30. Also in this case, when the reference signal Vslop reaches the initial value SLP_ini_b of the gain b, the AD conversion control unit 20A sends the gain change instruction signal CHNG to the reference signal generation unit 27 when the reference signal Vslop reaches the initial value SLP_ini_b of the gain b. The reference signal Vslop of gain b is generated from the voltage of the initial value SLP_ini_b.

  At time t32, since the reference signal Vslop matches the pixel voltage Vx_0, the comparator output VCO is inverted after a predetermined comparator output delay time, and the count stops. As a result, the pixel data level Vsig is AD converted with the gain b as the count value Dsig.

  Since the count-up starts from the count value Drst_b of the pixel reset level counted down by the gain b, the final count value Dsig is AD conversion of the differential voltage between the pixel reset level and the pixel data level at the gain b, that is, the same This is the value obtained by performing CDS with gain. As a result, noise signal components such as fixed pattern noise and reset noise can be removed.

  Next, at time t34, the latch signal VCOHL is set to active H, and the comparator output VCO of the voltage comparison unit 252 is held in the latch unit 501. Since the comparator output VCO of the voltage comparison unit 252 is inverted, the output Vrst of the latch unit 501 is also inverted.

  When the output Vrst of the latch unit 501 is inverted, the clock / clear control unit 502 stops outputting the count clock CKO as it is as the count clock CIN. Thereby, the count operation is not performed, and the through signal RT of the latch unit 513 at the subsequent time t36 is substantially invalidated, and the count value held at the time t32 is maintained as it is. In other words, the AD conversion read count operation with the gain a from the time t40 to the time t42 is not executed.

  As a result, the AD conversion count value Dsig held at time t32 becomes the final CDS read value. With respect to readout with a larger gain b, the readout time of the pixel reset signal and the readout timing of the pixel data signal are adjacent to each other, and a noise removal effect can be expected by the cutoff frequency characteristic of the CDS.

  Further, since the gain at the time of counting the count value Drst_b of the pixel reset level and the count value Dsig of the pixel data level is the gain b, the comparator output delay time is the same. Therefore, the comparator output delay time is canceled by the CDS processing. In addition, the influence of the slack of the slope immediately after the generation of the reference signal Vslop is canceled out by the CDS processing.

  As is clear from comparison between FIG. 5 and FIG. 6, in the present technology, bright pixels are AD-converted with a large gain as shown in FIG. 5, and dark pixels are small as shown in FIG. 6. AD conversion is performed with the gain.

  Other effects of the examples of FIGS. 5 and 6 are as follows.

1 Compared to analog CDS, noise conversion is highly effective because AD conversion is performed with a digital CDS with a higher sampling frequency for high gain reading.
2 For CDS with low gain readout, the gain switching point for signal readout is set in an area where background noise can be ignored, so there is no problem even if the sampling frequency has a low noise removal effect in CDS.
3. The readout gain setting method sets the optimal quantization step and gain switching point from the relationship between background noise and light shot noise. On the other hand, in the conventional method, a quantization step that allows the full count value of the bit width of the AD converter mounted on the sensor to cover the pixel saturation signal amount is set as the 0 dB gain of the sensor. Therefore, the quantization step on the low gain side of the present method is set to be coarser than the 0 dB gain of the conventional method, so the full count value on the low gain side is smaller than the full count value of the conventional method. As a result, the total count value of AD conversion can be reduced, and AD conversion time and power consumption are reduced.
4. In the high gain read count, the gain switching point is set depending on the relationship between the light shot noise and the background noise, but the count value is kept low. As described above, the low gain count value is small. Further, when the comparator inversion signal is sent to the subsequent circuit and the processing to match the difference in data weight depending on the gain in the subsequent circuit, the AD converter only needs to guarantee the bit width of the read count value at each gain. . That is, the number of bits of the AD converter can be suppressed to a bit width smaller than the bit width that can be expressed by AD conversion of the pixel signal amount. As a result, the number of circuit components of the AD converter can be reduced.
5. In the conventional method, when a bright part and a dark part of the subject are mixed, when a dark part is to be imaged, the bright part is whitened in order to perform readout with high gain. On the other hand, when it is desired to take an image of a bright place, the dark place is blacked out without gradation. However, this method uses high-gain readout for dark places and low-gain places for bright places, so that even dark places can be imaged with gradation, while bright places can be read, so the readout range is wide. It will be possible. That is, it is not necessary to set the gain that has been required so far.

  FIG. 7 shows an example in which counting is performed by multiplying the minimum count resolution that performs the counting operation at the time of reading with the gain a by the ratio of the gain a and the gain b. That is, in the embodiment of FIGS. 5 and 6, the minimum resolution of the gain a and gain b counts is 1. That is, the change in voltage per unit time, that is, the potential difference per count was 1. As a result, when the read result is gain a, it is necessary to correct the count value of the AD conversion result after the horizontal transfer by multiplying the gain ratio b / a. For this reason, for example, a correction unit 301 can be provided as shown in FIG. However, if the count itself is counted at a gain ratio multiple as in the embodiment of FIG. 7, the processing after horizontal transfer becomes unnecessary, and the configuration can be simplified. That is, the count value Drst_a in FIG. 7 is a value b / a times the count value Drst_a in FIGS. 5 and 6, and the count value Dsig in FIG. 7 is a value b / a times the count value Dsig in FIG. It is.

  FIG. 8 shows an embodiment of a different method of AD conversion operation. In this method, first, CDS reading including reading of a pixel reset level and a pixel data level with a gain b is performed. In this example, the count value Drst_b of the pixel reset level Vrst_b is obtained by counting down by reading from the time t10 with the gain b.

  At time t16, the count mode control signal UDC is set to active H, and the count up mode is set. By reading out from time t20, the count value (Drst_b + Dsig_b) of the pixel data level is obtained by counting up. However, the value of the pixel voltage Vx_0 when reading the pixel data level is large, and the pixel voltage Vx_0 and the reference signal Vslop do not cross each other. Therefore, the count value (Drst_b + Dsig_b) of this pixel data level does not correspond to the actual pixel data level.

  Therefore, immediately after the pixel data level is read, the latch signal VCOHL is set to active H at time t24. In the case of the example of FIG. 8, the pixel data level does not reach the voltage corresponding to all the counts of the gain b, the comparator output VCO of the voltage comparison unit 252 is not inverted, and the data in the latch unit 501 remains unchanged. At time t26, the counter reset signal CLO is set to active H, whereby the count value is cleared to zero.

  Next, readout of the pixel data level and readout of the pixel reset level at the gain a are performed. At time t30, a reference signal Vslop with a gain a is generated from the voltage of the initial value SLP_ini_a. At time t32, since the reference signal Vslop matches the pixel voltage Vx_0, the comparator output VCO of the voltage comparison unit 252 is inverted and the count-up operation is stopped. As a result, a count value (Drst_a + Dsig) is obtained.

  Further, pixel reset is performed at time t33, and the pixel voltage Vx_0 becomes the pixel reset level Srst. At time t36, the count mode control signal UDC is set to inactive L, and the countdown mode is set. At time t40, a reference signal Vslop with a gain a is generated from the voltage of the initial value SLP_ini_a and compared with the pixel reset level Srst. The countdown operation stops when the comparator output VCO of the voltage comparison unit 252 is inverted at time t42. Since the count value (Drst_a + Dsig) is counted down by the count value Drst_a of the pixel reset level, the count value Dsig is obtained.

  The AD conversion result with the gain b is cleared at time t26, and the difference count Dsig between the pixel data signal and the pixel reset signal with the gain a becomes the final count value.

  FIG. 9 shows an example in the case where the pixel data level at the gain b started from the time t20 is small and within the readout region of the gain b in the same AD conversion operation as in FIG. At time t20, a reference signal Vslop with a gain b is generated from the voltage of the initial value SLP_ini_b. At time t22, since the reference signal Vslop matches the pixel voltage Vx_0, the comparator output VCO of the voltage comparison unit 252 is inverted, and the count-up operation is stopped. As a result, a count value (Drst_b + Dsig) is obtained.

  Further, at time t24, the latch signal VCOHL is set to active H, and the data in the latch unit 501 is inverted. As a result, the counter clear signal CLO and the counter clock signal are gated. Therefore, at time t26, the counter clear signal CLO is set to active H, but the CDS result Dsig of gain b is held as the count value. Furthermore, the subsequent pixel data signal and pixel reset signal readout count operations at gain a are also stopped, and as a result, a CDS result at gain b is output.

  The method shown in FIGS. 8 and 9 does not require the latch unit 513 for storing the readout result of the pixel reset level with the low gain (that is, gain a), which is necessary in the embodiment shown in FIGS. This is a method that can keep the increase in the amount low.

  In low gain readout, there is a pixel reset (pixel reset at time t33 in FIG. 8) between readout of the pixel reset level and readout of the pixel data level, so kTC noise (ie pixel reset noise) is canceled by the CDS. However, since the read result is used from the region where the signal level is relatively high, the noise component is not conspicuous.

  FIG. 10 is a block diagram illustrating a configuration example of the count execution unit 503 in the reading method of FIGS. 8 and 9. This configuration is a configuration in which the latch unit 513 in the count execution unit 503 shown in FIG. 4 is omitted, and the other configuration is the same as that of the count execution unit 503 shown in FIG.

  That is, in the case of the readout method of FIGS. 5 to 7, since the P phase and D phase of gain b are read during the readout of the P phase and D phase of gain a, the reading of the P phase of gain a is performed. It is necessary to hold the result until the D phase is read. For this reason, the latch part 513 is required.

  On the other hand, in the case of the readout method of FIGS. 8 and 9, D phase readout is performed following P phase readout of gain b, and D phase readout is performed following P phase readout of gain a. . Therefore, the latch portion 513 is not necessary.

  Therefore, the count execution unit 503 in FIG. 10 is simplified in configuration and can be manufactured at a lower cost than the case shown in FIG.

  FIG. 11 shows still another embodiment of the AD conversion operation method. In this embodiment, first, CDS reading with gain b is performed at times t10 and t20.

  That is, the reference signal Vslop with the gain b is generated from the voltage of the initial value SLP_ini_b at time t10. At time t12, since the reference signal Vslop matches the pixel voltage Vx_0, the comparator output VCO of the voltage comparison unit 252 is inverted and the countdown operation is stopped. Thereby, the count value Drst_b is obtained.

  Further, in the period from time t14 to t18, the vertical drive circuit 14b sets the pixel transfer signal TRG to active H. As a result, the pixel voltage Vx_0 changes by a voltage (Vsig) corresponding to the pixel light signal amount. At time t20, a reference signal Vslop with a gain b is generated from the voltage of the initial value SLP_ini_b. At time t22, the count-up operation stops because the maximum value is reached before the reference signal Vslop matches the pixel voltage Vx_0. As a result, a count value (Drst_b + Dsig_b) is obtained. However, the comparator output VCO of the voltage comparison unit 252 is not inverted, and this count value (Drst_b + Dsig_b) does not correspond to the pixel data level.

  Next, at time t24, the latch signal VCOHL is set to active H, and the comparator output VCO of the voltage comparison unit 252 is latched. In this case, since the comparator output VCO is not inverted, the data in the latch unit 501 is not inverted, and the count value is cleared to 0 by the counter clear CLO at time t26.

  Next, a process of reading the pixel data level with a gain a is executed. At time t30, a reference signal Vslop with a gain a is generated from the voltage of the initial value SLP_ini_a. At time t32, since the reference signal Vslop matches the pixel voltage Vx_0, the comparator output VCO of the voltage comparison unit 252 is inverted and the count-up operation is stopped. As a result, a count value (Drst_a + Dsig) is obtained.

  After the horizontal transfer of the AD conversion result by the horizontal drive circuit 12b, the data of the horizontal optical black level (OPB (Optical Black) area) stored in advance in a line buffer or the like is used as the pixel reset level by the correction unit 301 to obtain the AD conversion result. Is subtracted from CD to perform pseudo CDS. That is, since the optical black level value Vob is substantially equal to the pixel reset level Drst_a, the optical black level value Vob stored in the line buffer of the correction unit 301 is subtracted from the count value (Drst_a + Dsig). Therefore, it is possible to perform CDS in a pseudo manner. In this case, the latch data of the comparator output VCO of the voltage comparison unit 252 is also horizontally transferred so that it can be determined that the reading is performed with the gain a, and when it is inverted, the subtraction process is performed with the OPB data.

  When substituting the horizontal OPB, a function capable of reading out the horizontal OPB area while changing the gain during one frame period is added, and not only the data of the gain b but also the data of the gain a are required. The gain a can be read out.

  In order to perform reading with the gain b and gain a in the OPB region, the following method can be considered.

  For example, reading with the gain b in the OPB region can be performed as shown in FIG. 11, and reading with the gain a in the OPB region can be performed as shown in FIG.

  In the example of FIG. 12, by setting the pixel reset signal RST to active H at time t1, the readout pixel is reset and the pixel voltage Vx_0 becomes the pixel reset level Srst. At time t14, the pixel transfer signal TRG is set to active H, and the pixel voltage Vx_0 changes from the pixel reset level Srst to the pixel data level Vsig.

  At time t30, a reference signal Vslop with a gain a is generated from the voltage of the initial value SLP_ini_a of the gain b. At time t32, the reference signal Vslop coincides with the pixel voltage Vx_0 and is counted up until the comparator output VCO is inverted after a predetermined comparator output delay time. As a result, the pixel data level Vsig is AD-converted as the count value Dsig with the gain a. This count value Dsig is the result of reading with the gain a in the OPB area.

  Further, in order to perform reading with the gain a and gain b in the OPB area, when reading is performed as shown in FIG. 11 to obtain the count value in the OPB area with gain a, A method of reading the pixel data level Vsig with the gain a while ignoring the inversion of the comparator output VCO is conceivable. FIG. 13 shows an example of this case.

  In the example of FIG. 13, by setting the pixel reset signal RST to active H at time t1, the readout pixel is reset and the pixel voltage Vx_0 becomes the pixel reset level Srst. At time t10, a reference signal Vslop of gain b is generated from the voltage of initial value SLP_ini_b of gain b. At time t12, since the reference signal Vslop matches the pixel voltage Vx_0, the comparator output VCO of the voltage comparison unit 252 is inverted and the countdown operation is stopped. Thereby, the count value Drst_b is obtained.

  At time t14, the pixel transfer signal TRG is set to active H, and the pixel voltage Vx_0 changes from the pixel reset level Srst to the pixel data level Vsig.

  Further, at time t20, a reference signal Vslop of gain b is generated from the voltage of initial value SLP_ini_b of gain b. At time t22, since the reference signal Vslop matches the pixel voltage Vx_0, the comparator output VCO of the voltage comparison unit 252 is inverted, and the count-up operation is stopped. Since the count-up starts from the pixel reset level Drst_b counted down by the gain b, the final count value Dsig is AD conversion of the differential voltage between the pixel reset level and the pixel data level at the gain b, that is, at the same gain. The value obtained by CDS.

  However, as will be described later, this count value is not used in this example. That is, at time t26, the counter reset signal CLO is set to active H to clear the count value to zero.

  Thereafter, the reference signal Vslop of gain a is generated from the voltage of the initial value SLP_ini_a of gain a at time t30. At time t32, since the reference signal Vslop matches the pixel voltage Vx_0, the comparator output VCO of the voltage comparison unit 252 is inverted and the count-up operation is stopped. Since the count-up is started from the reset level 0, the final count value Dsig becomes an AD conversion value of the pixel reset level at the gain a.

  FIG. 14 illustrates an example in which the pixel signal readout level at the gain b started from the time t20 is small and is within the readout region of the gain b in the same AD conversion operation as in FIG. In this case, the final AD conversion result is the CDS read result with the gain b.

  That is, at time t20, AD conversion processing of the pixel data level with the gain b is started. Even in this case, when the reference signal Vslop reaches the initial value SLP_ini_b of the gain b, the AD conversion control unit 20A uses the gain change instruction signal CHNG as the reference signal generation unit 27 when the reference signal Vslop reaches the initial value SLP_ini_b of the gain b. And a reference signal Vslop of gain b is generated from the voltage of the initial value SLP_ini_b.

  At time t22, since the reference signal Vslop matches the pixel voltage Vx_0, the comparator output VCO is inverted after a predetermined comparator output delay time, and the count is stopped. As a result, the pixel data level Vsig is AD converted with the gain b as the count value Dsig.

  Since the count-up starts from the pixel reset level Drst_b counted down by the gain b, the final count value Dsig is AD conversion of the differential voltage between the pixel reset level and the pixel data level at the gain b, that is, at the same gain. The value obtained by CDS. As a result, noise signal components such as fixed pattern noise and reset noise can be removed.

  Further, since the gain at the time of counting the count value Drst_b of the pixel reset level and the count value Dsig of the pixel data level is the gain b, the comparator output delay time is the same. Therefore, the comparator output delay time is canceled by the CDS processing. In addition, the influence of the slack of the slope immediately after the generation of the reference signal Vslop is canceled out by the CDS processing.

  Next, at time t24, the latch signal VCOHL is set to active H, and the comparator output VCO of the voltage comparison unit 252 is held in the latch unit 501. Since the comparator output VCO of the voltage comparison unit 252 is inverted, the output Vrst of the latch unit 501 is also inverted.

  As a result, the counter clear signal CLO and the counter clock signal are gated. Therefore, at time t26, the counter clear signal CLO is set to active H but invalidated, and the CDS result Dsig of gain b is held as the count value.

  Further, since the count clock is also gated, the count operation for AD conversion reading with the gain a from time t30 to time t32 is also stopped, and the count value is held.

  As a result, the AD conversion count value Dsig held at time t22 becomes the final CDS read value. Regarding the readout with the gain b, the readout time of the pixel reset signal and the readout time of the pixel data signal are adjacent to each other, and a noise removal effect can be expected by the cutoff frequency characteristic of the CDS.

  In addition, the gain at the time of counting the pixel reset level Drst_b and the count at the time of counting the count value Dsig of the pixel data level is the gain b, so the comparator output delay time is the same. Therefore, the comparator output delay time is canceled by the CDS processing. In addition, the influence of the slack of the slope immediately after the generation of the reference signal Vslop is canceled out by the CDS processing.

  As in the case of FIG. 11, the latch data of the comparator output VCO of the voltage comparison unit 252 is horizontally transferred. However, in this example, since the latch data of the comparator output VCO is not inverted, the subtraction process for OPB data is not performed.

  In the case of the example of FIGS. 11 and 14, the count execution unit 503 has the configuration shown in FIG. 10 (that is, the configuration without the latch unit 513).

  The method shown in FIGS. 11 and 14 reads out the horizontal OPB pixel at low gain instead of reading out the low gain pixel reset level, and subtracts the result from the low gain pixel data level count value of each column to calculate the CDS. It is a method to perform. For this reason, since it is not necessary to read out a low gain pixel reset level every 1H, the total readout time for reading all the pixels can be shortened. However, a line buffer for storing the horizontal OPB readout result in the low gain readout is required in the subsequent stage. Further, it is necessary to read out the horizontal OPB area by changing the gain for each frame and store it in the line buffer.

  Also, due to the difference from the horizontal OPB, the Vth variation component of the pixel (that is, the random variation component of the transistor) and the kTC noise component cannot be canceled by CDS, but the data is used from the region where the signal level is relatively high, so that the image quality is high. It doesn't stand out.

  FIG. 15 is a timing chart for explaining a case where reading with different gains is performed three times. First, P-phase readout is performed with gains a, b, and c, and then D-phase readout is performed with gains c, b, and a.

  Of the readings with gains a, b, and c, which gain data is used is determined by the presence or absence of inversion of the D-phase voltage comparison unit 252. In other words, if it is determined whether to use the immediately preceding D-phase result (results of CDS), or to clear the count value and count the next gain reading, it is possible to obtain two or more gains. Reading is possible. The same applies to other reading methods.

  In the example of FIG. 15, the count execution unit 503 has the configuration shown in FIG. 4 (that is, the configuration having the latch unit 513).

  The method of FIG. 15 is a method of reading with three types of gains. Similarly, it is possible to read with a plurality of gains of 4 or more by increasing the number of readouts having different gains. As a result, optimization of the quantization step further proceeds, and effects such as color reproduction can be improved.

<Imaging device>

  FIG. 16 is a diagram illustrating a schematic configuration of an imaging apparatus which is an example of a physical information acquisition apparatus using a mechanism similar to that of the solid-state imaging apparatus 1 described above. The imaging device 8 is an imaging device that obtains a visible light color image.

  The mechanism of the solid-state imaging device 1 described above can be applied not only to the solid-state imaging device but also to the imaging device. In this case, the imaging apparatus also changes the slope of the reference signal Vslop in accordance with the magnitude of the signal component Vsig, and changes the frequency dividing operation of the counter in accordance with the change in the slope of the reference signal Vslop (with higher speed). Go). Further, when changing the frequency dividing operation, it is possible to adopt a mechanism in which the lower bit output is sequentially invalidated and only the frequency dividing operation of the remaining upper bit output is changed. As a result, AD conversion can be realized at high speed without requiring correction for the AD conversion result accompanying the change in the inclination of the reference signal Vslop and without impairing the substantial conversion accuracy.

  At this time, the control of the slope change point and the slope magnitude of the reference signal Vslop and the control for increasing the frequency dividing speed of the counter for canceling the slope change can be arbitrarily designated by the external main control unit. To do. That is, it is possible to arbitrarily designate a mode switching instruction according to the purpose of obtaining higher accuracy or higher speed based on the relationship between light shot noise and quantization noise by data setting for the communication / timing control unit 20. To.

  Specifically, the imaging device 8 includes a photographing lens 802 for guiding light L carrying an image of the subject Z under the illumination device 801 such as a fluorescent lamp to the imaging device side, and an optical low-pass filter. 804. Further, for example, a color filter group 812 in which R, G, and B color filters are arranged in a Bayer array, a pixel array unit 10, and a drive control unit 7 that drives the pixel array unit 10 are provided. Further, the column processing unit 26 that performs CDS processing, AD conversion processing, and the like on the pixel signal output from the pixel array unit 10, and the reference signal generation unit 27 that supplies the reference signal Vslop to the column processing unit 26 are horizontally transferred. A correction unit 301 that corrects the counted value to a gain, or subtracts optical black level data from the pixel data level count value, and a camera signal processing unit that processes the imaging signal output from the column processing unit 26 810.

  The optical low-pass filter 804 is for blocking high frequency components higher than the Nyquist frequency in order to prevent aliasing distortion. Further, as indicated by a dotted line in the drawing, an infrared light cut filter 805 that reduces the infrared light component can be provided in combination with the optical low-pass filter 804. This is the same as a general imaging device.

  The camera signal processing unit 810 provided at the subsequent stage of the column processing unit 26 includes an imaging signal processing unit 820 and a camera control unit 900 that functions as a main control unit that controls the entire imaging apparatus 8.

  The imaging signal processing unit 820 outputs digital imaging signals supplied from the AD conversion function unit of the column processing unit 26 when a color filter other than the primary color filter is used as R (red), G (green), B A signal separation unit 822 having a primary color separation function for separating into (blue) primary color signals is included. The color signal processing unit 830 performs signal processing on the color signal C based on the primary color signals R, G, and B separated by the signal separation unit 822.

  The imaging signal processing unit 820 also converts the luminance signal Y / color signal C into a luminance signal processing unit 840 that performs signal processing on the luminance signal Y based on the primary color signals R, G, and B separated by the signal separation unit 822. And an encoder unit 860 that generates a video signal VD based on the encoder 860.

  Although not shown, the color signal processing unit 830 includes, for example, a white balance amplifier, a gamma correction unit, a color difference matrix unit, and the like. The white balance amplifier adjusts the gain of the primary color signal supplied from the primary color separation function unit of the signal separation unit 822 (white balance adjustment) based on the gain signal supplied from a white balance controller (not shown), and the gamma correction unit and brightness The signal is supplied to the signal processing unit 840.

  The gamma correction unit performs gamma (γ) correction for faithful color reproduction based on the primary color signal whose white balance is adjusted, and outputs the output signals R, G, and B for each color subjected to gamma correction as a color difference matrix unit To enter. The color difference matrix unit inputs the color difference signals RY and BY obtained by performing the color difference matrix processing to the encoder unit 860.

  Although not shown, the luminance signal processing unit 840 generates, for example, a high frequency signal that generates a luminance signal YH including a component having a relatively high frequency based on the primary color signal supplied from the primary color separation function unit of the signal separation unit 822. A luminance signal generation unit is included. In addition, a low frequency luminance signal generation unit that generates a luminance signal YL including only a component having a relatively low frequency based on a primary color signal adjusted in white balance supplied from a white balance amplifier, and two types of luminance signals YH, A luminance signal generation unit that generates a luminance signal Y based on YL and supplies the luminance signal Y to the encoder unit 860.

  The encoder unit 860 digitally modulates the color difference signals RY and BY with a digital signal corresponding to the color signal subcarrier, and then synthesizes the digital image with the luminance signal Y generated by the luminance signal processing unit 840. The signal is converted into a signal VD (= Y + S + C; S is a synchronization signal, and C is a chroma signal).

  The digital video signal VD output from the encoder unit 860 is further supplied to a camera signal output unit not shown in the subsequent stage, and is used for monitor output, data recording on a recording medium, and the like. At this time, the digital video signal VD is converted into the analog video signal V by DA conversion as necessary.

  The camera control unit 900 according to the present embodiment is a microprocessor (microprocessor) that forms the center of an electronic computer whose representative example is a CPU (Central Processing Unit) in which functions of computation and control performed by a computer are integrated into an ultra-small integrated circuit. ) 902. Also, a ROM (ReAD Only Memory) 904 that is a read-only storage unit, a RAM (Random Access Memory) 906 that is an example of a volatile storage unit that can be written and read at any time, and other peripheral members that are not shown have. The microprocessor 902, the ROM 904, and the RAM 906 are collectively referred to as a microcomputer.

  In the above description, the “volatile storage unit” means a storage unit in which the stored contents are lost when the power of the apparatus is turned off. On the other hand, the “nonvolatile storage unit” means a storage unit in a form that keeps stored contents even when the main power supply of the apparatus is turned off. Any memory device can be used as long as it can retain the stored contents. The semiconductor memory device itself is not limited to a nonvolatile memory device, and a backup power supply is provided to make a volatile memory device “nonvolatile”. You may comprise as follows.

  Further, the present invention is not limited to a semiconductor memory element, and may be configured using a medium such as a magnetic disk or an optical disk. For example, a hard disk device can be used as a nonvolatile storage unit. In addition, it is possible to use as a nonvolatile storage unit by adopting a configuration for reading information from a recording medium such as a CD-ROM.

  The camera control unit 900 controls the entire system. In particular, in relation to the speeding up of the above-described AD conversion processing, the reference signal generation unit 27 controls the inclination change of the reference signal Vslop and the counter unit 254 divides the frequency. It has a function of adjusting the on / off timing of various control pulses for speed control.

  The ROM 904 stores a control program for the camera control unit 900. In this example, in particular, the camera control unit 900 stores a program for setting on / off timings of various control pulses.

  The RAM 906 stores data for the camera control unit 900 to perform various processes.

  The camera control unit 900 is configured so that a recording medium 924 such as a memory card can be inserted and removed, and can be connected to a communication network such as the Internet. For example, the camera control unit 900 includes a memory reading unit 907 and a communication I / F (interface) 908 in addition to the microprocessor 902, the ROM 904, and the RAM 906.

  The recording medium 924 includes, for example, program data for causing the microprocessor 902 to perform software processing, the convergence range of the photometric data DL based on the luminance system signal from the luminance signal processing unit 840, and exposure control processing (including electronic shutter control). Used for. Also, for registering data such as various set values such as the inclination change control of the reference signal Vslop in the reference signal generation unit 27 and the on / off timing of various control pulses for frequency division speed control in the counter unit 254. Used for

  The memory reading unit 907 stores (installs) the data read from the recording medium 924 in the RAM 906. The communication I / F 908 mediates transfer of communication data with a communication network such as the Internet.

  In addition, although such an imaging device 8 shows the drive control unit 7 and the column processing unit 26 in a module form separately from the pixel array unit 10, as described for the solid-state imaging device 1, Needless to say, the one-chip solid-state imaging device 1 integrally formed on the same semiconductor substrate as the pixel array unit 10 may be used.

  In addition to the pixel array unit 10, the drive control unit 7, the column processing unit 26, the reference signal generation unit 27, and the camera signal processing unit 810, the imaging device 8 includes a photographing lens 802, an optical low-pass filter 804, or infrared light. It is shown in a state including an optical system such as a cut filter 805. This aspect is suitable when a module-like form having an imaging function that is packaged as a whole is packaged.

  In the relationship with the module in the solid-state imaging device 1 described above, as illustrated, a pixel array unit 10 (imaging unit) and a pixel array such as a column processing unit 26 having an AD conversion function and a difference (CDS) processing function. The solid-state imaging device 1 is provided in the form of a module having an imaging function in a state where signal processing units closely related to the unit 10 side (excluding the camera signal processing unit following the column processing unit 26) are packaged together As a result, the entire imaging device 8 may be configured by providing a camera signal processing unit 810 as a remaining signal processing unit in the subsequent stage of the solid-state imaging device 1 provided in the form of the module.

  Alternatively, although not shown, the solid-state imaging device 1 is provided in the form of a module having an imaging function in a state where the pixel array unit 10 and the optical system such as the photographing lens 802 are packaged together. In addition to the solid-state imaging device 1 provided in the form of a module, a camera signal processing unit 810 may be provided in the module to constitute the entire imaging device 8.

  Further, as a module form in the solid-state imaging device 1, a camera signal processing unit 810 corresponding to the camera signal processing unit 200 may be included. In this case, the solid-state imaging device 1 and the imaging device 8 are practically the same. It can also be regarded as a thing.

  Such an imaging device 8 is provided as a portable device having, for example, a camera or an imaging function for performing “imaging”. Note that “imaging” includes not only capturing an image during normal camera shooting but also includes fingerprint detection in a broad sense.

  The imaging device 8 having such a configuration is configured to include all the functions of the solid-state imaging device 1 described above, and can be the same as the basic configuration and operation of the solid-state imaging device 1 described above. . Further, by adopting a mechanism for performing control in which the change in the slope of the reference signal Vslop and the change in the counter frequency division speed are linked, it is possible to substantially and without correcting the AD conversion result accompanying the change in the slope of the reference signal Vslop. AD conversion can be performed at high speed without impairing conversion accuracy.

  For example, a program that causes a computer to execute the above-described processing is distributed through a recording medium 924 such as a non-volatile semiconductor memory card such as a flash memory, an IC card, or a miniature card. Furthermore, the program may be downloaded and acquired or updated via a communication network such as the Internet from a server or the like.

  A semiconductor memory such as an IC card or a miniature card as an example of the recording medium 924 includes the solid-state imaging device 1 described in the above embodiment (particularly, a control in which a change in inclination of the reference signal Vslop and a change in counter frequency division speed are linked). Part or all of the functions in the AD conversion speed-up process). Therefore, a program and a storage medium storing the program can be provided. For example, the AD conversion speed-up processing program for performing control in conjunction with the change in the inclination of the reference signal Vslop and the change in the counter dividing speed, that is, the software installed in the RAM 906 or the like is the AD conversion described for the solid-state imaging device 1. As with the high-speed processing, the control pulse setting function for realizing high-speed AD conversion processing is provided as software.

  The software is executed by the microprocessor 902 after being read into the RAM 906. For example, the microprocessor 902 executes a control pulse setting process based on a program stored in the ROM 904 and the RAM 906, which are examples of recording media, to link the change in the slope of the reference signal Vslop with the change in the counter dividing speed. By performing the control, the function of speeding up the AD conversion process can be realized in software.

  As mentioned above, although this technique was demonstrated using embodiment, the technical scope of this technique is not limited to the range as described in the said embodiment. Various changes or improvements can be added to the above-described embodiment without departing from the gist of the technology, and embodiments to which such changes or improvements are added are also included in the technical scope of the present technology.

  The above embodiments do not limit the technology according to the claims (claims), and all the combinations of features described in the embodiments are essential to the technical solution. Is not limited. The above-described embodiments include technologies at various stages, and various technologies can be extracted by appropriately combining a plurality of disclosed constituent elements. Even if some constituent requirements are deleted from all the constituent requirements shown in the embodiment, as long as the effect is obtained, the configuration from which these constituent requirements are deleted can be extracted as a technique.

<Others>

  The present technology can be configured as follows.

(1)
A reference signal for converting the level of an analog pixel signal obtained from a pixel into digital data, the reference signal having a first gain and the reference signal having a second gain different from the first gain. A generation unit for generating a pixel reset level read time and a pixel data level read time;
A comparison unit that compares the level of the analog pixel signal with the reference signal;
Count processing is performed in parallel with the comparison processing in the comparison section, and the count value at the time when the comparison processing of the reference signal of the first gain or the reference signal of the second gain is completed is used as the digital data. A solid-state imaging device comprising: a count unit to acquire.
(2)
A holding unit for holding the comparison result of the comparison unit;
The solid-state imaging device according to (1), wherein the count unit selects a count value obtained earlier and a count value obtained later based on the held comparison result.
(3)
The generation unit outputs a first reference signal of the first gain from a first initial value and a second reference signal of the second gain from a second initial value at the time of reading the pixel reset level. When the pixel data level is generated and read, the third reference signal of the first gain from the first initial value and the fourth reference signal of the second gain from the second initial value are generated. The solid-state imaging device according to (1) or (2).
(4)
When the second reference signal is generated between the one reference signal of the first gain and the other reference signal of the first gain, the count unit is one of the reference signals of the first gain. The solid-state imaging device according to (1), (2), or (3), wherein the count value based on is held and used as an initial value of the count value when counting based on the other reference signal.
(5)
Of the first gain and the second gain, the count processing when the pixel reset level is read and the pixel data level is read by the larger reference signal is performed at adjacent timings. 4) The solid-state imaging device according to any one of
(6)
Based on the gain of the count value selected by the count unit, a correction unit that corrects a difference in digital value resolution depending on the magnitude of the reference signal of the first gain and the reference signal of the second gain The solid-state imaging device according to any one of (1) to (5).
(7)
The solid-state imaging device according to any one of (1) to (6), wherein the count unit performs the counting by multiplying by a ratio of the first gain and the second gain.
(8)
The generation unit omits generation of one of the reference signal of the first gain and the reference signal of the second gain at the time of reading out the pixel data level, and generates only the other,
The solid-state imaging device according to any one of (1) to (7), wherein optical black level data is subtracted from the count value based on the generated other reference signal.
(9)
A reference signal for converting the level of an analog pixel signal obtained from a pixel into digital data, the reference signal having a first gain and the reference signal having a second gain different from the first gain. A generation unit for generating a pixel reset level read time and a pixel data level read time;
A comparison unit that compares the level of the analog pixel signal with the reference signal;
Count processing is performed in parallel with the comparison processing in the comparison section, and the count value at the time when the comparison processing of the reference signal of the first gain or the reference signal of the second gain is completed is used as the digital data. An imaging device comprising: a count unit to acquire.
(10)
A reference signal for converting the level of an analog pixel signal obtained from a pixel into digital data, the reference signal having a first gain and the reference signal having a second gain different from the first gain. , Generated at pixel reset level readout and pixel data level readout,
Comparing the level of the analog pixel signal with the reference signal;
A counting process is performed in parallel with the comparison process, and a count value at the time when the comparison process of the reference signal of the first gain or the reference signal of the second gain is completed is acquired as the digital data. .

DESCRIPTION OF SYMBOLS 1 Solid-state imaging device, 3 unit pixel, 10 pixel array part, 12 horizontal scanning circuit, 14 vertical scanning circuit, 15 row control line, 18 horizontal signal line, 19 vertical signal line, 20 communication / timing control part, 24 reading current source Unit, 25 column AD circuit, 26 column processing unit, 27 reference signal generation unit, 27 ADA conversion circuit, 28 output circuit, 32 charge generation unit, 252 voltage comparison unit, 254 counter unit, 256 data storage unit, 501 latch unit, 502 Clock / clear control unit, 503 count execution unit, 511 flip-flop, 512 data holding unit, 513 latch unit, 514 count mode switching unit, 515 count clock switching unit

Claims (10)

A reference signal for converting the level of an analog pixel signal obtained from a pixel into digital data, the reference signal having a first gain and the reference signal having a second gain different from the first gain. A generation unit for generating a pixel reset level read time and a pixel data level read time;
A comparison unit that compares the level of the analog pixel signal with the reference signal;
Count processing is performed in parallel with the comparison processing in the comparison section, and the count value at the time when the comparison processing of the reference signal of the first gain or the reference signal of the second gain is completed is used as the digital data. A solid-state imaging device comprising: a count unit to acquire. A holding unit for holding the comparison result of the comparison unit;
The solid-state imaging device according to claim 1, wherein the count unit selects a count value obtained earlier and a count value obtained later based on the held comparison result. The generation unit outputs a first reference signal of the first gain from a first initial value and a second reference signal of the second gain from a second initial value at the time of reading the pixel reset level. When the pixel data level is generated and read, the third reference signal of the first gain from the first initial value and the fourth reference signal of the second gain from the second initial value are generated. The solid-state imaging device according to claim 2. When the second reference signal is generated between the one reference signal of the first gain and the other reference signal of the first gain, the count unit is one of the reference signals of the first gain. The solid-state imaging device according to claim 3, wherein the count value based on is held and used as an initial value of the count value when counting based on the other reference signal. 5. The count processing at the time of reading the pixel reset level and the reading of the pixel data level by the reference signal, which is the larger of the first gain and the second gain, is performed at adjacent timings. Solid-state imaging device. Based on the gain of the count value selected by the count unit, a correction unit that corrects a difference in digital value resolution depending on the magnitude of the reference signal of the first gain and the reference signal of the second gain The solid-state imaging device according to claim 5. The solid-state imaging device according to claim 5, wherein the counting unit performs the counting by multiplying by a ratio of the first gain and the second gain. The generation unit omits generation of one of the reference signal of the first gain and the reference signal of the second gain at the time of reading out the pixel data level, and generates only the other,
The solid-state imaging device according to claim 2, wherein optical black level data is subtracted from the count value based on the generated other reference signal. A reference signal for converting the level of an analog pixel signal obtained from a pixel into digital data, the reference signal having a first gain and the reference signal having a second gain different from the first gain. A generation unit for generating a pixel reset level read time and a pixel data level read time;
A comparison unit that compares the level of the analog pixel signal with the reference signal;
Count processing is performed in parallel with the comparison processing in the comparison section, and the count value at the time when the comparison processing of the reference signal of the first gain or the reference signal of the second gain is completed is used as the digital data. An imaging device comprising: a count unit to acquire. A reference signal for converting the level of an analog pixel signal obtained from a pixel into digital data, the reference signal having a first gain and the reference signal having a second gain different from the first gain. , Generated at pixel reset level readout and pixel data level readout,
Comparing the level of the analog pixel signal with the reference signal;
A counting process is performed in parallel with the comparison process, and a count value at the time when the comparison process of the reference signal of the first gain or the reference signal of the second gain is completed is acquired as the digital data. .

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