JP2010178197A - Method of driving solid-state imaging device, solid-state imaging device, and camera - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a method of driving a solid-state imaging device suppressing degradation of a dynamic range due to dark output, a solid-state imaging device, and a camera. <P>SOLUTION: The solid-state imaging device includes: an imaging region 10 formed by arranging a plurality of pixels 3 in a matrix-like form; a reference signal generation unit 27 for generating a reference signal RAMP; comparators 252 each used for comparing a pixel signal output from the pixel 3 with the reference signal RAMP generated by the reference signal generation unit 27; counters 254 for counting input clocks; memories 256 each used for holding the number of counts obtained by being counted from the start of counting until the comparator 252 detects coincidence of the pixel signal with the reference signal RAMP; and a timing control unit 20 for changing the counting start time of each counter 254 based on input data to shift the counting start time of the counter 254 with respect to the start time of change of the voltage value of the reference signal RAMP. <P>COPYRIGHT: (C)2010,JPO&INPIT

Description

  The present invention relates to a solid-state imaging device and a camera using the same, and more particularly to a MOS type solid-state imaging device and a camera using the same.

  In recent years, various signal readout methods for MOS solid-state imaging devices have been proposed.

In the prior art disclosed in Patent Document 1, a row of pixels in an imaging region is selected, and pixel signals generated by the selected pixels are paralleled to a plurality of vertical signal lines (also referred to as “column signal lines”). A column-parallel output type MOS solid-state imaging device is proposed. There has also been proposed a column AD type solid-state imaging device in which an AD conversion circuit is provided corresponding to each vertical signal line to convert a pixel signal from an analog format to a digital format inside the MOS type solid-state imaging device.
JP 2005-323331 A

  Incidentally, in the solid-state imaging device disclosed in Patent Document 1, a dark output component is included in the pixel signal output from the pixel, but the maximum value of the counter that performs AD conversion of the pixel signal is limited by the number of bits of the counter. Therefore, digital data obtained by AD conversion of the signal component actually obtained by photoelectric conversion at the pixel is reduced by the dark output component. As a result, the solid-state imaging device of Patent Document 1 has a problem that the dynamic range is reduced by dark output.

  Accordingly, an object of the present invention is to provide a solid-state imaging device driving method, a solid-state imaging device, and a camera that can suppress a decrease in dynamic range due to dark output.

  In order to achieve the above object, a driving method for a solid-state imaging device according to the present invention is a driving method for a solid-state imaging device including a pixel array in which a plurality of pixels are arranged in a matrix. Generating a reference signal that monotonously increases or decreases, comparing the pixel signal output from the pixel with the reference signal, counting a clock input to a counter, and starting the counting A step of holding a count number obtained by counting until a match between the pixel signal and the reference signal is detected, and changing the count start timing of the counter based on the input data, Shifting the count start time with respect to the start time of the change of the value of

  In addition, the present invention corresponds to a pixel array in which a plurality of pixels are arranged in a matrix, a reference signal generation unit that generates a reference signal whose value monotonously changes with time, and each column of the pixel array. A comparator that compares a pixel signal output from a pixel in a corresponding column and a reference signal generated by the reference signal generation unit, a counter that counts an input clock, and each of the pixel arrays A memory arranged corresponding to a column and holding a count number obtained by counting from the start of counting until the comparator of the corresponding column detects a match between the pixel signal and the reference signal; A counter control unit that changes a count start time of the counter based on data and shifts the count start time with respect to a start time of a change in the value of the reference signal. It can be a solid-state imaging device according to claim and. Here, the data includes a pixel signal readout mode, an ambient temperature of the solid-state imaging device, a rate of change of the value of the reference signal, an analog gain of an amplifier disposed in the pixel, or between the pixel and the comparator. It may be data relating to the analog gain of the amplifier disposed in the circuit.

  This delays the count start time of the counter based on the digital data of the pixel signal of the pixel where the light is blocked, thereby reducing the number of dark output components included in the pixel signal and lowering the dynamic range due to dark output Can be suppressed.

  Further, the data is data related to a level of digital data of the pixel signal output from the pixel, and the counter control unit performs the count start time according to the level of the digital data of the pixel signal output from the pixel. May be changed.

  Further, the data is data related to a level of digital data of a pixel signal that is shielded from light, and the counter control unit performs the count start time in accordance with the level of digital data of the pixel signal output from the pixel that is shielded from light. May be changed.

  The counter control unit may delay the count start timing as the level of the digital data of the pixel signal output from the pixel is higher.

  In addition, the counter control unit may detect the reference signal value change start time in the long exposure read mode, the pixel mixture mode, the ambient temperature is high, or the analog gain is high. The count start time may be delayed.

  The counter control unit may change the count start time for each frame to be captured.

  Further, the present invention may be a camera including the solid-state imaging device. Specifically, a signal processing unit that performs signal processing on video data, a memory that stores video data obtained as a result of signal processing, a control unit that determines gain, an optical lens, and the solid-state imaging device are provided. It can also be set as the camera characterized by this.

  The present invention can realize a driving method of a solid-state imaging device, a solid-state imaging device, and a camera that can suppress a decrease in dynamic range due to dark output.

The best mode for carrying out the present invention will be described below in detail with reference to the drawings.
FIG. 1 is a schematic configuration diagram of a solid-state imaging device 1 according to an embodiment of the present invention.

  As shown in FIG. 1, the solid-state imaging device (MOS image sensor or CMOS image sensor) 1 includes an imaging region (pixel array) 10 in which a plurality of pixels 3 are arranged in a matrix and a periphery of the imaging region 10. A column control unit 26 constituted by a drive control unit arranged, a plurality of column AD circuits 25 arranged corresponding to each column of the pixels 3 in the imaging region 10, and a DAC (Digital Analog Converter) 27a A reference signal generator 27 that generates a reference signal RAMP whose voltage value changes monotonously with the passage of time at a predetermined change rate, and an output circuit 28 are provided.

  The drive control unit includes a horizontal scanning circuit (column scanning circuit) 12, a vertical scanning circuit (row scanning circuit) 14, and a timing control unit 20. The timing control unit 20 is an example of the counter control unit of the present invention, generates various internal clocks based on the master clock CLK0 input via the terminal 5a, and generates the generated internal clocks in the solid-state imaging device 1. Supply to each circuit.

  Each pixel 3 is connected to a row control line 15 (V 1, V 2,... Vn) derived from the vertical scanning circuit 14 and a vertical signal line 19 that transmits a pixel signal to the column processing unit 26. The vertical scanning circuit 14 generates drive pulses (φR, φTX) based on the clock CN1 supplied from the timing control unit 20 and supplies the drive pulses (φR, φTX) to the pixels 3 via the row control lines 15. The horizontal scanning circuit 12 generates a drive pulse based on the clock CN2 supplied from the timing control unit 20.

  The column AD circuit 25 is a circuit that is arranged corresponding to each column of the imaging region 10 and converts an analog pixel signal into digital data. The column AD circuit 25 includes a reference signal RAMP generated by the reference signal generation unit 27, and pixel signals obtained from the pixels 3 in the corresponding column via the vertical signal lines 19 (H0, H1,... Hm). A comparator (voltage comparator) 252, a counter 254 that counts the clock CN5 input to the counter 254, and the comparator 252 in the corresponding column after the counter 254 starts counting the pixel signal and the reference signal A memory 256 that holds a count number obtained by counting until a match is detected, and a switch element 258 that switches between conduction and non-conduction between the counter 254 and the memory 256 based on the control data CN8. The digital data of the pixel signal held in the memory 256 is output to the outside of the solid-state imaging device 1 as video data D1 by the horizontal scanning circuit 12 via the output circuit 28.

  The solid-state imaging device 1 is mainly characterized by the timing control unit 20. Specifically, the duck clock CKdac input to the reference signal generation unit 27 and the counter clock CK0 input to the counter 254 of the column AD circuit 25 are characteristic. That is, the timing control unit 20 fixes the timing of the duck clock CKdac serving as a reference for the reference signal RAMP and changes the timing of the counter clock CK0 serving as a reference for the count start timing in the counter 254. On the other hand, in the timing control unit according to the prior art (Patent Document 1), the timings of the duck clock CKdac serving as the reference signal reference and the counter clock CK0 serving as the count start timing reference are fixed.

  The timing control unit 20 generates various internal clocks (duck clock CKdac, counter clock CK0, etc.) based on the master clock CLK0 input from the outside of the timing control unit 20 via the terminal 5a. Further, the timing control unit 20 sets the timing of the counter clock CK0 based on the data DATA input from the outside of the timing control unit 20 via the terminal 5b or the digital data DATA2 output from the output circuit 28.

  In addition to the solid-state imaging device 1, the camera according to the embodiment of the present invention determines a signal processing unit that performs signal processing on the video data D1, a memory that stores video data obtained as a result of the signal processing, and a gain. And an optical system (optical lens) that forms an image on the solid-state imaging device 1.

  Next, the operation of the solid-state imaging device 1 according to the embodiment of the present invention (the driving method of the solid-state imaging device 1), particularly the operation in a scene where the pixel signal is AD converted by the column AD circuit 25 will be described.

  2 and 3 are timing charts showing the operation of the solid-state imaging device 1 according to this embodiment. Specifically, the relationship between the counter clock CK0 input to the column AD circuit 25 and the output of the counter 254 is detailed. It is a timing chart shown in FIG. 2 shows a case where the dark output component count number ΔVleak is small, and FIG. 3 shows a case where the dark output component count number ΔVleak is large.

  First, the timing control unit 20 resets the count number of the counter 254 to the initial value “0”, and sets the counter 254 to the down-count mode. In addition, the timing control unit 20 causes the pixel 3 in any row Rx to read out a pixel signal having a reset component. Pixel signals appear on the vertical signal lines 19 (H1, H2,... Hm), respectively. The timing control unit 20 supplies the control data CN4 and the duck clock CKdac to the reference signal generation unit 27 (DAC 27a) when the pixel signal of the vertical signal line 19 becomes stable (time t10). In response to this, the reference signal generator 27 (DAC 27a) starts to change the reference signal RAMP over time. At the same time, the timing controller 20 starts to input the counter clock CK0 to the column AD circuit 25 (counter 254) (time t10). In response to this, the counter 254 starts down-counting from the initial value “0”. The duck clock CKdac and the counter clock CK0 are generally clocks obtained by multiplying the master clock CLK0 by the timing control unit 20.

  The reference signal RAMP changes with time, and coincides with the reset component at a certain time (time t12). At this time, the output signal of the comparator 252 is inverted, and in response to this, the counter 254 stops down-counting. The count number at this time corresponds to ΔV.

  When the down-count period elapses (time t14), the timing control unit 20 stops supplying the control data CN4 and the duck clock CKdac to the reference signal generation unit 27 (DAC 27a) and simultaneously inputs the counter clock CK0 to the counter 254. To stop.

  Subsequently, the timing control unit 20 sets the counter 254 to the up-count mode, and reads a pixel signal having a signal component (signal component obtained by actually performing photoelectric conversion) Vsig on the pixel 3 in an arbitrary row Rx. Let it come out. The reading method is the same as the reading of the reset component except that the counter 254 is set to the up-count mode.

  As described above, the counter 254 is set to a down count when the reset component is read out and an up count when the signal component Vsig is read out, so that the subtraction is automatically performed in the counter 254 and the count corresponding to the signal component Vsig is obtained. The number ΔVsig can be obtained.

  Here, the timing control unit 20 changes the timing of the counter clock CK0 to the duck clock CKdac based on the data DATA input from the outside of the timing control unit 20 via the terminal 5b or the digital data output from the output circuit 28. Change it. That is, the timing control unit 20 changes the count start time of the counter 254 based on the data input to the timing control unit 20, and the count start time of the counter 254 with respect to the start time of the change in the voltage value of the reference signal RAMP. Move. Thereby, the count number of the dark output component is reduced, and the decrease in the dynamic range due to the dark output component can be suppressed.

  Specifically, the timing control unit 20 can delay the count start timing by delaying the supply timing of the counter clock CK0 with respect to the supply timing of the duck clock CKdac. That is, the timing control unit 20 can delay the count start time by delaying the count start time of the counter 254 with respect to the start time of the change in the voltage value of the reference signal RAMP. The counter output can be expressed as ΔV + ΔVleak + ΔVsig−ΔVdelay, where ΔVdelay is the voltage change count of the reference signal RAMP that has changed from the time when the voltage value of the reference signal RAMP starts to change monotonously until the counter 254 starts counting. Although it is necessary to control to ΔVdelay ≦ ΔVleak, if it is controlled to ΔVdelay = ΔVleak, the counter output becomes ΔV + ΔVsig, and the reduction of the dynamic range due to the dark output component count number ΔVleak can be suppressed.

  For example, when the dark output component count number ΔVleak is small, the timing control unit 20 sets the count number ΔVsig to ΔVleak << ΔVsig. Accordingly, in this case, as shown in FIG. 2, the timing of the counter clock CK0 is set to be the same as that of the duck clock CKdac, and the start time of the change in the voltage value of the reference signal RAMP and the count start time of the counter 254 are set. It is the same. At this time, since ΔVdelay = 0 and ΔVleak << ΔVsig, the counter output can be expressed as ΔV + ΔVsig.

  On the other hand, when the count number ΔVleak of the dark output component is large, the count number ΔVleak of the dark output component is at a level that cannot be ignored with respect to the count number ΔVsig. Therefore, in this case, as shown in FIG. 3, the timing control unit 20 delays the timing of the counter clock CK0 with respect to the duck clock CKdac, and counters the start time of the change in the voltage value of the reference signal RAMP. The count start time of 254 is delayed. At this time, the counter output can be expressed as ΔV + ΔVleak + ΔVsig−ΔVdelay.

  Next, FIGS. 4 and 5 are top views for explaining a configuration for obtaining a pixel signal of the pixel 3 in a state where the light in the solid-state imaging device 1 is blocked.

  As shown in FIG. 4, the solid-state imaging device 1 includes an effective pixel region 31 that is open on the photodiode for photoelectric conversion, and a light-shielded pixel that is shielded from light by covering the photodiode with a metal wiring layer or the like. And an area. The light-shielding pixel region has a vertical OB (optical black) pixel region 32 above the effective pixel region 31 and a horizontal OB pixel region 33 on the left side of the effective pixel region 31. As shown in FIG. 5, the light-shielding pixel area includes a vertical OB (optical black) pixel area 32 below the effective pixel area 31 and a horizontal OB pixel area 33 on the right side of the effective pixel area 31. You may have.

  In such a solid-state imaging device 1, digital data of the light-shielded pixel 3 can be acquired by detecting the pixel signal of the pixel 3 in the vertical OB pixel region 32 or the horizontal OB pixel region 33. The dark output refers to a sensor output in a state where light is blocked, and a leak current of the pixel 3 is a main factor. Accordingly, the timing control unit 20 acquires the digital data of the pixel 3 that is shielded from light, changes the timing of the counter clock CK0 based on the digital data, and starts the count start timing of the counter 254 with respect to the start timing of the change in the voltage value of the reference signal RAMP. By determining the delay time and performing the delay, it is possible to accurately control ΔVdelay ≦ ΔVleak. That is, by obtaining the count number of ΔVleak from the pixel signal of the pixel 3 that is shielded from light, it is possible to control ΔVdelay ≦ ΔVleak.

  Further, there is no frame from the reading of the pixel signal from the vertical OB pixel region 32 to the reading of the pixel signal from the effective pixel region 31. When the ambient temperature of the solid-state imaging device 1, the exposure period of the solid-state imaging device 1, and the gain control are different between frames, the dark output is different between frames. Therefore, the timing control unit 20 delays the count start time using the digital data acquired from the pixel 3 in the vertical OB pixel region 32, and the timing control unit 20 changes the start time of the counter 254 in units of frames to be imaged. Thus, it is possible to control ΔVdelay ≦ ΔVleak with higher accuracy.

  In the solid-state imaging device 1 of the present embodiment, the maximum value of AD conversion by the column AD circuit 25 is determined by the number of bits of the counter 254 provided for each column of the pixels 3, and for example, a 12-bit counter 254 counts from 0 to 4095 LSB. can do. If the reset component count number is ΔV, the dark output component count number is ΔVleak, and the photoelectrically converted signal count number is ΔVsig, the counter output can be expressed as ΔV + ΔVleak + ΔVsig, but the maximum value of the counter 254 is the maximum value of the counter 254 Since it is limited by the number of bits, when ΔVleak increases, ΔVsig that can be AD-converted decreases. However, according to the solid-state imaging device 1 of the present embodiment, since ΔVleak can be reduced, it is possible to prevent ΔVsig from being reduced and the dynamic range from being lowered even when the dark output is increased.

  As described above, the solid-state imaging device and the camera of the present invention have been described based on the embodiment. However, the present invention is not limited to this embodiment. The present invention includes various modifications made by those skilled in the art without departing from the scope of the present invention.

  For example, the video data D1 of the light-shielded pixel area acquired by the camera system in which the solid-state imaging device 1 is mounted is reflected in the data DATA, and the data DATA reflecting the video data D1 is used for determining the count start time. Also good. Thereby, the supply timing of the counter clock CK0 can be directly controlled, and the circuit scale of the timing control unit 20 can be suppressed.

  In the above embodiment, the light-shielded pixel region is exemplified as a configuration for obtaining the digital data of the light-shielded pixel 3. However, the present invention is not limited to this. For example, a light-shielded state is created using a mechanical shutter function of a camera. Thus, digital data of the pixel 3 that is shielded from light may be acquired.

  Further, in the above embodiment, the timing control unit 20 changes the count start time of the counter 254 based on the digital data of the pixel 3 in the light-shielded pixel region, and with respect to the start time of the change in the voltage value of the reference signal RAMP. The count start time of the counter 254 is delayed. However, more simply, the digital data of the pixel 3 in the light-shielded pixel region is not used, the pixel signal readout mode, the ambient temperature of the solid-state imaging device 1, the exposure time of the solid-state imaging device 1, and the change rate of the reference signal RAMP (see Analog gain controlled by the monotonically increasing rate of the signal RAMP), the analog gain of the amplifier (not shown) arranged in the pixel 3, and the pixel 3 (vertical signal line 19) and the comparator 252. The timing of the counter clock CK0 is controlled according to the data related to the analog gain of the amplifier (not shown), the count start time of the counter 254 is changed, and the counter for the start time of the change in the voltage value of the reference signal RAMP The count start time of 254 may be delayed.

  The dark output refers to the sensor output in a state where light is blocked. Since the leak current of the pixel 3 is a main factor, the leak current increases especially when the temperature rises, and accumulates when the exposure time becomes long. The leakage charge increases and the effect becomes stronger. Further, when the analog gain before AD conversion is increased, the dark output component is gain-multiplied. In the pixel signal mixing mode in which pixel signals are mixed, the dark output component is also added, so that the influence is further increased. For this reason, in the case of the long exposure mode in which long exposure is performed, the pixel signal mixed mode, the ambient temperature of the solid-state imaging device 1 is high (when the temperature is high, such as 50 ° C. to 90 ° C.), or the analog gain Is high (when the analog gain is high, such as 2 to 16 times), it is possible to easily control ΔVdelay ≦ ΔVleak with high accuracy by delaying the count start timing of the counter 254. Even for elements that are difficult to detect with the solid-state imaging device 1 alone, such as detection of exposure time and ambient temperature, the camera system equipped with the solid-state imaging device 1 controls exposure time, ambient temperature, analog gain, and mode. By performing the above-described control and control in units of frames, it is possible to accurately control ΔVdelay ≦ ΔVleak. As a result, it is possible to suppress a decrease in dynamic range due to dark output at a high level.

  In the above embodiment, the counter output can be expressed as ΔV + ΔVleak + ΔVsig−ΔVdelay, but may be controlled to ΔVdelay ≦ ΔVleak + ΔV. If ΔVdelay = ΔVleak + ΔV is set, ΔV + ΔVleak + ΔVsig−ΔVdelay = ΔVsig, and the dynamic range can be further expanded as an AD output.

  Further, in the above embodiment, although there is a variation in the detection of the reset component, ΔV is determined uniformly by the solid-state imaging device 1, so ΔV may be a fixed value, or the downcount output of ΔV is It may be detected separately. The detection of the down count output can be detected by not performing the up count operation. In this case, for example, ΔV may be detected when the solid-state imaging device 1 is activated, or a period during which the up-counting operation is stopped is provided during a part of the vertical scanning, and ΔV may be detected during this period.

  In the above-described embodiment, the down-counting is performed when the reset component appears, and the up-counting is performed when the signal component appears. However, the down-counting may not be performed if it is not necessary to subtract the reset component. In this case, the counter 254 may not be an up / down counter configuration.

  In the above-described embodiment, the timing control unit 20 performs any driving mode such as a still image full image reading mode, a moving image pixel mixing mode, and a thinning mode based on data from the outside of the timing control unit 20. Also good.

  In the above embodiment, the reference signal generator 27 generates the reference signal RAMP whose voltage value monotonously decreases with time. However, the reference signal RAMP is not limited to this as long as the reference signal RAMP whose voltage value changes monotonously with the passage of time is generated. The reference signal generator 27 generates the reference signal RAMP whose voltage value monotonously increases with the passage of time. May be.

  The present invention can be used for a MOS type solid-state imaging device, and in particular, for a digital camera or the like.

1 is a schematic configuration diagram of a solid-state imaging device according to an embodiment of the present invention. It is a timing chart which shows operation of a solid imaging device concerning an embodiment of the present invention. It is a timing chart which shows operation of a solid imaging device concerning an embodiment of the present invention. It is a top view which shows the pixel structure of the solid-state imaging device which concerns on embodiment of this invention. It is a top view which shows the pixel structure of the solid-state imaging device which concerns on embodiment of this invention.

DESCRIPTION OF SYMBOLS 1 Solid-state imaging device 3 Pixel 5a, 5b Terminal 10 Imaging area 12 Horizontal scanning circuit 14 Vertical scanning circuit 15 Row control line 19 Vertical signal line 20 Timing control part 25 Column AD circuit 26 Column processing part 27 Reference signal generation part 27a DAC
28 Output Circuit 31 Effective Pixel Area 32 Vertical OB Pixel Area 33 Horizontal OB Pixel Area 252 Comparator 254 Counter 256 Memory 256 Switch Element

Claims (6)

A method for driving a solid-state imaging device including a pixel array formed by arranging a plurality of pixels in a matrix,
Generating a reference signal whose value monotonously increases or decreases over time;
Comparing the pixel signal output from the pixel with the reference signal;
Counting the clock input to the counter;
Holding a count number obtained by counting from the start of counting until the coincidence between the pixel signal and the reference signal is detected;
A method of driving a solid-state imaging device, comprising: changing a count start time of the counter based on input data, and shifting the count start time with respect to a start time of a change in the value of the reference signal. A pixel array in which a plurality of pixels are arranged in a matrix;
A reference signal generation unit that generates a reference signal whose value monotonously increases or decreases over time;
A comparator that is disposed corresponding to each column of the pixel array, and that compares a pixel signal output from a pixel in the corresponding column with a reference signal generated by the reference signal generation unit;
A counter that counts the input clock; and
A memory that is arranged corresponding to each column of the pixel array and holds a count number obtained by counting from the start of the count until the comparator of the corresponding column detects a match between the pixel signal and the reference signal When,
A solid-state imaging device comprising: a counter control unit that changes a count start time of the counter based on input data, and shifts the count start time with respect to a change start time of the value of the reference signal. The data includes a pixel signal of a light-shielded pixel, a pixel signal reading mode, an ambient temperature of the solid-state imaging device, a change rate of a value of the reference signal, an analog gain of an amplifier disposed in the pixel, or the pixel The solid-state imaging device according to claim 2, wherein the data is related to an analog gain of an amplifier disposed between the comparator and the comparator. The counter control unit is configured to detect a change timing of the reference signal value in a long exposure mode, a pixel signal mixture mode, a high ambient temperature, or a high analog gain. The solid-state imaging device according to claim 3, wherein the counting start time is delayed. The solid-state imaging device according to claim 2, wherein the counter control unit changes the count start time in units of frames to be imaged.   A camera provided with the solid-state imaging device according to claim 2.

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