JP2012175690A - Solid state imaging device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To accurately correct a dark current.SOLUTION: A solid state imaging device 1 comprises: effective pixels 11 which have photoelectric conversion parts for photoelectric conversion of incident light to capture an image; first elements 12 which have the same constitution as that of the effective pixels 11 and are shaded; second elements 13 which have a structure obtained by removing the photoelectric conversion parts from the same constitution as the effective pixels 11; a correction amount acquisition part 25 which obtains a correction amount according to the difference between the output signals of the first elements 12 and the output signals of the second elements 13; and AD conversion parts 7, 8, 9, and 21 which perform AD conversion of outputs from the effective pixels 11 such that converted output values are corrected according to the correction amount.

Description

  The present invention relates to a solid-state imaging device.

  Patent Document 1 below discloses a solid-state imaging device such as a CMOS image sensor including an AD conversion unit that performs AD conversion (analog-digital conversion) on a pixel signal.

  In such a solid-state imaging device, each pixel arranged in a matrix outputs a pixel signal corresponding to the charge accumulated in a photoelectric conversion unit such as a photodiode. However, some dark current is generated in the pixel regardless of light reception. Due to the generation of dark current, the black level increases and the dynamic range of the pixel data corresponding to the pixel signal becomes narrow, so it is necessary to correct the dark current.

  Therefore, in the solid-state imaging device disclosed in Patent Document 1, based on the difference between the reset value and the data value (black level offset difference) of the OB pixel (optical black pixel, light-shielded pixel for generating the black level). The amount of dark current correction is obtained. That is, in this solid-state imaging device, if there is no dark current, the black level offset difference is regarded as zero, and the black level offset difference is regarded as corresponding to the amount of dark current. Thus, the correction amount of the dark current is obtained. In this solid-state imaging device, the AD conversion unit AD converts the pixel signal so that the output value after conversion is corrected according to the correction amount.

JP 2010-154396 A

  However, in practice, the black level offset difference is not necessarily zero even if there is no dark current. Therefore, in the solid-state imaging device disclosed in Patent Document 1, if there is no dark current, the black level offset difference is considered to be zero, and the black level offset difference is considered to correspond to the amount of dark current. Therefore, it is not possible to obtain a correction amount that reflects the amount of dark current with high accuracy, and hence it is not possible to correct dark current with high accuracy.

  The present invention has been made in view of such circumstances, and an object of the present invention is to provide a solid-state imaging device capable of correcting dark current with high accuracy.

  The following aspects are presented as means for solving the problems. The solid-state imaging device according to the first aspect includes an effective pixel that has a photoelectric conversion unit that photoelectrically converts incident light and that captures an image, and a first element that has the same configuration as the effective pixel and is shielded from light. A correction amount corresponding to the difference between the second element having the same configuration as the effective pixel and the photoelectric conversion unit removed, and the difference between the output signal of the first element and the output signal of the second element. And an AD conversion unit that AD-converts the output from the effective pixel so that the converted output value is corrected according to the correction amount.

  In the solid-state imaging device according to the second aspect, in the first aspect, the AD conversion unit compares the reference signal that gradually changes from a predetermined level with the output signal of the effective pixel, and the reference signal. A counter that performs a counting operation until the output signal of the effective pixel matches, the counter being an optical signal including optical information obtained by photoelectrically converting the output signal of the effective pixel at the effective pixel. In some cases, the counting operation is performed from the time when the reference signal starts to change from the predetermined level and is delayed by the delay time corresponding to the correction amount.

  A solid-state imaging device according to a third aspect is the solid state imaging device according to the second aspect, wherein the counter is a down-count mode when the output signal of the effective pixel is a difference signal including a noise component to be subtracted from the optical signal. In one of the up-count modes, by performing a counting operation from the time when the reference signal starts changing from the predetermined level to the time when the reference signal and the output signal of the effective pixel match, The counter acquires a count value, and when the output signal of the effective pixel is the optical signal, the counter changes the reference signal from the predetermined level in the other one of the down-count mode and the up-count mode. The reference signal and the output signal of the effective pixel from a time point delayed by a delay time corresponding to the correction amount from the start time point To the point but consistent, it performs a counting operation from the count value.

  A solid-state imaging device according to a fourth aspect includes any one of the first to third aspects, and includes a plurality of the first elements and the second elements, and the correction amount acquisition unit includes the correction amount as the correction amount. A correction amount corresponding to a difference between an average value of output signals of the plurality of first elements and an average value of output signals of the plurality of second elements is obtained.

  The solid-state imaging device according to a fifth aspect is the solid-state imaging device according to any one of the first to third aspects, wherein the correction amount acquisition unit uses the output signal of the first element and the output of the second element as the correction amount. In addition to the difference from the signal, an amount corresponding to the length of the period from the end of the exposure period of the effective pixel to the time of reading the output signal of the effective pixel is obtained.

  The solid-state imaging device according to a sixth aspect includes the first element and the second element in any one of the first to third aspects, and the correction amount acquisition unit includes the correction amount as the correction amount. , Depending on the difference between the average value of the output signals of the plurality of first elements and the average value of the output signals of the plurality of second elements, and the output signal of the effective pixels from the end of the exposure period of the effective pixels An amount corresponding to the length of the period until the reading time is obtained.

  ADVANTAGE OF THE INVENTION According to this invention, the solid-state image sensor which can correct | amend a dark current with high precision can be provided.

1 is a schematic configuration diagram illustrating a solid-state imaging device according to a first embodiment of the present invention. It is a circuit diagram which shows one effective pixel in FIG. It is a block diagram which shows the correction amount acquisition part in FIG. It is a timing chart which shows an example of operation | movement of the solid-state image sensor by the 1st Embodiment of this invention. 6 is a timing chart showing an operation during a predetermined period in FIG. 4. It is a block diagram which shows the correction amount acquisition part of the solid-state image sensor by the 2nd Embodiment of this invention.

  Hereinafter, a solid-state imaging device according to the present invention will be described with reference to the drawings.

[First Embodiment]
FIG. 1 is a schematic configuration diagram showing a solid-state imaging device 1 according to the first embodiment of the present invention. The solid-state imaging device 1 according to the present embodiment is configured as a CMOS image sensor.

  As shown in FIG. 1, a solid-state imaging device 1 according to the present embodiment is provided corresponding to a pixel array unit 2 composed of a plurality of pixels arranged two-dimensionally and corresponding to each column of these pixels. A vertical signal line 3 to which an output signal of a pixel in a column is supplied, a constant current source 4 provided in each vertical signal line 3, a vertical scanning circuit 5, and a column circuit 6 provided in each vertical signal line 3. , A reference signal generation unit 9, a timing control unit 21, a horizontal scanning circuit 22, an m-bit horizontal signal line 23, an output circuit 24, and a correction amount acquisition unit 25.

  In the present embodiment, the pixels 11 in the third and subsequent rows among the pixels of the pixel array unit 2 have a photoelectric conversion unit (photodiode PD described later in this embodiment) that photoelectrically converts incident light, and an image is displayed. It is an effective pixel for imaging, and the area after the third row of the pixel array unit 2 is an effective pixel area.

  Among the pixels of the pixel array unit 2, the pixels 12 in the second row are optical black pixels (OB pixels) that generate a black level signal, and the second row of the pixel array unit 2 is an OB pixel region. Yes. In the present embodiment, the OB pixel 12 is the first element that has the same configuration as the effective pixel 11 and is shielded from light.

  Of the pixels in the pixel array unit 2, the pixels 13 in the first row are second elements having a configuration in which the photoelectric conversion unit is removed from the same configuration as the effective pixels 11. For convenience of explanation, the pixel 13 is referred to as a dummy pixel, and a region in the first row where the pixel 13 is disposed in the pixel array unit 2 is referred to as a dummy pixel region. The dummy pixels 13 are not necessarily shielded from light, but are preferably shielded from light.

  Note that the arrangement, the number of rows, the number of columns, and the like of the effective pixel region, the OB pixel region, and the dummy pixel region in the pixel array unit 2 are not limited to the above-described example.

  FIG. 2 is a circuit diagram showing one effective pixel 11 in FIG. Each effective pixel 11 includes a photodiode PD as a photoelectric conversion unit that generates and accumulates charges according to incident light, and a floating capacitance unit FD that receives the charges and converts them into a potential, as in a general CMOS image sensor. A transfer transistor TX serving as a transfer unit that transfers charges from the photodiode PD to the floating capacitor unit FD, a reset transistor RST that resets the potential of the floating capacitor unit FD, and a signal corresponding to the potential of the floating capacitor unit FD. And an amplifying transistor AMP as an amplifying unit, and a selection transistor SEL as a selecting unit for selecting the pixel. In the present embodiment, the transistors AMP, TX, RST, and SEL are all nMOS transistors. In FIG. 2, Vdd is a power supply potential.

  The gate of the transfer transistor TX is commonly connected to the control line 30 for each row, and a control signal φTX for controlling the transfer transistor TX is supplied from the vertical scanning circuit 5 thereto. The gate of the reset transistor RST is commonly connected to the control line 31 for each row, and a control signal φRST for controlling the reset transistor RST is supplied from the vertical scanning circuit 5 to the reset line. The gates of the selection transistors SEL are commonly connected to the control line 32 for each row, and a control signal φSEL for controlling the selection transistors SEL is supplied from the vertical scanning circuit 5 thereto. The source of the selection transistor SEL of the effective pixel 11 is commonly connected to the vertical signal line 3 for each column. The control lines 30, 31 and 32 are connected to the vertical scanning circuit 5. In FIG. 2, reference numeral 33 denotes a power supply line for supplying a power supply potential Vdd. Since the constant current source 4 is connected to the vertical signal line 3, the amplification transistor AMP operates as a source follower circuit.

  Although not shown in the drawing, the circuit configuration of the OB pixel 12 and the connection relationship of the OB pixel 12 to the vertical scanning circuit 5 and the vertical signal line 3 are the same as those of the effective pixel 11 described above. Although not shown in the drawings, the circuit configuration of the dummy pixel 13 and the connection relationship of the dummy pixel 13 with respect to the vertical scanning circuit 5 and the vertical signal line 3 are the above-described effective pixels 11 except that there is no photodiode PD. Is the same as

  The vertical scanning circuit 5 outputs the control signals φSEL, φRST, and φTX for each row of the pixels 11, 12, and 13 in accordance with the control signal CON1 from the timing control unit 21, respectively. Control. By this control, output signals (analog signals) from the pixels 11, 12, and 13 in the corresponding columns are supplied to each vertical signal line 3. In FIG. 2, (n) attached to the control signal indicates that the control signal is a signal in the nth row.

  The timing controller 21 is based on a master clock (not shown) having a predetermined frequency, such as the control signal CON1, control signals CON2 to CON5 and clocks CK0 and CK1, which will be described later, and clock signals and timings necessary for the operation of each part of the circuit. Signals are generated, and these signals are supplied to the corresponding parts of the circuit.

  Each column circuit 6 includes a comparator 7 as a comparison unit that compares the signal of the corresponding vertical signal line 3 and the reference signal Vref from the reference signal generation unit 9, and a counter 8. In the present embodiment, the output signal of the comparator 7 becomes high when the level of the reference signal Vref is higher than the signal (pixel output signal) of the vertical signal line 3, while the level of the reference signal Vref is vertical signal line. When it is lower than the signal 3 (pixel output signal), it is at a low level. Note that an amplifier or the like may be provided between the vertical signal line 3 and the comparator 7 as necessary.

  In the present embodiment, an up / down counter is used as the counter 8. A control signal CON4 for instructing whether the counter 8 operates in the down-count mode or the up-count mode is input to the counter 8 from the timing control unit 21. The counter 8 also receives a count clock CK 1 from the timing control unit 21. The control signal CON4 and the count clock CK1 are respectively input to the counter 8 of each column circuit 6 in common. Further, the output signal of the corresponding comparator 7 is also input to the counter 8. The counter 8 counts the count clock CK1 in the mode indicated by the control signal CON4 until the signal (pixel output signal) of the corresponding vertical signal line 3 matches the reference signal Vref. As a result, the signal (pixel output signal) of the vertical signal line 3 is subjected to CDS processing (correlated double sampling processing) and AD conversion processing. This point will be described in detail later with reference to FIG.

  The reference signal generation unit 9 includes a DAC (digital-analog converter) 9a and a counter (not shown), and is referred from the initial value indicated by the control signal CON3 from the timing control unit 21 from the timing control unit 21. The signal generation clock CK0 is counted and the count value is DA converted. As a result, the reference signal generation unit 9 uses a stepped sawtooth wave (ramp waveform) as a reference signal that gradually changes from a predetermined level in synchronization with the reference signal generation clock CK0 from the initial value indicated by the control signal CON3. Is supplied to the comparator 7 of each column circuit 6 as the generated reference signal Vref.

  The horizontal scanning circuit 22 performs horizontal scanning according to the control signal CON2 from the timing control unit 21, and sequentially outputs the converted digital signal obtained by the counter 8 of each column circuit 6 to the m-bit horizontal signal line 23. Let The output circuit 24 converts the digital signal output to the vertical signal line 3 into a signal of a predetermined signal format, and outputs it as image data to the outside.

  The correction amount acquisition unit 25 obtains a correction amount according to the difference between the output signal of the OB pixel 12 and the output signal of the dummy pixel 13 in accordance with the control signal CON5 from the timing control unit 21. In the present embodiment, the AD conversion unit that AD converts the output from the effective pixel 11 so that the output value after conversion is corrected according to the correction amount, the control signals CON3, CON4 and the clocks CK0, CK1. The function of the timing control unit 21 to be supplied, the column circuit 6 and the reference signal generation unit 9 are configured.

  FIG. 3 is a block diagram showing the correction amount acquisition unit 25 in FIG. In the present embodiment, the correction amount acquisition unit 25 includes an OB pixel output holding unit 41 that holds each output value related to each OB pixel 12 output to the horizontal signal line 23, and each dummy output to the horizontal signal line 23. A dummy pixel output holding unit 42 that holds each output value related to the pixel 13, an average value calculation unit 43 that calculates an average value of output values held in the OB pixel output holding unit 41, and a dummy pixel output holding unit 42 An average value calculating unit 44 for calculating an average value of the output values, and a difference calculating unit for calculating a difference value between the average value calculated by the average value calculating unit 43 and the average value calculated by the average value calculating unit 44 45. In the present embodiment, the correction amount acquisition unit 25 supplies the difference value calculated by the difference calculation unit 45 to the timing control unit 21 as a correction amount. The values held in the OB pixel output holding unit 41 and the values held in the dummy pixel output holding unit 42 will be described later.

  FIG. 4 is a timing chart showing an example of the operation of the solid-state imaging device 1 according to the present embodiment. When the operation is started, after a mechanical shutter (not shown) is opened for a predetermined period (exposure period) T0, the first row readout period, the second row readout period,..., The nth row readout period, .. Are performed, and the reading operation is sequentially repeated one by one from the first line to the last line. The readout period of each row includes a vertical transfer period (including an AD conversion period) of the row and a horizontal transfer period (horizontal scanning period) of the row subsequent thereto. In FIG. 4, T1 indicates the vertical transfer period of the read period of the first row, T2 indicates the vertical transfer period of the read period of the second row, and Tn indicates the vertical transfer period of the read period of the nth row. As shown in FIG. 4, in the vertical transfer period of the readout period of each row, the control signal φSEL of that row is set to the high level, and the selection transistor SEL of the pixel of that row is turned on.

  FIG. 5 is a timing chart showing the operation in the vertical transfer period Tn of the readout period of the nth row in FIG. The pixels in the nth row are effective pixels 11. 5A to 5C show the control signals φSEL (n), φRES (n), and φTX (n) of the nth row supplied from the vertical scanning circuit 5, respectively. FIG. 5D shows a pixel output signal (signal of the vertical signal line 3) of the effective pixel 11 in the n-th row. FIG. 5E shows the reference signal Vref supplied from the reference signal generator 9 to the counter 8. FIG. 5F shows the reference signal generation clock CK 0 supplied from the timing control unit 21 to the reference signal generation unit 9. FIG. 5G shows the output signal of the comparator 7. FIG. 5H shows the case where the correction amount supplied from the correction amount acquisition unit 25 to the timing control unit 21 is zero and the delay time ΔT proportional to the correction amount is zero, and is supplied from the timing control unit 21 to the counter 8. The count clock CK1 is shown. FIG. 5I is a diagram showing the count value of the counter 8 when the correction amount is zero and the delay time ΔT is zero. FIG. 5 (h ′) shows the count clock CK1 supplied from the timing controller 21 to the counter 8 when the correction amount is a certain value and the delay time ΔT is a certain value b. FIG. 5 (i ′) is a diagram showing the count value of the counter 8 when the correction amount is a certain value and the delay time ΔT is the value b.

  In the vertical transfer period Tn, the control signal φSEL (n) in the nth row is set to the high level, and the selection transistor SEL of the effective pixel 11 in the nth row is turned on.

  The control signal φRST (n) in the n-th row is set to a high level for a predetermined period from the time t1 after the start of the vertical transfer period Tn, and the reset transistor RST of the effective pixel 11 in the n-th row is turned on. Thereby, as an output signal of the effective pixel 11, a signal corresponding to the reset component of the effective pixel 11 (here, a differential signal including a noise component to be subtracted from an optical signal including optical information photoelectrically converted by the effective pixel 11) Is output to the vertical signal line 3. Thereafter, in a period from time t2 to time t4 when the signal corresponding to the reset component is stabilized, the timing control unit 21 generates a clock having a predetermined frequency as the reference signal generation clock CK0. In accordance with the reference signal generation clock CK0, the reference signal Vref is constant over time from a predetermined level a at the time point t2 (a level corresponding to the initial value indicated by the control signal CON3 from the timing control unit 21) to the time point t4. Decrease with rate of change. As a result, at a certain time between time t2 and time t4 (time t3 in FIG. 5), the reference signal Vref and the pixel output signal match, and the output of the comparator 7 is changed from the high level to the low level at time t3. Invert to level. Although not shown in FIG. 5, during the period from time t2 to time t4, the operation mode of the counter 8 is set to the down-count mode by the control signal CON4 from the timing control unit 21. Note that by the time point t2, the timing control unit 21 resets the count value of the counter 8 to zero as an initial value.

  Regardless of the correction amount (that is, regardless of the delay time ΔT), as shown in FIG. 5 (h) and FIG. 5 (h ′), the timing control unit 21 is in the period from time t2 to time t4. The same clock as the reference signal generation clock CK0 is generated as the count clock CK1. Therefore, regardless of the correction amount, as shown in FIGS. 5 (i) and 5 (i ′), the counter 8 counts down the count clock CK1 from the initial value zero during the period from time t2 to time t3. The count value of the counter 8 after the time point t3 is a value −Vd obtained by AD-converting a signal corresponding to the reset component.

  At a predetermined time after time t4 and before time t6 described later, the reference signal Vref is returned to the predetermined level a, and the output of the comparator 7 is returned from the low level to the high level.

  The control signal φTX (n) in the nth row is set to the high level for a predetermined period from the time t5 after the time t4, and the transfer transistor TX of the effective pixel 11 in the nth row is turned on. As a result, a signal corresponding to the data component of the effective pixel 11 (here, an optical signal including optical information photoelectrically converted by the effective pixel 11) is output to the vertical signal line 3 as an output signal of the effective pixel 11. . Thereafter, in a period from time t6 to time t9 when the signal corresponding to the data component is stabilized, the timing control unit 21 generates a clock having a predetermined frequency as the reference signal generation clock CK0. In accordance with the reference signal generation clock CK0, the reference signal Vref decreases at a constant change rate over time from the predetermined level a at time t6 to time t9. As a result, at a certain time between time t6 and time t9 (time t8 in FIG. 5), the reference signal Vref and the pixel output signal match, and the output of the comparator 7 changes from the high level to the low level at time t8. Invert to level. Although not shown in FIG. 5, during the period from time t6 to time t9, the operation mode of the counter 8 is set to the up-count mode by the control signal CON4 from the timing control unit 21.

  When the correction amount supplied from the correction amount acquisition unit 25 to the timing control unit 21 is zero and the delay time ΔT proportional to the correction amount is zero, as shown in FIG. In the period from t6 (that is, the time delayed by the delay time ΔT = 0 from time t6) to time t9, the same clock as the reference signal generation clock CK0 is generated as the count clock CK1. Therefore, when the correction amount is zero, as shown in FIG. 5 (i), the count clock CK1 is only the value Vs obtained by AD-converting the optical signal from the value −Vd during the period from the time point t6 to the time point t8. The count value of the counter 8 counted up and after time t8 is a value Vs−Vd obtained by AD conversion of a signal corresponding to the data component minus a signal corresponding to the reset component. At a predetermined time after time t9 and before the end of the vertical transfer period Tn, the reference signal Vref is returned to the predetermined level a, and the output of the comparator 7 is returned from the low level to the high level.

  On the other hand, when the correction amount supplied from the correction amount acquisition unit 25 to the timing control unit 21 is a certain value and the delay time ΔT is a value b proportional to the correction amount, as shown in FIG. The control unit 21 counts the clock obtained by masking the reference signal generation clock CK0 for the period t6-t7 in the period from the time t7 (that is, the time delayed from the time t6 by the delay time ΔT = b) to the time t9. Occurs as CK1. Therefore, when the correction amount is a certain value and the delay time ΔT is a certain value b, as shown in FIG. 5 (i ′), the counter 8 counts the count clock CK1 during the period from the time point t7 to the time point t8. A value Vs ′ obtained by AD-converting the optical signal after correction from Vd (an optical signal reduced by an amount corresponding to the correction amount) is counted up, and the count value of the counter 8 after time t8 is the corrected data component A value obtained by subtracting a signal corresponding to the reset component from a signal corresponding to A / D converted value Vs′−Vd. At a predetermined time after time t9 and before the end of the vertical transfer period Tn, the reference signal Vref is returned to the predetermined level a, and the output of the comparator 7 is returned from the low level to the high level.

  As described above, the signal (pixel output signal) of the vertical signal line 3 is subjected to CDS processing (correlated double sampling processing) and AD conversion processing.

  In order to facilitate understanding, in the above description, when the correction amount is zero and the delay time ΔT is zero (FIGS. 5 (h) and (i)), the delay time ΔT with a certain value of the correction amount. In the case of a certain value b (FIG. 5 (h ′), (i ′)), the description is divided. However, in any case, there is no change in that the count clock CK1 is generated from the time point delayed by the delay time ΔT from the time point t6 and the up-count is started from the time point delayed by the delay time ΔT from the time point t6.

  As is clear from a comparison between FIGS. 5 (h) and (i) and FIGS. 5 (h ′) and (i ′), the count value of the processing result counter 8 is changed from the correction amount acquisition unit 25 to the timing control unit 21. Is corrected by a correction value ΔV = Vs−Vs ′ smaller than that when the correction amount is zero.

  When the vertical transfer period Tn of the n-th readout period ends, a horizontal transfer period of the n-th readout period follows. In this horizontal transfer period, the horizontal scanning circuit 22 performs horizontal scanning in accordance with the control signal CON2 from the timing control unit 21, and converts the converted digital signal (count value of the counter 8) obtained by the counter 8 of each column circuit 6. Are sequentially output to the m-bit horizontal signal line 23. The output circuit 24 converts the digital signal output to the vertical signal line 3 into a signal of a predetermined signal format, and outputs it as image data to the outside.

  The reading period of the nth row when the pixel of the nth row is the effective pixel 11 has been described above. The operation during the readout period of the other rows of the effective pixels 11 is the same as the operation during the readout period of the nth row.

  The operation of the row readout period of the dummy pixels 13 (the first row readout period in the present embodiment) and the operation of the row readout period of the OB pixels 12 (the second row readout period in the present embodiment) are also performed. , Operation in the readout period of the nth row is the same. However, in these readout periods, the timing control unit 21 always considers the delay time ΔT to be zero, performs the same operation as in FIGS. 5 (h) and (i), and performs the same operations as in FIGS. The same operation as i ′) is not performed.

  In the readout period of the row of the OB pixels 12, the count value corresponding to the count value Vs−Vd obtained at the time t <b> 9 in FIG. 5I is the OB pixel output of the correction amount acquisition unit 25 for each OB pixel 12. It is held by the holding unit 41. In the readout period of the row of dummy pixels 13, the count value corresponding to the count value Vs−Vd obtained at time t <b> 9 in FIG. 5I is the dummy pixel output of the correction amount acquisition unit 25 for each dummy pixel 13. It is held by the holding unit 42. The average value calculation unit 43 calculates the average value of the count values held in the OB pixel output holding unit 41. The average value calculation unit 44 calculates the average value of the count values held in the dummy pixel output holding unit 42. The difference calculation unit 45 calculates a difference value between the average value calculated by the average value calculation unit 43 and the average value calculated by the average value calculation unit 44. The correction amount acquisition unit 25 performs the above operation based on the control signal from the timing control unit 21, and supplies the difference value calculated by the difference calculation unit 45 to the timing control unit 21 as a correction amount. As described above, this correction amount is used to determine the delay time ΔT described above in the vertical transfer period of the readout period of the row of effective pixels 11.

  Since the correction amount obtained by the correction amount acquisition unit 25 in this way is in accordance with the difference between the output signal of the OB pixel 12 and the output signal of the dummy pixel 13, the dark current is reduced as in the conventional technique described above. Otherwise, the amount of dark current is reflected with higher accuracy than when the black level offset difference is regarded as zero and the black level offset difference is regarded as corresponding to the amount of dark current.

  In the present embodiment, as described above, the output value after conversion (the count value Vs ′ obtained at time t9 in FIG. 5 (i ′)) according to the correction amount obtained by the correction amount acquisition unit 25. (The count value corresponding to −Vd) is corrected, the dark current can be corrected with high accuracy.

[Second Embodiment]
FIG. 6 is a block diagram illustrating a correction amount acquisition unit of the solid-state imaging device according to the second embodiment of the present invention, and corresponds to FIG. 6, elements that are the same as or correspond to those in FIG. 3 are given the same reference numerals, and redundant descriptions thereof are omitted.

  The difference between the present embodiment and the first embodiment is that in this embodiment, the correction amount acquisition unit 25 uses the difference between the output signal of the OB pixel 12 and the output signal of the dummy pixel 13 as the correction amount. As well as the length of the period from the end of the exposure period T0 of the effective pixel 11 to the output signal reading time of the effective pixel 11 (referred to as “reading time” for convenience of explanation). It is only a point to get.

  Specifically, the present embodiment is different from the first embodiment in that a calculation unit 46 and an addition unit 47 are added in the correction amount acquisition unit 25, and the correction amount acquisition unit 25 outputs the output of the addition unit 47. It is only the point which outputs (addition value) as a correction amount.

  The calculation unit 46 receives a read row signal indicating which row is currently read from the timing control unit 21, converts the read row signal into a read time of the read row indicated by the read row signal, and sets the read time to a predetermined value. Is multiplied by a weighting coefficient (weighting coefficient for matching the difference value from the difference calculation unit 45 with the scale) α to obtain the multiplication value. The addition unit 47 adds the difference value from the difference calculation unit 45 and the multiplication value from the calculation unit 46. In the present embodiment, the correction amount acquisition unit 25 supplies the addition value obtained by the addition unit 47 to the timing control unit 21 as a correction amount. This correction amount is used to determine the delay time ΔT in the vertical transfer period of the reading period of the current row.

  As shown in FIG. 5 described above, after the exposure period T0, the reading operation is sequentially repeated row by row from the first row to the last row. For this reason, the readout time of the effective pixels 11 in each row varies from row to row. In the first embodiment and the present embodiment, the output signal reading time of the effective pixel 11 is a time corresponding to the time t5 in FIG.

  And the dark current accumulated in the photodiode PD of the effective pixel 11 increases as the readout period of the effective pixel 11 becomes longer. Therefore, as described above, since the readout time of the effective pixels 11 in each row differs from row to row, the amount of dark current accumulated in the photodiode PD of the effective pixels 11 in each row differs from row to row.

  For this reason, in the first embodiment, shading occurs due to a difference in the amount of dark current for each row.

  On the other hand, in the present embodiment, the correction amount acquisition unit 25 not only responds to the difference between the output signal of the OB pixel 12 and the output signal of the dummy pixel 13 as the correction amount, but also in the readout time of the effective pixel 11. Therefore, the influence of the variation in the dark current amount for each row can be reduced, and the shading can be reduced.

  Although the embodiments of the present invention have been described above, the present invention is not limited to these embodiments.

  For example, in each of the above embodiments, an up / down counter is used as the counter 8. In the present invention, a counter that performs only up-counting is used as the counter 8, and a count value corresponding to the Vd of the counter 8 is set. A latch circuit for holding and a latch circuit for holding a count value corresponding to the Vs ′ of the counter 8 may be provided, and a difference between values held in the respective latch circuits may be taken.

  Further, in each of the embodiments, the correction amount acquisition unit 25 takes the difference between the average value of the values of the plurality of OB pixels 12 and the average value of the values of the plurality of dummy pixels 13, but instead, A difference between the value of one OB pixel 12 and the value of one dummy pixel 13 may be taken.

  Further, in each of the embodiments, as described above, the correction based on the correction amount obtained by the correction amount acquisition unit 25 is realized by setting the delay time Δ corresponding to the correction amount. However, in the present invention, the correction based on the correction amount is not limited to this. For example, the initial level a at the time point t6 of the reference signal Vref is set according to the correction amount while the delay time Δ is always zero. It may be realized by changing.

DESCRIPTION OF SYMBOLS 1 Solid-state image sensor 2 Pixel array part 7 Comparator 8 Counter 9 Reference signal generation part 11 Effective pixel 12 OB pixel (1st element)
13 Dummy pixel (second element)
21 Timing control unit 25 Correction amount acquisition unit

Claims (6)

An effective pixel for capturing an image having a photoelectric conversion unit that photoelectrically converts incident light;
A light-shielded first element having the same configuration as the effective pixel;
A second element having a configuration in which the photoelectric conversion unit is removed from the same configuration as the effective pixels;
A correction amount acquisition unit for obtaining a correction amount according to the difference between the output signal of the first element and the output signal of the second element;
An AD converter that AD converts the output from the effective pixel so that the output value after conversion is corrected according to the correction amount;
A solid-state imaging device comprising: The AD conversion unit performs a counting operation until a comparison unit that compares a reference signal that gradually changes from a predetermined level with the output signal of the effective pixel, and a point in time when the reference signal and the output signal of the effective pixel match. A counter, and
When the output signal of the effective pixel is an optical signal including optical information photoelectrically converted by the effective pixel, the counter corresponds to the correction amount from the time when the reference signal starts changing from the predetermined level. The solid-state imaging device according to claim 1, wherein the counting operation is performed from a point of time delayed by a delay time. When the output signal of the effective pixel is a differential signal including a noise component to be subtracted from the optical signal, the counter is configured to select the predetermined signal in the down-count mode or the up-count mode. The count value is obtained by performing the counting operation from the time when the change starts from the level until the time when the reference signal and the output signal of the effective pixel match,
When the output signal of the effective pixel is the optical signal, the counter corrects the correction signal from the time when the reference signal starts changing from the predetermined level in the other one of the down-count mode and the up-count mode. From the time point delayed by a delay time according to the amount to the time point when the reference signal and the output signal of the effective pixel match, the count operation is performed from the count value.
The solid-state imaging device according to claim 2. A plurality of the first element and the second element, respectively,
The correction amount acquisition unit obtains, as the correction amount, a correction amount according to a difference between an average value of output signals of the plurality of first elements and an average value of output signals of the plurality of second elements. The solid-state image sensor according to any one of claims 1 to 3.   The correction amount acquisition unit responds to the difference between the output signal of the first element and the output signal of the second element as the correction amount and outputs the output signal of the effective pixel from the end of the exposure period of the effective pixel. The solid-state imaging device according to any one of claims 1 to 3, wherein an amount corresponding to a length of a period until reading is obtained. A plurality of the first element and the second element, respectively,
The correction amount acquisition unit responds to a difference between an average value of output signals of the plurality of first elements and an average value of output signals of the plurality of second elements as the correction amount, and 4. The solid-state imaging device according to claim 1, wherein an amount corresponding to a length of a period from an end of an exposure period to an output signal readout time of the effective pixel is obtained.

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