JP2013106225A - Imaging apparatus and imaging system - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide an imaging apparatus which reduces a sampling time difference between sampling timing for AD-converting a dummy pixel and sampling timing for AD-converting a valid pixel and can reduce horizontal streak noise.SOLUTION: An imaging apparatus includes: second analog-digital conversion means for analogue-to-digital-converting an analog signal outputted from a dummy pixel section for a plurality of times while first analog-digital conversion means performs analog-digital conversion; a plurality of recording means for recording a plurality of pieces of data obtained by the second analog-digital conversion means; selecting means for selecting one of the plurality of pieces of data recorded in the plurality of recording means in accordance with timing when a first analog-digital conversion is performed; and first arithmetic means for operating data obtained from the first analog-digital conversion means and data selected by the selecting means.

Description

  The present invention relates to an imaging apparatus used for a digital camera or the like, and more particularly to a column AD conversion type imaging apparatus having AD conversion means for each column of a pixel array unit.

  In recent years, some imaging devices such as digital cameras have a column parallel ADC type CMOS (Complementary Metal Oxide Semiconductor) image sensor in which an ADC (Analog-Digital Converter) is arranged for each column of the pixel array section. It has been reported. As an example, there is Patent Document 1. Hereinafter, a conventional imaging apparatus will be described with reference to FIG.

  FIG. 6 is a block diagram showing a configuration of a solid-state imaging device according to the prior art. In FIG. 6, 100 is a solid-state imaging device, 111 is a pixel array unit, 112 is a unit pixel including a photoelectric conversion device, 113 is a row selection signal line, 114 is a column signal line, 115 is a row scanning circuit, and 116 is a column AD conversion unit. 117 is a plurality of column-unit AD converters, 118 is a comparator, 119 is an up / down counter, 120 is a memory for holding data from the counter, 121 is a signal output line, 122 is an output circuit, and 123 is a column scanning circuit , 124 is a timing control circuit, and 125 is a DAC-type reference voltage supply circuit that generates a reference signal Vref having a ramp waveform, and outputs a Vref voltage in proportion to the count value of the counter.

  The operation of the conventional solid-state imaging device will be described with reference to the timing chart of FIG. Here, a driving example in the case of performing digital double sampling is shown. The first sampling uses the reference voltage Vn as a determination target, and corresponds to variations in unit pixels and offset variations in comparators for each column. The timing control circuit 124 instructs the down count mode to the up / down counter 119 group. A reference voltage Vn (corresponding to a reset component) generated in each pixel for each column is input to the comparator 118 for the unit pixel 112 group in the selected row by the row scanning circuit 115. The comparator 117 compares the ramp waveform reference voltage Vref from the DAC (Digital-Analog Converter) DAC type reference voltage supply circuit 125 with the pixel output Vpix. During this period, the up / down counter 119 continues to count the reference clock CLK. When the reference voltage Vref of the ramp waveform exceeds the reference voltage Vn, the comparator output Vcmp is inverted and becomes “L” level, and the count operation of the up / down counter 119 is stopped. Thereby, the up / down counter 119 obtains the reset component Dn as the counter output CNT by the down-counting. This reset component Dn corresponds to the reference voltage Vn. By taking the reset component Dn into account, the offset voltage variation between pixels when there is no signal is eliminated. The reset component Dn is temporarily held in the memory 120. After a predetermined time elapses, the reference voltage Vref is reset to 0 level, and the comparator output Vcmp is returned to “H” level.

  Further, when a predetermined time elapses, the second sampling is started. Similarly, the timing chart of FIG. The second sampling is up-counting for the luminance signal voltage Vs output from the pixel. The timing control circuit 124 instructs the up / down counter 119 group to enter the up count mode. Further, the luminance signal voltage Vs at each pixel for each column in the unit pixel 112 group of the selected row by the row scanning circuit 115 is input to the comparator 118. The comparator 118 compares the ramp waveform reference voltage Vref from the DAC-type reference voltage supply circuit 125 with the pixel output Vref. During this time, the up / down counter 119 continues to count up the reference clock CLK. The count value CNT by the up / down counter 119 has the reset component Dn obtained at the time of the down count as an initial value.

  When the reference voltage Vref of the ramp waveform exceeds the luminance signal voltage Vs, the comparator output Vcmp is inverted, and the count operation of the up / down counter 119 is stopped at the counter operation time Tc. Thereby, the up / down counter 119 obtains the count value CNT. The count value CNT is obtained by adding a reset component Dn by down-counting, and is Dn + Ds. Therefore, the digital pixel value Ds of the normal signal component corresponding to the luminance signal voltage Vs is obtained by taking the difference between the first sampling result Dn and the second sampling result Dn + Ds. The obtained digital pixel value Ds is temporarily held in the memory 120, thereby completing AD conversion for one pixel.

  The above-mentioned signal processing in units of columns is performed simultaneously for all the unit pixels 112 in the selected row in the pixel array unit 111 (FIG. 7 shows an operation in one horizontal period for one pixel). That is, the column-unit comparator 118 and the up / down counter 119 operate in the same manner as described above, and the digital pixel value Ds corresponding to the pixel output Vpix from all the unit pixels 112 in the selected row is held in the memory 120. become. Next, the column scanning circuit 123 performs column scanning on the AD converter 117 in units of columns, and sequentially outputs pixel data for one selected row through the signal output line 121 and the output circuit 122 to the outside.

  The pixel signal processing for one selected row as described above is executed for all selected rows by repeating sequential updating of the selected row by the row scanning circuit 115 to obtain digital image data for one field. It is done.

  However, fluctuations such as a power source connected to the pixel array unit 111 may be superimposed on the actual pixel output signal. When the fluctuation component having the characteristic shown in the power supply voltage VCC of FIG. 7 is superimposed on the pixel output, the power supply fluctuation voltage difference ΔVp is superimposed on the luminance signal voltage Vs. Here, in the conventional technique disclosed in Patent Document 1 described above, since the time difference ΔTs between the sampling time of Dn and the sampling time timing of Ds is large, it is easily affected by fluctuations in the power supply of low frequency. In the column parallel AD type CMOS, AD conversion is performed at the same time for each selected row. Therefore, noise such as power fluctuation affects the image as horizontal noise.

  As a countermeasure against this, as disclosed in Patent Document 2, there is a method in which a dummy pixel not connected to a photoelectric conversion element is provided in each row, and noise in each row is corrected. Hereinafter, a conventional imaging apparatus will be described with reference to FIG. In FIG. 8, the same parts as those in FIG.

  In FIG. 8, 126 is a dummy pixel array unit, 127 is a dummy pixel to which no photoelectric conversion element is connected, 128 is an AD converter that AD-converts data of the dummy pixel, 129 is a comparator that compares dummy pixel data, and 130 is A dummy pixel up / down counter 131 is a dummy pixel memory for holding data from the dummy pixel counter. Reference numeral 132 denotes a subtracter that subtracts data from an AD converter that AD converts a dummy pixel. The timing chart will be described with reference to FIG. The AD conversion of the effective pixel portion to which the photoelectric conversion element is connected is the same as that in FIG. 7, but at the same time, the AD conversion of the dummy pixel is also performed. Since the output from the dummy pixel is superimposed with noise components such as power fluctuations that do not depend on the photoelectric conversion element, the digital pixel value data Ds of the effective pixel and the digital pixel value data Ddummy of the dummy pixel are subtracted in FIG. By subtracting with a device, noise such as power fluctuations can be reduced.

JP 2005-278135 A JP-A-6-189200

  However, in the conventional technique disclosed in Patent Document 2 described above, when the luminance level of the effective pixel is high, the sampling time difference ΔTs2 between the sampling timing for AD conversion of the dummy pixel and the sampling timing for AD conversion of the effective pixel is the Patent Document Although it is improved compared to 1, it is not sufficiently small, and there is also a superimposed power supply fluctuation voltage difference ΔVp2, which is easily affected by low-frequency power fluctuations. For this reason, in the column parallel AD type CMOS, AD conversion is performed at the same time for each selected row. Therefore, noise such as power supply fluctuation affects the image as horizontal noise.

  SUMMARY OF THE INVENTION An object of the present invention is to provide an imaging apparatus that can reduce the horizontal noise by reducing the sampling time difference between sampling timing for AD conversion of dummy pixels and sampling timing for AD conversion of effective pixels. is there.

In order to achieve the above object, the present invention provides an effective pixel unit in which unit pixels including photoelectric conversion elements are two-dimensionally arranged in a matrix, a dummy pixel unit to which no photoelectric conversion elements are connected, and the effective pixel unit. And row scanning means for selecting and controlling each unit pixel of the dummy pixel portion for each row,
First analog-to-digital conversion means for converting an analog signal output from a unit pixel of an effective pixel portion selected and controlled by the row scanning means into a digital signal;
First recording means for recording data obtained from the first analog-digital conversion means;
Second analog-to-digital conversion means for performing analog-to-digital conversion of an analog signal output from the dummy pixel section a plurality of times during a period in which the first analog-to-digital conversion means performs analog-to-digital conversion;
A plurality of recording means for recording a plurality of data obtained by the second analog-digital conversion means;
Selection means for selecting one of a plurality of data recorded in the plurality of recording means according to the timing at which the first analog-digital conversion is performed;
It has a 1st calculating means which calculates the data obtained from the said 1st analog-digital conversion means, and the data selected by the said selection means, It is characterized by the above-mentioned.

  According to the present invention, it is possible to provide an imaging apparatus capable of reducing the sampling time difference between the sampling timing for AD conversion of the dummy pixels and the sampling timing for AD conversion of the effective pixels and reducing the horizontal noise.

The block diagram explaining the 1st Embodiment of this invention Timing chart for explaining the first embodiment of the present invention 1 is a circuit diagram illustrating a first embodiment of the present invention. The block diagram explaining the 2nd Embodiment of this invention The block diagram explaining the 3rd Embodiment of this invention Block diagram for explaining a conventional configuration Timing chart explaining conventional configuration Block diagram for explaining a conventional second embodiment Timing chart for explaining the conventional second embodiment

  Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings. FIG. 1 shows an imaging apparatus according to an embodiment of the present invention.

[Example 1]
Hereinafter, an image pickup apparatus according to a first embodiment of the present invention will be described with reference to FIG.

  In FIG. 1, the same parts as those in FIG. 133 is a DAC-type reference voltage supply circuit for dummy pixels, 134 is a multiplexer for branching data from the up / down counter for dummy pixels, and 135 is a first for holding data from the up / down counter for dummy pixels A dummy pixel memory 136 is a second dummy pixel memory 137 for holding data from the dummy pixel up / down counter, and 137 is a selector. This is a selector for selecting dummy pixel data used for the subtracter 132.

  The operation of this embodiment will be described with reference to the timing chart of FIG. Simultaneously with the AD conversion of the effective pixels, the AD conversion of the dummy pixels is performed as in the conventional case. Data obtained by first AD converting the dummy pixel output is branched by the multiplexer 134 in FIG. 1 and recorded in the memory 135. Thereafter, the DAC reference voltage supply circuit 133 for dummy pixels is once reset and starts a voltage sweep again. Thereby, the AD conversion of the dummy pixel is performed again. The data at this time is branched by the multiplexer 134 in FIG. 1 and recorded in the memory 136. After that, the selector 137 in the block diagram of FIG. 1 selects whether to use the data recorded in the memory 135 or the data recorded in the memory 136 as the data used for the subtraction process. When the effective pixel data has a low luminance level, subtraction processing is performed using the AD conversion data that was performed the first time, that is, data recorded in the memory 135, and when the effective pixel data has a high luminance level, Subtraction processing is performed using the converted AD conversion data, that is, data recorded in the memory 136.

  Thereby, even when the luminance signal level is high, the sampling timing for AD conversion of the dummy pixel signal can be made close, the sampling time difference ΔTs−3 can be reduced, and the power supply fluctuation voltage difference ΔVp3 is also small. In this way, by reducing the sampling time difference ΔTs−3, it is possible to make it less susceptible to the influence of low-frequency power supply fluctuations, and horizontal pulling noise due to noise such as power supply fluctuations is reduced.

  FIG. 3 shows the configuration of a DAC-type reference voltage supply circuit for dummy pixels and a DAC-type reference voltage supply circuit for effective pixels.

  FIG. 3 shows a configuration using two general R-2R DACs, and the bits are B0, B1, and B2 for simplification, but this number of bits can be any number. I do not care. B0 is LSB and B3 is MSB.

  125 is a DAC-type reference voltage supply circuit for effective pixels, 133 is a DAC-type reference voltage supply circuit for dummy pixels, and 401 is a resistor group forming a DAC-type reference voltage supply circuit 125 for effective pixels. R, 402 is a resistor group forming a DAC-type reference voltage supply circuit 125 for an effective pixel, the resistance value is 2 × R, and 403 is a DAC-type reference voltage supply for an effective pixel that switches the voltage to the VR or GND level. A switch group of the circuit 125, 404 is an output buffer of the DAC reference voltage supply circuit 125 for the effective pixel, 411 is a resistor group forming the DAC reference voltage supply circuit 133 for the effective pixel, and the resistance value is R 412 Is a resistor group forming a DAC-type reference voltage supply circuit 133 for an effective pixel. The resistance value is 2 × R and 413 is an DAC for an effective pixel that switches the voltage to the VR or GND level. A switch group 414 of the reference voltage supply circuit 133 of the type is an output buffer of the DAC reference voltage supply circuit 133 for the effective pixel.

  Here, the reference output from the DAC reference voltage supply circuit 133 for dummy pixels is output as compared to the DAC reference voltage supply circuit 125 for effective pixels that need to be adapted to AD conversion from a dark image to a bright image. Since the voltage is close to that of a dark image, the output reference voltage range may be small. Therefore, for the digital input bits B0, B1, and B2 used in the DAC type reference voltage supply circuit 125, the DAC type reference voltage supply circuit 133 receives the lower bits B0 and B1 of the digital input bits.

  The number of low-order bits input to the DAC-type reference voltage supply circuit 133 only needs to be sufficient to enable AD conversion of the dummy pixels. Here, the description is made with two bits B0 and B1. However, there is no particular limitation.

  Further, by using the input bit in common, the transition times of the reference voltages of the DAC-type reference voltage supply circuit 125 and the DAC-type reference voltage supply circuit 133 can be matched. Also, since the DAC configuration is only the number of input bits, the voltage error between the reference voltage output from the DAC-type reference voltage supply circuit 125 and the reference voltage output from the DAC-type reference voltage supply circuit 133 is also increased. The error can be reduced.

  Although the preferred embodiment of the present invention has been described above, the number of times of AD conversion of dummy pixels is described here as two times, but the number of branches of 134 multiplexers and the AD conversion result of dummy pixels are recorded. By using a plurality of recording devices and the like, it is possible to perform AD conversion a plurality of times. By performing the process a plurality of times, the sampling timing difference ΔTs−3 for AD conversion between the effective pixel and the dummy pixel can be further reduced, and it can be made less susceptible to the influence of power supply fluctuation.

[Example 2]
Hereinafter, with reference to FIG. 4, an imaging apparatus according to a second embodiment of the present invention will be described.
In the first embodiment, a single dummy pixel is described, but it is easily affected by random noise. Therefore, it is more preferable that the dummy pixels have a plurality of columns. Here, an imaging apparatus when there are a plurality of dummy pixels will be described.

  In FIG. 4, the same parts as those in FIG.

  226 is a second dummy pixel array unit, 227 is a second dummy pixel to which no photoelectric conversion element is connected, 228 is a second AD converter that AD-converts data of the second dummy pixel, and 218 is a second dummy pixel A second comparator for comparing the dummy pixel data of the second dummy pixel, 219 a second up / down counter for the second dummy pixel, 234 a second multiplexer for branching the data from the up / down counter for the dummy pixel, 235 Is a third dummy pixel memory for holding data from the up / down counter for the second dummy pixel, 236 is a fourth dummy pixel for holding data from the up / down counter for the second dummy pixel 237 is a first arithmetic unit for calculating an average value of the data of the first dummy pixel memory and the third dummy pixel memory, and 238 is the second memory. A second calculator for calculating an average value of the data and the fourth dummy pixel memory of the memory for over pixels.

  Here, the result of AD conversion of the first dummy pixel for the first time and the result of AD conversion of the second dummy pixel for the first time are averaged by the calculation unit 237, and the first dummy pixel is AD converted for the second time. The arithmetic unit 238 averages the result of the above and the result of AD conversion of the second dummy pixel for the second time. When the luminance level of the effective pixel data is low, the subtraction process is performed using the data obtained by averaging the AD conversion data performed at the first time, that is, the output data of the calculation unit 237, and when the luminance level of the effective pixel data is high Subtraction processing is performed using data obtained by averaging the AD conversion data performed for the second time, that is, output data of the calculation unit 237.

  By using the data of a plurality of dummy pixels, the influence of random noise is eliminated, and even when the luminance signal level is high, the AD conversion sampling timing with the dummy pixel signal can be made close, and the sampling time difference ΔTs −3 can be reduced, making it less susceptible to low frequency power supply fluctuations, and reducing horizontal noise due to power fluctuations and other noise.

[Example 3]
Hereinafter, with reference to FIG. 5, an image pickup apparatus according to a third embodiment of the present invention will be described.

  In FIG. 5, the same parts as in FIG. In the first embodiment, the characteristics of the DAC-type reference voltage supply circuit 125 for the effective pixel and the DAC-type reference voltage supply circuit 133 for the dummy pixel vary, which causes an offset error. Considering the point.

  A dummy pixel comparator 329 uses Vref as a comparison voltage. 330 is an up / down counter for counting the output of the comparator, 334 is a memory for holding the output result from 330, 335 is a DAC type reference voltage supply circuit 125 based on the data from the memory 135 and the data from the memory 334 An offset detection unit 336 detects an offset of the DAC-type reference voltage supply circuit 133. A subtraction unit 336 subtracts data from the offset detection unit from comparison data of the dummy pixels.

  The comparator 329 receives the output voltage from the dummy pixel and the output of the DAC-type reference voltage supply circuit 125, and the comparator 129 receives the output voltage from the dummy pixel and the output of the DAC-type reference voltage supply circuit 133. Entered. For this reason, the errors of the DAC-type reference voltage supply circuit 125 and the DAC-type reference voltage supply circuit 133 are recorded in the memory 330 and the memory 135, and the offset detection unit 335 detects the error of the DAC-type reference voltage supply circuit 125 and the DAC. The offset error of the reference voltage supply circuit 133 of the type is detected, and it is subtracted from the dummy data of the memory 135 and the dummy data of 136 to correct it.

  Thereby, it is possible to correct the offset error between the DAC-type reference voltage supply circuit 125 and the DAC-type reference voltage supply circuit 133, and even when the luminance signal level is high, the sampling timing for AD conversion of the dummy pixel signal , The sampling time difference ΔTs−3 can be reduced, the influence of low frequency power supply fluctuations can be reduced, and the horizontal noise due to noise such as power supply fluctuations can be reduced.

  As mentioned above, although preferable embodiment of this invention was described, this invention is not limited to these embodiment, A various deformation | transformation and change are possible within the range of the summary.

DESCRIPTION OF SYMBOLS 100 ... Solid-state image sensor, 111 ... Pixel array part, 112 ... Unit pixel containing a photoelectric conversion element, 113 ... Row selection signal line, 114 ... Column signal line, 115 ... Row Scanning circuit 116... Column AD converter, 117... Multiple column AD converters 118... Comparator 119. Up / down counter 120. Signal output line 122 ... Output circuit 123 ... Column scanning circuit 124 ... Timing control circuit 125 ... Reference voltage supply circuit 126 ... Me pixel array unit 127 ... Dummy pixel , 128... AD converter, 129 ... dummy pixel comparator, 130 ... dummy pixel up / down counter, 131 ... dummy pixel memory, 132 ... subtractor, 133 ... dummy Pixel reference Voltage supply circuit, 134 ... multiplexer, 135 ... first dummy pixel memory, 136 ... second dummy pixel memory, 137 ... selector

Claims (7)

An effective pixel unit in which unit pixels including photoelectric conversion elements are two-dimensionally arranged in a matrix, a dummy pixel unit to which no photoelectric conversion elements are connected, and each unit pixel of the effective pixel unit and the dummy pixel unit for each row Row scanning means for selectively controlling
First analog-to-digital conversion means for converting an analog signal output from a unit pixel of an effective pixel portion selected and controlled by the row scanning means into a digital signal;
First recording means for recording data obtained from the first analog-digital conversion means;
Second analog-to-digital conversion means for performing analog-to-digital conversion of an analog signal output from the dummy pixel section a plurality of times during a period in which the first analog-to-digital conversion means performs analog-to-digital conversion;
A plurality of recording means for recording a plurality of data obtained by the second analog-digital conversion means;
Selection means for selecting one of a plurality of data recorded in the plurality of recording means according to the timing at which the first analog-digital conversion is performed;
An image pickup apparatus comprising: first calculation means for calculating data obtained from the first analog-digital conversion means and data selected by the selection means. The first and second analog-to-digital conversion means output the analog signal output from the unit pixel in the row selected and controlled by the row scanning means and the digital-to-analog conversion means, and according to the passage of time. A reference signal whose voltage level changes, a comparison means for comparing the analog signal output from the pixel with the reference signal and outputting a determination result, and a counting means for counting the elapsed time during which the determination result is output; The imaging apparatus according to claim 1, wherein: The reference signal whose voltage level changes with the passage of time includes a first reference signal used for the first analog-digital conversion means and a second reference used for the second analog-digital conversion means. The imaging apparatus according to claim 2, wherein at least two signals are present. 3. The imaging apparatus according to claim 2, wherein the digital-analog converting means for outputting the second reference signal is inputted with lower bits of a digital-analog converter for outputting the first reference signal. . Obtained from a plurality of columns of dummy pixel portions to which photoelectric conversion elements are not connected, a plurality of analog-digital conversion means for analog-digital conversion of the plurality of columns of dummy pixel portions, and the plurality of analog-digital conversion means The imaging apparatus according to claim 1, further comprising a plurality of recording means for recording results. A second calculation means for calculating an average value of the results recorded in the plurality of recording means according to claim 5 and a result of the second calculation means are obtained from an analog-digital conversion result of the effective pixel portion. The imaging apparatus according to claim 1, further comprising a first computing unit that performs computation. First conversion means for analog-digital conversion of the dummy pixel portion using the first reference signal, and second conversion means for analog-digital conversion of the dummy pixel portion using the second reference signal And
Detection means for detecting an error between the first reference signal and the second reference signal from the result obtained by the first conversion means and the result obtained by the second conversion means; The first calculation means for calculating a result obtained from the detection means for detecting the error from a result obtained by performing analog-digital conversion a plurality of times in the dummy pixel portion. Imaging device.