CN117200789A

CN117200789A - Analog-to-digital conversion circuit

Info

Publication number: CN117200789A
Application number: CN202311198671.9A
Authority: CN
Inventors: 邹维; 刘俊; 何波
Original assignee: Hangzhou Hikmicro Sensing Technology Co Ltd
Current assignee: Hangzhou Hikmicro Sensing Technology Co Ltd
Priority date: 2023-09-15
Filing date: 2023-09-15
Publication date: 2023-12-08

Abstract

The application provides an analog-to-digital conversion circuit which comprises a ramp signal generator, a first comparator, a second comparator, a first latch and a second latch. And a ramp signal generator for outputting a plurality of first ramp signals to the first comparator and outputting a plurality of second ramp signals to the second comparator. The first comparator is used for comparing the voltage signal related to the target pixel with the first slope signal and outputting a first comparison result to the first latch; and the second comparator is used for comparing the voltage signal related to the target pixel with the second ramp signal and outputting a second comparison result to the second latch. A first latch for latching a first count value based on the first comparison result; a second latch for latching a second count value based on the second comparison result; the first count value and the second count value are used for determining a voltage response value of the target pixel. By the technical scheme, the voltage response value can be accurately obtained, namely, the error of the voltage response value is small.

Description

Analog-to-digital conversion circuit

Technical Field

The application relates to the technical field of circuits, in particular to an analog-to-digital conversion circuit.

Background

An analog-to-digital conversion circuit (Analog to Digital Converter, ADC) is a circuit for converting an analog signal into a digital signal, typically converting an input voltage signal into an output digital signal. The main technical indexes of the analog-digital conversion circuit comprise resolution, quantization error, conversion time and the like. The resolution of the analog-to-digital conversion circuit is represented by the number of digits of the output binary number, and the more the digits are, the smaller the error is, and the higher the conversion accuracy is. The quantization error of the analog-to-digital conversion circuit is an inherent error due to the integral quantization. The conversion time of the analog-to-digital conversion circuit refers to the time required for completing one analog-to-digital conversion.

The analog-to-digital conversion circuit can be applied to any device requiring analog-to-digital conversion, and the analog-to-digital conversion circuit is adopted on the device to convert an input voltage signal into an output digital signal, and the digital signal can reflect the voltage value of the voltage signal, i.e. the voltage value of the voltage signal can be determined based on the digital signal. However, when the analog-to-digital conversion circuit is used to convert the voltage signal into the digital signal, there may be an error in the digital signal, and this error may result in that the voltage value of the voltage signal cannot be obtained accurately.

Disclosure of Invention

The application provides an analog-to-digital conversion circuit, which comprises a ramp signal generator, a first comparator, a second comparator, a first latch and a second latch, wherein the first comparator is connected with the ramp signal generator; wherein:

the ramp signal generator is used for outputting a plurality of first ramp signals to the first comparator and outputting a plurality of second ramp signals to the second comparator; wherein the slopes corresponding to the plurality of first slope signals and the slopes corresponding to the plurality of second slope signals are opposite numbers;

the first comparator is used for comparing the voltage signal related to the target pixel with the first slope signal and outputting a first comparison result to the first latch; the second comparator is used for comparing the voltage signal related to the target pixel with a second slope signal and outputting a second comparison result to the second latch;

the first latch is used for latching a first count value based on the first comparison result; the second latch is used for latching a second count value based on the second comparison result; the first count value and the second count value are used for determining a voltage response value of the target pixel.

As can be seen from the above technical solutions, in the embodiments of the present application, an analog-to-digital conversion circuit is designed, which can generate a plurality of first ramp signals and a plurality of second ramp signals, latch a first count value based on a first comparison result of a voltage signal associated with a target pixel and the plurality of first ramp signals, latch a second count value based on a second comparison result of the voltage signal associated with the target pixel and the plurality of second ramp signals, and determine a voltage response value of the target pixel based on the first count value and the second count value. When the analog-to-digital conversion circuit is used for converting the voltage signal into the digital signal, the two digital signals (namely the first count value and the second count value) are obtained, and the error of the digital signal is eliminated or reduced through the difference value of the two digital signals, so that the voltage value (namely the voltage response value) of the voltage signal can be accurately obtained, namely the error of the voltage response value is smaller.

Drawings

In order to more clearly illustrate the embodiments of the present application or the technical solutions in the prior art, the following description will briefly describe the drawings required to be used in the embodiments of the present application or the description in the prior art, and it is obvious that the drawings in the following description are only some embodiments described in the present application, and other drawings may be obtained according to these drawings of the embodiments of the present application for a person having ordinary skill in the art.

FIG. 1 is a schematic diagram of an analog-to-digital conversion circuit according to an embodiment of the present application;

FIG. 2 is a schematic diagram illustrating an operation timing of an analog-to-digital conversion circuit according to an embodiment of the present application;

FIG. 3 is a schematic diagram of an analog-to-digital conversion circuit according to an embodiment of the present application;

FIG. 4 is a schematic diagram of an analog-to-digital conversion circuit according to an embodiment of the present application;

fig. 5 is a schematic diagram illustrating an operation timing of the analog-to-digital conversion circuit according to an embodiment of the present application.

Detailed Description

The terminology used in the embodiments of the application is for the purpose of describing particular embodiments only and is not intended to be limiting of the application. As used in this specification and the appended claims, the singular forms "a," "an," and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise. It should also be understood that the term "and/or" as used herein refers to any or all possible combinations including one or more of the associated listed items.

It should be understood that although the terms first, second, third, etc. may be used in embodiments of the present application to describe various information, these information should not be limited to these terms. These terms are only used to distinguish one type of information from another. For example, first information may also be referred to as second information, and similarly, second information may also be referred to as first information, without departing from the scope of the application. Depending on the context, furthermore, the word "if" used may be interpreted as "at … …" or "at … …" or "in response to a determination".

An analog-to-digital conversion circuit is a circuit for converting an analog signal into a digital signal, typically an analog voltage signal. The monoclinic analog-to-digital conversion circuit (i.e., monoclinic ADC) is a type of analog-to-digital conversion circuit, and by comparing an analog voltage signal with a ramp signal of a fixed slope, a count value from a start time to a target time (i.e., a time at which the ramp signal is equal to the analog voltage signal) of the ramp signal is quantized with reference to a counter, and the count value is an output digital signal.

Referring to fig. 1, a schematic diagram of an analog-to-digital conversion circuit (e.g., a monoclinic analog-to-digital conversion circuit) is shown, where the analog-to-digital conversion circuit may include a ramp signal generator, a counter, a comparator, a latch, and the like. Wherein the N bit output end of the counter is connected with the data input end of the N bit latch, N represents the conversion precision of the analog-to-digital conversion circuit for controlling the clock period number, and if one analog conversion is completed, at least 2 is needed ^N For a clock cycle. The output of the comparator is connected to the enable input of the N bit latch. Analog voltage signal V to be converted _IN (i.e. input voltage signal or inputThe output voltage signal) is connected with the positive input end of the comparator, and the ramp signal (namely the ramp voltage signal, recorded as V) _RAMP ) And the negative input end of the comparator is connected.

Referring to fig. 2, a schematic diagram of an operation timing sequence of an analog-to-digital conversion circuit (such as a monoclinic analog-to-digital conversion circuit), a basic operation principle of the analog-to-digital conversion circuit may be expressed as: before the analog-to-digital conversion circuit performs analog-to-digital conversion, the counter is reset to all 0 by the reset signal RST, and the ramp signal generator is reset to the initial ramp signal V by the reset signal RST _{REF_L} Initial ramp signal V _{REF_L} Is the minimum voltage value.

After the reset is released, the counter begins to increment the count value sequentially from all 0 to all 1, such as sequentially outputting 0, 1, 2, 3, 2 to the latch ^N -1 and so on, i.e. 1 clock cycle per interval, 1 count value is output, e.g. the first clock cycle outputs count value 0, the second clock cycle outputs count value 1, the third clock cycle outputs count value 2, and so on, each clock cycle outputs an incremented count value.

After the reset is released, the ramp signal generator generates an initial ramp signal V _{REF_L} Initially, the ramp signal is incremented based on a fixed slope and sequentially output a ramp signal to the comparator, i.e., 1 ramp signal per 1 clock cycle, with the initial ramp signal V being output to the comparator, e.g., the first clock cycle _{REF_L} The second clock cycle outputs a ramp signal S1, the ramp signal S1 being based on the initial ramp signal V _{REF_L} And a fixed slope determination, the third clock cycle outputs a ramp signal S2, and so on, each clock cycle generates a ramp signal based on the fixed slope and outputs the ramp signal.

Each ramp signal (e.g. V _{REF_L} S1, S2, etc.) are denoted as ramp signals V _RAMP During the first few clock cycles (i.e. the clock cycles preceding the count value P), due to the ramp signal V _RAMP Less than the analogue voltage signal V _IN The comparator receives the ramp signal V _RAMP Thereafter, to the ramp signal V _RAMP And simulation ofVoltage signal V _IN The comparison is performed and a high level is output. The latch may change the count value after receiving the count value output from the counter, and may not latch the count value.

When the ramp signal V _RAMP Greater than or equal to the analogue voltage signal V _IN At the time, i.e. clock period from the count value P, the comparator receives the ramp signal V _RAMP Thereafter, to the ramp signal V _RAMP And analog voltage signal V _IN The comparison is performed and the output low level, i.e. the high level is switched to the low level. The latch latches the counter output code (the output code is the count value) corresponding to the moment of the falling edge of the output of the comparator, namely, the latch latches the count value after receiving the count value output by the counter, the subsequent count value is not changed, and the latched count value is the analog voltage signal V _IN The corresponding number, such as count value P in fig. 2.

From the working principle of the analog-to-digital conversion circuit, it can be seen that: the analog-to-digital conversion circuit converts an analog-to-digital input signal (i.e. analog voltage signal V _IN ) Converted into time length, and quantized to obtain analog voltage signal V _IN A corresponding count value P. Obviously, analog voltage signal V _IN The size of the analog-to-digital conversion circuit is proportional to the time length from the reset release time to the time of the falling edge output by the comparator, the time length corresponds to the count value latched by the latch, and the LSB of the analog-to-digital conversion circuit corresponds to the clock period T of the counter on the time axis _CLK 。

The analog-to-digital conversion circuit can be suitable for multiplexing, and when multiplexing is needed for simultaneous conversion, the counter and the ramp signal generator can be shared, and each path corresponds to one comparator and one latch. Referring to fig. 3, a schematic diagram of an M-channel N-bit precision analog-to-digital conversion circuit (e.g., a monoclinic analog-to-digital conversion circuit) is shown.

The analog-to-digital conversion circuit may include a counter and a ramp signal generator, and may include M analog voltage signals V _IN M comparators corresponding to each other, the analog-to-digital conversionThe conversion circuit can comprise M paths of analog voltage signals V _IN M latches in one-to-one correspondence. M-way analog voltage signal V _IN Corresponding to the same counter, M paths of analog voltage signals V _IN Corresponding to the same ramp signal generator.

Obviously, the counter can output the count value to M paths of analog voltage signals V simultaneously in each clock period _IN M latches corresponding to each other, the ramp signal generator outputs a ramp signal V _RAMP Output to M paths of analog voltage signals V _IN And M comparators respectively corresponding to the two comparators. For each comparator, the analog voltage signal V of the comparator can be based on _IN And ramp signal V _RAMP Comparing and outputting the comparison result to the latch, i.e. the input of the latch is the analog voltage signal V _IN The corresponding comparison result and the count value output by the counter.

By M paths of analog voltage signals V _IN The same counter and ramp signal generator are shared, so that the area and the power consumption of the analog-to-digital conversion circuit can be saved, and the analog-to-digital conversion circuit has great advantages compared with other types of analog-to-digital conversion circuits.

For the analog-to-digital conversion circuit of N-bit resolution shown in FIG. 1 or FIG. 3, at least 2 is required to complete one analog conversion ^N With a clock period, i.e. counter generation 2 ^N A count value, a ramp signal generator generates 2 ^N Ramp signals V _RAMP Based on 2 ^N Sum of count values 2 ^N Ramp signals V _RAMP And finishing analog-to-digital conversion.

Illustratively, as can be seen from the timing of FIG. 2, T can be determined using the following equations (1) and (2) _OUT And D _OUT ，T _OUT Representing the corresponding time length of the first P count values, the count value P is the ramp signal V _RAMP Greater than or equal to the analogue voltage signal V _IN A corresponding count value. D (D) _OUT Representing a count value P. By substituting equation (1) into equation (2), it is also possible to determine D using equation (3) _OUT 。

In the formulas (1), (2) and (3), N represents the conversion accuracy of the analog-to-digital conversion circuit for controlling the number of clock cycles, e.g., at least 2 are required for completing one analog conversion ^N For a clock cycle. T (T) _CLK Representing the length of one clock cycle. V (V) _IN Representing an analog voltage signal, V _{REF_L} Representing the minimum voltage value in the first ramp signal, i.e., all ramp signals. V (V) _{REF_H} Representing the last ramp signal, i.e. the maximum voltage value in all ramp signals. P represents a ramp signal V _RAMP Greater than or equal to the analogue voltage signal V _IN The corresponding count value is the count value latched by the latch.

Obviously, based on the formula (3), D _OUT 、N、V _{REF_L} 、V _{REF_H} All are known values, and V can be obtained by substituting the values into the formula (3) _IN And V is _IN The voltage response value to be solved. In the formula (3), the count value D _OUT Magnitude and analog voltage signal V _IN Is a strict linear relationship.

However, since the analog-to-digital conversion circuit is reset, it is difficult to ensure that the counter count start time and the ramp start point of the ramp signal generator are completely synchronized, and an offset is generated in response to the final output. In addition, the conversion delay of the comparator, which is not a fixed value and varies with the analog voltage signal, is usually nonlinear. For example, assume that the delay from the falling edge of the reset signal RST to the start of counting by the counter is TD _{cnt_start} The delay of the counter output to the latch input is TD _{cnt_out} The delay from the falling edge of the reset signal RST to the ramp starting point of the ramp signal generator is TD _ramp The conversion delay of the comparator is TD _comp (V _IN ) Thus, equation (1) needs to be replaced with equation (4):

due to TTD _comp (V _IN ) With analogue voltage signal V _IN And then, after substituting equation (4) into equation (2), equation (5) can be derived for solving for D _OUT ：

As can be seen by comparing equation (5) with equation (3), the fixed delay TD _ramp 、TD _{cnt_start} 、TD _{cnt_out} TTD with non-linear variation introduced with offset error _comp (V _IN ) Not only can lead in offset error, but also can lead the analog voltage signal V _IN To D _OUT Is no longer linear, i.e. is an integral non-linearity. With higher conversion accuracy and conversion rate, the time length T corresponding to LSB of the analog-to-digital conversion circuit _CLK Smaller and smaller, the offset and nonlinearity produced by the same delay will become larger and larger in LSB units. In summary, when the analog-to-digital conversion circuit is used to convert the voltage signal into the digital signal, the digital signal may have an error, and the voltage response value cannot be obtained accurately due to the error. The offset error refers to the difference between the actual conversion characteristic curve and the ideal conversion characteristic curve of the analog-digital conversion circuit in the horizontal direction. The integral nonlinearity refers to the maximum difference between the actual conversion characteristic curve of the analog-digital conversion circuit and the linear fitting curve of the analog-digital conversion circuit in the vertical direction.

In view of the above findings, an embodiment of the present application provides an analog-to-digital conversion circuit (such as a monoclinic analog-to-digital conversion circuit) that uses two independent comparators to simulate a voltage signal V _IN Ramp respectively and differentiallyAnd comparing the signals, and finally outputting two groups of count values (namely digital codes) and performing subtraction operation on the two groups of count values. Thus, offset errors caused by asynchronous counting starting time of the counter and slope starting point of the slope signal generator can be eliminated, nonlinear influence caused by conversion delay of the comparator along with the change of the analog voltage signal can be eliminated, and influence caused by delay difference of the counter output to each path of latch can be eliminated.

By way of example, the analog-to-digital conversion circuit may include, but is not limited to, a counter, a ramp signal generator, a first comparator, a second comparator, a first latch, and a second latch. Referring to fig. 4, a schematic diagram of an analog-to-digital conversion circuit (e.g., a monoclinic analog-to-digital conversion circuit) is shown, where the analog-to-digital conversion circuit may include, but is not limited to: ramp signal generator, counter, comparator a (i.e., first comparator), comparator B (i.e., second comparator), latch a (i.e., first latch), and latch B (i.e., second latch).

The N bit output end of the counter is connected with the data input end of the N bit latch A, the N bit output end of the counter is connected with the data input end of the N bit latch B, N represents the conversion precision of the analog-to-digital conversion circuit for controlling the clock period number, for example, at least 2 are needed for completing one analog conversion ^N For a clock cycle. The output end of the comparator A is connected with the enabling input end of the N bit latch A, and the analog voltage signal V which needs to be converted is obtained _IN I.e. an input voltage signal or an output voltage signal, is connected to the positive input of the comparator a. The output end of the comparator B is connected with the enabling input end of the N bit latch B, and the analog voltage signal V _IN And is connected to the negative input of the comparator B. Wherein the analog voltage signal V _IN The voltage signal related to the target pixel can be the voltage signal directly output by the target pixel or the voltage signal processed by other circuits after being output by the target pixel, and the analog voltage signal V is not limited to the voltage signal _IN The voltage signal V associated with the target pixel _IN 。

The ramp signal generator outputs two voltage signals (i.e. ramp voltage signals, which are referred to as ramp signals), two ramp signalsThe ramp signal is a ramp signal V _{RAMP_P} And ramp signal V _{RAMP_N} Ramp signal V _{RAMP_P} A negative input terminal of the comparator A is connected with the ramp signal V _{RAMP_N} The positive input of the comparator B is connected.

In one possible implementation, to generate two ramp signals (i.e., two ramp signals are generated simultaneously per clock cycle), the ramp signal generator may be one differential ramp signal generator, i.e., two ramp signals are generated by one differential ramp signal generator. The differential ramp signal generator is a circuit capable of generating two paths of ramp signals with symmetrical initial voltage and common mode voltage and opposite ramp slopes, and the circuit structure of the differential ramp signal generator is not limited in this embodiment.

Referring to fig. 4, in the case of the differential ramp signal generator, the two ramp signals generated by the differential ramp signal generator may be the ramp signals V at the positive output terminal, respectively _{RAMP_P} And a ramp signal V at the negative output _{RAMP_N} Ramp signal V at positive output end _{RAMP_P} A slope signal V connected with the negative input end and the negative output end of the comparator A _{RAMP_N} The positive input of the comparator B is connected.

The positive output of the differential ramp signal generator is required to generate a set of ramp signals including a plurality of ramp signals V _{RAMP_P} A plurality of ramp signals V _{RAMP_P} Referred to as a plurality of first ramp signals. Wherein the initial value of the first ramp signals is the minimum voltage value V _{REF_L} And the plurality of first ramp signals are generated based on a first slope, the first slope being positive. For example, the differential ramp signal generator generates a plurality of first ramp signals with a minimum voltage value V based on the first slope _{REF_L} The last one of the first ramp signals is the maximum voltage value V _{REF_H} 。

For example, the minimum voltage value V _{REF_L} Is a preset voltage value, such as 1V, and has a maximum voltage value V _{REF_H} Is a pre-configured voltage value, a fixed value such as 16V, etc., then the minimum power is knownPressure value V _{REF_L} And maximum voltage value V _{REF_H} The first slope may then be known. Of course, the minimum voltage value V may be preconfigured _{REF_L} And a first slope, a known minimum voltage value V _{REF_L} And a first slope, the maximum voltage value V can be obtained _{REF_H} . Alternatively, the maximum voltage value V may be preconfigured _{REF_H} And a first slope, a known maximum voltage value V _{REF_H} And a first slope, the minimum voltage value V can be obtained _{REF_L} 。

For example, when the differential ramp signal generator sequentially generates a plurality of first ramp signals, assuming that there are 16 clock periods in total and 1 first ramp signal is generated in 1 clock period, the plurality of first ramp signals sequentially generate 1V, 2V, 3V, 16V, that is, 16 first ramp signals in total, and the start value of the plurality of first ramp signals is the minimum voltage value V _{REF_L} The last one of the first ramp signals is the maximum voltage value V _{REF_H} And the plurality of first ramp signals are generated based on the first slope. Alternatively, when the differential ramp signal generator sequentially generates the plurality of first ramp signals, not controlled by the clock period, but generates a continuous ramp signal, i.e., generates the continuous ramp signal based on the first slope, then the plurality of first ramp signals are sequentially 1V, 1.1V, 1.2V, 2V, 3V, 16V, and of course, the granularity of the first ramp signals may be greater or smaller, i.e., generates a large number of first ramp signals, which are continuous ramp signals, and the start value of the plurality of first ramp signals is the minimum voltage value V _{REF_L} The last one of the first ramp signals is the maximum voltage value V _{REF_H} 。

The negative output of the differential ramp signal generator is required to generate a set of ramp signals including a plurality of ramp signals V _{RAMP_N} A plurality of ramp signals V _{RAMP_N} Referred to as a plurality of second ramp signals. The slopes corresponding to the plurality of first slope signals and the slopes corresponding to the plurality of second slope signals are opposite to each other.

Wherein the initial value of the plurality of second ramp signals is the maximum voltage value V _{REF_H} And a plurality of The second ramp signal is generated based on a second slope that is negative and has the same absolute value as the first slope, e.g., 1 for the first slope and-1 for the second slope, or 2 for the first slope and-2 for the second slope, i.e., the second slope is determined based on the first slope. For example, the differential ramp signal generator generates a plurality of second ramp signals with a maximum voltage value V based on the second slope _{REF_H} The last one of the second ramp signals is a minimum voltage value V _{REF_L} 。

For example, the second slope is determined on the basis of the known first slope, again due to the maximum voltage value V _{REF_H} Is known and can therefore be based on the maximum voltage value V _{REF_H} And the second slope generates a second ramp signal.

For example, when the differential ramp signal generator sequentially generates a plurality of second ramp signals, assuming that there are 16 clock periods in total and 1 second ramp signal is generated in 1 clock period, the plurality of second ramp signals sequentially generate 16V, 15V, 14V, …, and 1V, that is, 16 second ramp signals are generated in total, and the initial value of the plurality of second ramp signals is the maximum voltage value V _{REF_H} The last one of the second ramp signals is a minimum voltage value V _{REF_L} And the plurality of second ramp signals are generated based on the second slope. Alternatively, when the differential ramp signal generator sequentially generates the plurality of second ramp signals, not controlled by the clock period, but generates a continuous ramp signal, that is, generates the continuous ramp signal based on the second slope, then the plurality of second ramp signals are sequentially 16V, 15.9V, 15.8V, 15V, 14V, 1V, and of course, the granularity of the second ramp signals may be greater or smaller, that is, a large number of second ramp signals are generated, the second ramp signals are continuous ramp signals, and the initial values of the plurality of second ramp signals are maximum voltage values V _{REF_H} The last one of the second ramp signals is a minimum voltage value V _{REF_L} 。

In another possible embodiment, the ramp signal generator may include a logic circuit for generating two ramp signals (i.e., generating two ramp signals simultaneously per clock cycle)Includes a first sub-generator and a second sub-generator, i.e. there are two sub-generators. One set of ramp signals is generated by a first sub-generator, another set of ramp signals is generated by a second sub-generator, and two sets of ramp signals are generated by the first sub-generator and the second sub-generator. For example, the ramp signal generated by the first sub-generator is a ramp signal V _{RAMP_P} Ramp signal V _{RAMP_P} The second sub-generator generates a ramp signal V as a ramp signal _{RAMP_N} Ramp signal V _{RAMP_N} The positive input of the comparator B is connected.

The first sub-generator needs to generate a set of ramp signals including a plurality of ramp signals V _{RAMP_P} A plurality of ramp signals V _{RAMP_P} Referred to as a plurality of first ramp signals. Wherein the initial value of the first ramp signals is the minimum voltage value V _{REF_L} And the plurality of first ramp signals are generated based on a first slope, the first slope being positive. For example, the first sub-generator generates a plurality of first ramp signals with a minimum voltage value V based on the first slope _{REF_L} The last one of the first ramp signals is the maximum voltage value V _{REF_H} . The process of generating the plurality of first ramp signals by the first sub-generator is similar to the process of generating the plurality of first ramp signals by the differential ramp signal generator, and thus, the description thereof will not be repeated.

The second sub-generator is required to generate a set of ramp signals including a plurality of ramp signals V _{RAMP_N} A plurality of ramp signals V _{RAMP_N} Referred to as a plurality of second ramp signals. Wherein the initial value of the plurality of second ramp signals is the maximum voltage value V _{REF_H} The plurality of second ramp signals are generated based on the second slope, the second slope is negative, and the absolute value of the second slope is the same as the first slope, namely the second slope is determined based on the first slope. For example, the second sub-generator generates a plurality of second ramp signals with a maximum voltage value V based on the second slope _{REF_H} The last one of the second ramp signals is a minimum voltage value V _{REF_L} . Wherein the method comprises the steps ofThe process of generating the plurality of second ramp signals by the second sub-generator is similar to the process of generating the plurality of second ramp signals by the differential ramp signal generator, and thus, a detailed description thereof will not be repeated.

Referring to fig. 5, a schematic diagram of an operation timing sequence of an analog-to-digital conversion circuit (such as a monoclinic analog-to-digital conversion circuit), a basic operation principle of the analog-to-digital conversion circuit may be expressed as: the counter is reset to all 0's by a reset signal RST before the analog-to-digital conversion circuit performs analog-to-digital conversion. Positive output terminal V of differential ramp signal generator _{RAMP_P} (or first sub-generator, followed by a positive output of differential ramp signal generator for example) is reset to the initial ramp signal V by a reset signal RST _{REF_L} Initial ramp signal V _{REF_L} Is the minimum voltage value. Negative output terminal V of differential ramp signal generator _{RAMP_N} (or a second sub-generator, followed by a negative output of the differential ramp signal generator for example) is reset to the initial ramp signal V by a reset signal RST _{REF_H} Initial ramp signal V _{REF_H} Is the maximum voltage value.

In one possible implementation, after the reset is released, the counter begins to increment the count value sequentially from all 0 s to all 1 s, such as sequentially outputting 0 s, 1 s, 2 s, 3 s, 2 s to latch a (i.e., the first latch) ^N -1, etc. and outputs 0, 1, 2, 3, # 2 to latch B (i.e. the second latch) in sequence ^N -1, etc. For example, the counter may output 1 count value to each of the latch a and the latch B every 1 clock cycle, such as the first clock cycle outputting the count value 0, the second clock cycle outputting the count value 1, the third clock cycle outputting the count value 2, and so on, each clock cycle outputting an incremented count value. In summary, the counter is configured to accumulate a count value every one clock period after receiving the reset signal, and output the currently accumulated count value to the latch a and the latch B.

After the reset is released, the positive output terminal V of the differential ramp signal generator _{RAMP_P} From an initial ramp signal V _{REF_L} Initially, the first ramp signal is incremented based on the first slope and is directed to comparator aOutputting a first ramp signal, i.e. 1 first ramp signal V to the comparator A every 1 clock cycle, e.g. the first clock cycle _{REF_L} The second clock cycle outputs a first ramp signal S11, the first ramp signal S11 being based on the initial ramp signal V _{REF_L} And a first slope determination, a third clock cycle outputs a first ramp signal S12, and so on, each clock cycle generates a first ramp signal based on the first slope and outputs the first ramp signal to the comparator a.

Each first ramp signal (e.g. V _{REF_L} S11, S12, etc.) is denoted as a first ramp signal V _{RAMP_P} During the first few clock cycles (i.e. the clock cycles preceding the count value P), due to the first ramp signal V _{RAMP_P} Less than the voltage signal V associated with the target pixel _IN The comparator A receives the first ramp signal V _{RAMP_P} Thereafter, for the first ramp signal V _{RAMP_P} And voltage signal V _IN Comparing, outputting a first level based on the comparison result, the first level being used for representing the first ramp signal V _{RAMP_P} Less than the voltage signal V _IN . After receiving the count value output by the counter, the latch a only needs to follow the change of the count value, and does not latch the count value because the comparison result is the first level.

When the first ramp signal V _{RAMP_P} Greater than or equal to voltage signal V _IN At the time, i.e. the clock period from the count value P, the comparator A receives the first ramp signal V _{RAMP_P} Thereafter, for the first ramp signal V _{RAMP_P} And voltage signal V _IN Comparing, outputting a second level based on the comparison result, the second level being used for representing the first ramp signal V _{RAMP_P} Greater than or equal to voltage signal V _IN I.e. from a first level to a second level. The latch A latches the counter output code (the output code is the count value) corresponding to the falling edge time or the rising edge time of the output of the comparator A, namely, the latch A receives the counter output at the time of switching from the first level to the second level (the falling edge time or the rising edge time of the output of the comparator A)After the count value, the latch A latches the count value, and the subsequent count value is not changed, and the latched count value is the voltage signal V _IN The corresponding number, such as count value P in fig. 5.

The first level may be a high level and the second level may be a low level, based on which the high level is used to represent the first ramp signal V _{RAMP_P} Less than the voltage signal V _IN A low level for indicating the first ramp signal V _{RAMP_P} Greater than or equal to voltage signal V _IN The latch A latches the counter output code corresponding to the moment of the falling edge of the output of the comparator A. Alternatively, the first level may be a low level and the second level may be a high level, based on which the low level is used to represent the first ramp signal V _{RAMP_P} Less than the voltage signal V _IN A high level for indicating the first ramp signal V _{RAMP_P} Greater than or equal to voltage signal V _IN The latch A latches the counter output code corresponding to the rising edge time of the output of the comparator A.

In summary, the differential ramp signal generator is configured to output the first ramp signal to the first comparator (i.e. the comparator a) every one clock period after receiving the reset signal, i.e. output a plurality of first ramp signals to the first comparator. A first comparator for comparing the voltage signal V _IN And a first ramp signal and outputs a first comparison result to a first latch (e.g., latch a). For example, for each first ramp signal, if the first ramp signal is smaller than the voltage signal V _IN The first comparison result is a first level, i.e. the first comparator outputs a first level, e.g. a high level, to the first latch. If the first ramp signal is greater than or equal to the voltage signal V _IN The first comparison result is a second level, i.e. the first comparator outputs a second level, e.g. a low level, to the first latch. A first latch for latching the first count value based on the first comparison result, for example, when the first latch detects that the first comparison result is switched from the first level to the second level, latching the current count value as the first count value, that is, the first latch is used for latching the count when the first level is switched to the second level A value such as the count value P in fig. 5.

After the reset is released, the negative output terminal V of the differential ramp signal generator _{RAMP_N} From an initial ramp signal V _{REF_H} Initially, the second ramp signal is incremented based on the second slope and is output to the comparator B, i.e. 1 second ramp signal is output to the comparator B every 1 clock cycle, e.g. the first clock cycle _{REF_H} The second clock cycle outputs a second ramp signal S21, the second ramp signal S21 being based on the initial ramp signal V _{REF_H} And a second slope determination, a third clock cycle outputs a second ramp signal S22, and so on, each clock cycle generates a second ramp signal based on the second slope and outputs the second ramp signal to the comparator B.

Each of the second ramp signals (e.g. V _{REF_H} S21, S22) is denoted as a second ramp signal V _{RAMP_N} During the first few clock cycles (i.e. the clock cycle before the count value Q), due to the second ramp signal V _{RAMP_N} Voltage signal V greater than that associated with target pixel _IN The comparator B receives the second ramp signal V _{RAMP_N} Thereafter, for the second ramp signal V _{RAMP_N} And voltage signal V _IN Comparing, outputting a third level based on the comparison result, the third level being used for representing the second ramp signal V _{RAMP_N} Greater than voltage signal V _IN . After receiving the count value output by the counter, the latch B may change along with the count value, and may not latch the count value, since the comparison result is the third level.

When the second ramp signal V _{RAMP_N} Less than or equal to voltage signal V _IN At the time, i.e. the clock period from the count value Q, the comparator B receives the second ramp signal V _{RAMP_N} Thereafter, for the second ramp signal V _{RAMP_N} And voltage signal V _IN Comparing, outputting a fourth level for representing the second ramp signal V based on the comparison result _{RAMP_N} Less than or equal to voltage signal V _IN I.e. from the third level to the fourth level. Latch B will latch the ratioThe comparator B outputs a counter output code (which is a count value) corresponding to the falling edge time or the rising edge time, that is, for the time of switching from the third level to the fourth level (the comparator B outputs the falling edge time or the rising edge time), the latch B latches the count value output by the counter after receiving the count value, the subsequent count value is not changed any more, and the latched count value is the voltage signal V _IN A corresponding number, such as the count value Q in fig. 5.

The third level may be a high level and the fourth level may be a low level, based on which the high level is used to represent the second ramp signal V _{RAMP_N} Greater than voltage signal V _IN A low level for representing the second ramp signal V _{RAMP_N} Less than or equal to voltage signal V _IN The latch B latches the counter output code corresponding to the moment of the falling edge of the output of the comparator B. Alternatively, the third level may be a low level and the fourth level may be a high level, based on which the low level is used to represent the second ramp signal V _{RAMP_N} Greater than voltage signal V _IN A high level for representing the second ramp signal V _{RAMP_N} Less than or equal to voltage signal V _IN The latch B latches the counter output code corresponding to the rising edge time of the output of the comparator B.

In summary, the differential ramp signal generator is configured to output the second ramp signal to the second comparator (i.e. the comparator B) every one clock period after receiving the reset signal, i.e. output a plurality of second ramp signals to the second comparator. A second comparator for comparing the voltage signal V _IN And a second ramp signal and outputs a second comparison result to a second latch (e.g., latch B). For example, for each second ramp signal, if the second ramp signal is greater than the voltage signal V _IN The second comparison result is a third level, i.e. the second comparator outputs a third level, e.g. a high level, to the second latch. If the second ramp signal is smaller than or equal to the voltage signal V _IN The second comparison result is a fourth level, i.e., the second comparator outputs a fourth level, e.g., a low level, to the second latch. A second latch for based on the second comparison resultThe second latch latches the current count value as the second count value, that is, the second latch is used to latch the count value at the time of switching the third level to the fourth level, such as the count value Q in fig. 5, when the second latch detects that the second comparison result is switched from the third level to the fourth level.

In another possible embodiment, after the reset is released, the counter begins to increment the count value sequentially from all 0 s to all 1 s, such as sequentially outputting 0 s, 1 s, 2 s, 3 s, 2 s to latch a ^N -1, etc. and outputs 0, 1, 2, 3,..2, 2 to latch B in sequence ^N -1, etc. For example, the counter may output 1 count value to each of the latch a and the latch B every 1 clock cycle.

After the reset is released, the positive output terminal V of the differential ramp signal generator _{RAMP_P} From an initial ramp signal V _{REF_L} Initially, the first ramp signal is output to the comparator a based on the first slope increment, that is, the first ramp signal is continuously output, which is not affected by the clock period, and the output granularity of the first ramp signal may be smaller than the clock period, that is, a plurality of first ramp signals are output one clock period.

Each first ramp signal output by the differential ramp signal generator is recorded as a first ramp signal V _{RAMP_P} At the first ramp signal V _{RAMP_P} Less than the voltage signal V _IN When the comparator A receives the first ramp signal V _{RAMP_P} Thereafter, for the first ramp signal V _{RAMP_P} And voltage signal V _IN The comparison is performed, and the first level is output based on the comparison result. After receiving the count value output by the counter, the latch a only needs to follow the change of the count value, and does not latch the count value because the comparison result is the first level.

When the first ramp signal V _{RAMP_P} Greater than or equal to voltage signal V _IN When the comparator A receives the first ramp signal V _{RAMP_P} Thereafter, for the first ramp signal V _{RAMP_P} And voltage signal V _IN Comparing, outputting the second level based on the comparison result, i.e. switching from the first level to the second levelA level.

The latch A latches the counter output code corresponding to the falling edge time or rising edge time of the output of the comparator A, namely, after the latch A receives the counter value output by the counter, the counter value is not changed any more, and the latched counter value is the voltage signal V _IN The corresponding number is the count value P of fig. 5.

After the reset is released, the negative output terminal V of the differential ramp signal generator _{RAMP_N} From an initial ramp signal V _{REF_H} Initially, the second ramp signal is output to the comparator B based on the second slope increment, that is, the second ramp signal is continuously output, which is not affected by the clock period, and the output granularity of the second ramp signal may be smaller than the clock period, that is, a plurality of second ramp signals are output one clock period.

Each second ramp signal output by the differential ramp signal generator is recorded as a second ramp signal V _{RAMP_N} At the second ramp signal V _{RAMP_N} Greater than voltage signal V _IN When the comparator B receives the second ramp signal V _{RAMP_N} Thereafter, for the second ramp signal V _{RAMP_N} And voltage signal V _IN And comparing, and outputting a third level based on the comparison result. After receiving the count value output by the counter, the latch B may change along with the count value, and may not latch the count value, since the comparison result is the third level.

When the second ramp signal V _{RAMP_N} Less than or equal to voltage signal V _IN When the comparator B receives the second ramp signal V _{RAMP_N} Thereafter, for the second ramp signal V _{RAMP_N} And voltage signal V _IN The comparison is performed, and the fourth level is output based on the comparison result, i.e., the third level is switched to the fourth level.

The latch B latches the counter output code corresponding to the falling edge time or rising edge time of the comparator B, namely, the latch B receives the count at the time of switching from the third level to the fourth level (the falling edge time or the rising edge time)After the counter value output by the counter, the counter value is latched, the subsequent counter value is not changed any more, and the latched counter value is the voltage signal V _IN Corresponding digital quantities such as count value 0 of fig. 5.

For example, after the count value of the counter reaches all 1, the first count value P latched by the latch a and the second count value Q latched by the latch B may be subtracted to obtain the target count value DOUT, e.g., dout=p-Q, where the target count value DOUT obtained by the subtraction is the sum voltage signal V _IN The corresponding digital quantity, i.e. the target count value DOUT, is used to determine the voltage signal V _IN Corresponding voltage response values.

Illustratively, it can be seen from the operating principle of the analog-to-digital conversion circuit that: the analog-to-digital conversion circuit converts the analog-to-digital voltage signal (i.e. voltage signal V _IN ) Converted into time length, and quantized to obtain voltage signal V _IN Corresponding count value P and count value Q. Obviously, the voltage signal V _IN The magnitude of (a) is proportional to the time length from the reset release time to the time of the falling edge output by the comparator, the time length corresponds to the count value latched by the latch A, the time length also corresponds to the count value latched by the latch B, and the LSB of the analog-to-digital conversion circuit corresponds to the clock period T of which the length on the time axis is the counter _CLK 。

For example, the analog-to-digital conversion circuit may be suitable for multiplexing, and when multiplexing is required, the counter and the differential ramp signal generator may be shared, where each path corresponds to a set of comparators (e.g., comparator a and comparator B) and a set of latches (e.g., latch a and latch B).

For example, if the analog-to-digital conversion circuit corresponds to K target pixels, where K is a positive integer, the analog-to-digital conversion circuit may include one counter that corresponds to K target pixels in common and one ramp signal generator that corresponds to K target pixels in common (the one ramp signal generator may be a differential ramp signal generator, or the one ramp signal generator may be a first sub-generator and a second sub-generator). The analog-to-digital conversion circuit can comprise K target pixels (K paths of voltage signals V _IN ) One-to-oneThe analog-to-digital conversion circuit can comprise K latches A corresponding to the K target pixels one by one and K latches B corresponding to the K target pixels one by one.

Based on this, K-way voltage signal V _IN Can correspond to the same counter, K paths of voltage signals V _IN May correspond to the same ramp signal generator. For each voltage signal V _IN The voltage signal V _IN One comparator a, one comparator B, one latch a, and one latch B may be corresponded.

Obviously, the counter can output the count value to the K-way voltage signal V simultaneously in each clock period _IN K latches A respectively corresponding to the voltage signals and simultaneously outputting the counted values to K paths of voltage signals V _IN And K latches B respectively corresponding to the two latches.

The ramp signal generator may generate the first ramp signal V at each clock cycle _{RAMP_P} Output to K paths of voltage signals V _IN K comparators A respectively corresponding to the first and second ramp signals V _{RAMP_N} Output to K paths of voltage signals V _IN And K comparators B respectively corresponding to the two comparators. Alternatively, the ramp signal generator may compare the first ramp signal V _{RAMP_P} Continuously output to K paths of voltage signals V _IN K comparators A respectively corresponding to the first and second ramp signals V _{RAMP_N} Continuously output to K paths of voltage signals V _IN And K comparators B respectively corresponding to the two comparators.

For each comparator A, the voltage signal V of the comparator A can be based on _IN And a first ramp signal V _{RAMP_P} Comparing and outputting the comparison result to a latch A, and for each comparator B, can be based on the voltage signal V of the comparator B _IN And a second ramp signal V _{RAMP_N} The comparison is performed and the comparison result is output to the latch B.

For each latch a, a value based on the count value output by the counter and the comparison result (first ramp signal V _{RAMP_P} And voltage signal V _IN A first comparison result of (a) latches the voltage signal V _IN Is a first count value of (a). For each latchA counter B for outputting a counter value based on the counter output and the comparison result (second ramp signal V _{RAMP_N} And voltage signal V _IN Second comparison result of (a) latches the voltage signal V _IN Is a second count value of (a).

From the above, it can be seen that if the analog-to-digital conversion circuit and the K-path voltage signal V _IN Correspondingly, i.e. the analog-to-digital conversion circuit corresponds to K target pixels, K may be a positive integer, e.g. a positive integer greater than 1, and the analog-to-digital conversion circuit may include a ramp signal generator, a counter, K comparators A, K comparators B, K latches a and K latches B. A ramp signal generator for outputting a first ramp signal to the K-way voltage signal V _IN K comparators A respectively corresponding to the voltage signals and outputting second ramp signals to the K paths of voltage signals V _IN And K comparators B respectively corresponding to the two comparators. A counter for outputting the count value to the K-path voltage signal V _IN K latches A respectively corresponding to the voltage signal V and outputting the counted value to the K paths of voltage signals _IN And K latches B respectively corresponding to the two latches.

By K-way voltage signal V _IN The same counter and ramp signal generator are shared, so that the area and the power consumption of the analog-to-digital conversion circuit can be saved, and the analog-to-digital conversion circuit has great advantages compared with other types of analog-to-digital conversion circuits. For the analog-to-digital conversion circuit of N-bit resolution shown in FIG. 4, at least 2 is required to complete one analog conversion ^N With a clock period, i.e. counter generation 2 ^N A count value, a ramp signal generator generates 2 ^N Ramp signals V _RAMP Based on 2 ^N Sum of count values 2 ^N Ramp signals V _RAMP And finishing analog-to-digital conversion.

In one possible implementation, the analog-to-digital conversion circuit may be applied to any device that needs analog-to-digital conversion, for example, the analog-to-digital conversion circuit may be applied to a readout circuit of an image sensor, and the analog-to-digital conversion circuit may be applied to a readout circuit of an infrared array, which is not limited to the application scenario of the analog-to-digital conversion circuit.

Wherein, when the analog-to-digital conversion circuit is applied to the readout circuit of the image sensor, the voltage signal V _IN May be of an image sensorVoltage signal V associated with a target pixel _IN (e.g. voltage signal directly output by target pixels or voltage signal processed by other circuits after output by target pixels), i.e. each target pixel of image sensor is associated with a voltage signal V _IN The analog-to-digital conversion circuit is used for determining a voltage signal V associated with each target pixel _IN The corresponding first count value and second count value are used to determine the voltage response value of the target pixel, where the voltage response value is used to determine the pixel value of the target pixel in the image, and the process of determining the pixel value based on the voltage response value is not limited in this embodiment.

When the analog-to-digital conversion circuit is applied to the read-out circuit of the infrared array, the voltage signal V _IN Voltage signal V associated with a target picture element, which may be an infrared array _IN I.e. each target picture element of the infrared array is associated with a voltage signal V _IN The analog-to-digital conversion circuit is used for determining a voltage signal V associated with each target pixel _IN The first count value and the second count value are used for determining a voltage response value of the target pixel, the voltage response value is used for determining a temperature value of the target pixel, the temperature value can be reflected to the infrared image, and the process of determining the temperature value based on the voltage response value is not limited in the embodiment.

Of course, the above is only two examples of application scenarios of the analog-to-digital conversion circuit, and this is not a limitation.

In one possible implementation, if the analog-to-digital conversion circuit is applied to the readout circuit of the image sensor, the readout circuit may include a plurality of rows and a plurality of columns of pixels, and when the K target pixels correspond to the same counter and the K target pixels correspond to the same ramp signal generator, the K target pixels corresponding to the analog-to-digital conversion circuit may be all pixels or part of pixels in the same row of the readout circuit, or the K target pixels corresponding to the analog-to-digital conversion circuit may be all pixels or part of pixels in the same column of the readout circuit.

For example, taking as an example all pixels of which K target pixels are the same column of the readout circuit, assuming that the readout circuit includes 100 rows and 50 columns of pixels, the readout circuit corresponds to 50 analog-to-digital conversion circuits, and the 50 analog-to-digital conversion circuits correspond to 50 columns of the readout circuit. The 1 st analog-to-digital conversion circuit corresponds to all pixels (i.e. 100 pixels) of the 1 st column, i.e. the analog-to-digital conversion circuit corresponds to 100 pixels (i.e. K target pixels) of the 1 st column, and the 100 pixels correspond to one counter, one ramp signal generator, 100 comparators a, 100 comparators B, 100 latches a and 100 latches B. The 2 nd analog-to-digital conversion circuit corresponds to all pixels (i.e., 100 pixels) of the 2 nd column, and so on.

Of course, the K target pixels corresponding to the analog-to-digital conversion circuit may be all pixels of a plurality of rows of the readout circuit, in addition to all pixels of the same row of the readout circuit. Or,

the K target pixels corresponding to the analog-to-digital conversion circuit may be all pixels of a plurality of columns of the readout circuit, besides all pixels of a same column of the readout circuit, for example, the K target pixels are all pixels of 2 columns of the readout circuit, all pixels of 4 columns, and the like, and the K target pixels are not limited.

In one possible implementation, if the analog-to-digital conversion circuit is applied to the readout circuit of the infrared array, the readout circuit may include a plurality of rows and a plurality of columns of pixels, and when the K target pixels correspond to the same counter and the K target pixels correspond to the same ramp signal generator, the K target pixels corresponding to the analog-to-digital conversion circuit may be all pixels or part of pixels in the same row of the readout circuit, or the K target pixels corresponding to the analog-to-digital conversion circuit may be all pixels or part of pixels in the same column of the readout circuit.

In one possible embodiment, the voltage response value of the target pixel, i.e., the voltage signal V, may be determined based on the first count value and the second count value _IN The corresponding voltage response value may, for example, be determined based on a difference between the first count value and the second count value, and the voltage response value of the target pel may be determined based on the target count value. For example, when the count value of the counter reaches the full valueAfter 1, the first count P and the second count Q may be subtracted to obtain a target count DOUT, e.g., dout=p-Q, which is used to determine the voltage signal V _IN Corresponding voltage response values.

Assume that the delay from the falling edge of the reset signal RST to the start of counting by the counter is TD _{cnt_start} The delay of the counter output to latch a input is TD _{cnt_out_p} The delay of the counter output to the latch B input is TD _{cnt_ont_n} The delay from the falling edge of the reset signal RST to the ramp starting point of the ramp signal generator is TD _ramp The conversion delay of the comparator A is TD _{comp_p} (V _IN ) The switching delay of comparator B is TD _{comp_n} (V _IN )。

As can be seen from the timing of FIG. 5, T can be determined using equation (6) and equation (7) _{OUT_P} And T _{OUT_N} ，T _{OUT_P} Representing the corresponding time length of the first P count values, wherein the count value P is that the first ramp signal is greater than or equal to the voltage signal V _IN Count value corresponding to time T _{OUT_N} Representing the corresponding time length of the first Q count values, wherein the count value Q is that the second ramp signal is smaller than or equal to the voltage signal V _IN A corresponding count value.

For the count value P latched by the latch a, the count value P is determined using the following formula:for the count value Q latched by the latch B, the count value Q may be determined using the following formula: />

At the counterAfter subtraction of the value P and the value Q, the target value D can be obtained _OUT For example, the target count value D may be determined using the following formula (8) _OUT ：

Considering that in the layout, latch A and latch B are placed close together, TD _{cnt_out_p} With TD _{cnt_out_n} Can be basically equal, and since the voltage signals VIN corresponding to the inversion moments of the comparator A and the comparator B are the same, TD _{comp_p} (V _IN ) And TD (time division) _{comp_n} (V _IN ) May be substantially equal, and TD may be calculated by the above equation (8) _{cnt_start} 、TD _{cnt_out_p} 、TD _{cnt_out_n} 、TD _ramp 、TD _{comp_p} (V _IN )、TD _{comp_n} (V _IN ) Subtracting from each other, and taking equation (6) and equation (7) into equation (8), equation (9) can be used to determine D _OUT ，D _OUT Represented is a target count value for determining a voltage response value.

Then, the equation (9) may be modified to obtain the equation (10) to determine the voltage response value.

In the formulas (6), (7), (8), (9) and (10), N represents conversion accuracy of the analog-to-digital conversion circuit for controlling the number of clock cycles, e.g., at least 2 are required for completing one analog conversion ^N Cycle of clock, 2 ^N Representing the number of clock cycles. T (T) _CLK Representing the length of one clock cycle. V (V) _IN Representing voltage signal, V _{REF_L} Representing the minimum voltage value, V _{REF_H} Representing the maximum voltage value. P represents that the first ramp signal is greater than or equal to the voltage signal V _IN The corresponding count value P is the count value latched by the latch a. Q represents that the second ramp signal is less than or equal to the voltage signal V _IN The corresponding count value Q is the count value latched by the latch B. D (D) _oUT Representing a target count value.

Obviously, based on the formula (10), D _OUT 、N、V _{REF_L} 、V _{REF_H} All are known values, and V can be obtained by substituting the values into the formula (10) _IN And V is _IN The voltage response value to be solved. In the formula (10), the count value D _OUT Magnitude and input voltage signal V _IN Is a strict linear relationship.

As can be seen from the formula (10), the offset and nonlinear effects caused by the delay of each unit of the analog-to-digital conversion circuit are subtracted, offset errors caused by the asynchronous counting start time of the counter and the slope start point of the slope signal generator can be eliminated, nonlinear effects caused by the conversion delay of the comparator along with the change of the input voltage signal can be eliminated, and effects caused by the delay difference of the counter output to each latch can be eliminated.

As can be seen from the formula (10), when determining the voltage response value corresponding to the target pel based on the target count value, the voltage response value of the target pel may be determined based on the target count value, the conversion accuracy configured to control the number of clock cycles, the maximum voltage value, and the minimum voltage value. Of course, the formula (10) is merely an example, and the manner of determining the voltage response value is not limited, and the voltage response value may be related to parameters such as the target count value, the configured conversion accuracy, the maximum voltage value, and the minimum voltage value.

Exemplary, since the value of the first count value P ranges from 0 to 2 ^N -1, the value range of the second count value Q is 0-2 ^N -1, after subtracting the first count value P from the second count value Q, the subtracted target count value D _OUT The range becomes- (2) ^N -1)～2 ^N -1, realizing equivalent n+1bitThe resolution, namely the resolution is increased from N bit to N+1bit, so that the resolution of the analog-to-digital conversion circuit is improved. If the analog-to-digital conversion circuit supports the resolution of N bits, then the analog-to-digital conversion circuit only needs 2 ^N The conversion can be completed in 1 clock period, and the working frequency of the counter can be reduced to half of the original analog-digital conversion circuit under the same conversion time.

As can be seen from the above technical solutions, in the embodiments of the present application, an analog-to-digital conversion circuit is designed, which can generate a plurality of first ramp signals and a plurality of second ramp signals, latch a first count value based on a first comparison result of a voltage signal associated with a target pixel and the plurality of first ramp signals, latch a second count value based on a second comparison result of the voltage signal associated with the target pixel and the plurality of second ramp signals, and determine a voltage response value of the target pixel based on the first count value and the second count value. When the analog-to-digital conversion circuit is used for converting the voltage signal into the digital signal, the two digital signals (namely the first count value and the second count value) are obtained, and the error of the digital signal is eliminated or reduced through the difference value of the two digital signals, so that the voltage value (namely the voltage response value) of the voltage signal can be accurately obtained, namely the error of the voltage response value is smaller. The offset error and nonlinear influence can be reduced or avoided, and the conversion rate of the analog-to-digital conversion circuit is improved.

The counter counting starting time and the asynchronous starting point of the slope signal generator, the transmission delay from the output of the counter to the input of the latch, the offset error and nonlinear influence caused by the conversion delay of the comparator and the like can be compensated, and the working frequency of the counter is reduced under the condition of the same bit resolution and conversion rate.

Based on the same application concept as the analog-to-digital conversion circuit, another analog-to-digital conversion circuit is provided in the embodiment of the present application, and the analog-to-digital conversion circuit includes a ramp signal generator, a first comparator, a second comparator, a first latch and a second latch. Wherein: a ramp signal generator for outputting a plurality of first ramp signals to the first comparator and outputting a plurality of second ramp signals to the second comparator; the slopes corresponding to the first slope signals and the slopes corresponding to the second slope signals are opposite. The first comparator is used for comparing the voltage signal related to the target pixel with the first slope signal and outputting a first comparison result to the first latch; and the second comparator is used for comparing the voltage signal related to the target pixel with the second ramp signal and outputting a second comparison result to the second latch. A first latch for latching the first count value based on the first comparison result; a second latch for latching a second count value based on a second comparison result; the first count value and the second count value are used for determining a voltage response value of the target pixel.

The first ramp signals are generated based on a first slope, and the first slope is positive; the initial values of the plurality of second ramp signals are maximum voltage values, the plurality of second ramp signals are generated based on second slopes, the second slopes are negative, and the absolute values of the second slopes are the same as the first slopes, namely the second slopes and the first slopes are opposite numbers.

The ramp signal generator is a differential ramp signal generator for generating a plurality of first ramp signals based on a first slope and a plurality of second ramp signals based on a second slope; alternatively, the ramp signal generator includes a first sub-generator for generating a plurality of first ramp signals based on a first slope, and a second sub-generator for generating a plurality of second ramp signals based on a second slope.

For example, for each first ramp signal, if the first ramp signal is smaller than the voltage signal, the first comparison result is a first level, and if the first ramp signal is larger than the voltage signal, the first comparison result is a second level; and a first latch for latching the current count value as a first count value when the first comparison result is detected to be switched from the first level to the second level.

For example, for each second ramp signal, if the second ramp signal is greater than the voltage signal, the second comparison result is a third level, and if the second ramp signal is less than the voltage signal, the second comparison result is a fourth level; and a second latch for latching the current count value as a second count value when the second comparison result is detected to be switched from the third level to the fourth level.

The analog-to-digital conversion circuit may further include a counter for accumulating a count value every one clock period (i.e., every time the count value is the last count value plus 1) after receiving the reset signal, and outputting the currently accumulated count value to the first latch and the second latch.

For example, the first level may be a high level, the second level may be a low level, or the first level may be a low level, and the second level may be a high level. The third level may be a high level, the fourth level may be a low level, or the third level may be a low level and the fourth level may be a high level.

For example, if the analog-to-digital conversion circuit corresponds to K target pixels, where K is a positive integer, the analog-to-digital conversion circuit includes one ramp signal generator that K target pixels commonly correspond to, one counter that K target pixels commonly correspond to, K first comparators that K target pixels one-to-one correspond to, K second comparators that K target pixels one-to-one correspond to, K first latches that K target pixels one-to-one correspond to, and K second latches that K target pixels one-to-one correspond to; wherein: the slope signal generator is used for outputting a first slope signal to K first comparators corresponding to the K target pixels respectively, and outputting a second slope signal to K second comparators corresponding to the K target pixels respectively;

And the counter is used for outputting the count value to K first latches corresponding to the K target pixels respectively, and outputting the count value to K second latches corresponding to the K target pixels respectively.

Illustratively, if the analog-to-digital conversion circuit is applied to a readout circuit of an image sensor, and the readout circuit includes a plurality of rows and columns of picture elements, then: the K target pixels corresponding to the analog-to-digital conversion circuit are all pixels or part of pixels in the same row of the readout circuit, or the K target pixels corresponding to the analog-to-digital conversion circuit are all pixels or part of pixels in the same column of the readout circuit.

Illustratively, the process of determining the voltage response value of the target pel based on the first count value and the second count value may include, but is not limited to: determining a target count value based on a difference between the first count value and the second count value; and determining a voltage response value of the target pixel based on the target count value.

In one possible implementation, determining the voltage response value of the target pel based on the target count value may include, but is not limited to: the voltage response value of the target pel is determined based on the target count value, the conversion accuracy configured to control the number of clock cycles, the maximum voltage value, and the minimum voltage value.

In one possible implementation, determining the voltage response value of the target pel based on the target count value may include, but is not limited to: the voltage response value of the target pixel is determined by adopting the following formula:

wherein D is _OUT Represents a target count value, N represents conversion accuracy, 2 ^N Representing the number of clock cycles, V _{REF_H} Represents the maximum voltage value, V _{REF_L} Representing the minimum voltage value, V _IN Representing the voltage response value.

The foregoing is merely exemplary of the present application and is not intended to limit the present application. Various modifications and variations of the present application will be apparent to those skilled in the art. Any modification, equivalent replacement, improvement, etc. which come within the spirit and principles of the application are to be included in the scope of the claims of the present application.

Claims

1. An analog-to-digital conversion circuit is characterized by comprising a ramp signal generator, a first comparator, a second comparator, a first latch and a second latch; wherein:

2. The analog-to-digital conversion circuit of claim 1, wherein,

the initial values of the plurality of first ramp signals are minimum voltage values, the plurality of first ramp signals are generated based on a first slope, and the first slope is positive; the start values of the plurality of second ramp signals are maximum voltage values, the plurality of second ramp signals are generated based on a second slope, the second slope is negative, and the absolute value of the second slope is the same as the first slope.

3. The analog-to-digital conversion circuit of claim 2, wherein said ramp signal generator is a differential ramp signal generator for generating a plurality of first ramp signals based on said first slope and a plurality of second ramp signals based on said second slope;

or, the ramp signal generator includes a first sub-generator for generating a plurality of first ramp signals based on the first slope and a second sub-generator for generating a plurality of second ramp signals based on the second slope.

4. The analog-to-digital conversion circuit of claim 1, wherein,

for each first ramp signal, if the first ramp signal is smaller than the voltage signal, the first comparison result is a first level, and if the first ramp signal is larger than the voltage signal, the first comparison result is a second level; the first latch is used for latching the current count value into the first count value when the first comparison result is detected to be switched from the first level to the second level;

for each second ramp signal, if the second ramp signal is greater than the voltage signal, the second comparison result is a third level, and if the second ramp signal is less than the voltage signal, the second comparison result is a fourth level; the second latch is configured to latch a current count value as the second count value when it is detected that the second comparison result is switched from the third level to the fourth level.

5. The analog-to-digital conversion circuit of claim 4, further comprising a counter for accumulating a count value every one clock cycle after receiving the reset signal, and outputting the currently accumulated count value to the first latch and the second latch.

6. The analog-to-digital conversion circuit of claim 1, wherein,

if the analog-to-digital conversion circuit corresponds to K target pixels, and the K is a positive integer, the analog-to-digital conversion circuit comprises a ramp signal generator, a counter, K first comparators, K second comparators, K first latches and K second latches, wherein the ramp signal generator corresponds to the K target pixels in a common mode, the counter corresponds to the K target pixels in a common mode, the K first comparators correspond to the K target pixels in a one-to-one mode, the K second comparators correspond to the K target pixels in a one-to-one mode, and the K first latches correspond to the K target pixels in a one-to-one mode;

wherein: the ramp signal generator is used for outputting a first ramp signal to K first comparators corresponding to the K target pixels respectively, and outputting a second ramp signal to K second comparators corresponding to the K target pixels respectively;

the counter is used for outputting a count value to K first latches corresponding to the K target pixels respectively, and outputting the count value to K second latches corresponding to the K target pixels respectively.

7. The analog-to-digital conversion circuit of claim 6, wherein,

if the analog-to-digital conversion circuit is applied to a readout circuit of an image sensor, the readout circuit comprises a plurality of rows and a plurality of columns of pixels, the K target pixels corresponding to the analog-to-digital conversion circuit are all pixels or part of pixels in the same row of the readout circuit, or the K target pixels corresponding to the analog-to-digital conversion circuit are all pixels or part of pixels in the same column of the readout circuit.

8. The analog-to-digital conversion circuit of claim 1, wherein the process of determining the voltage response value of the target pel based on the first count value and the second count value comprises:

determining a target count value based on a difference between the first count value and the second count value;

and determining a voltage response value of the target pixel based on the target count value.

9. The analog-to-digital conversion circuit of claim 8, wherein,

the determining the voltage response value of the target pixel based on the target count value includes:

and determining a voltage response value of the target pixel based on the target count value, the conversion accuracy configured to control the number of clock cycles, the maximum voltage value and the minimum voltage value.

10. An analog to digital conversion circuit according to claim 8 or 9, wherein,

the voltage response value of the target pixel is determined by adopting the following formula:

D _OUT represents the target count value, N represents conversion accuracy, 2 ^N Representing the number of clock cycles, V _{REF_H} Representing the maximum voltage value, V _{REF_L} Representing the minimum voltage value, V _IN Representing the voltage response value.