JP2017055382A - Imaging apparatus and imaging system - Google Patents

Abstract

PROBLEM TO BE SOLVED: To reduce the number of elements in an imaging apparatus having an AD conversion circuit in each row of a plurality of pixels and performing multiple AD conversions to an input pixel signal.SOLUTION: An imaging apparatus has a first memory group for holding a digital value obtained by performing first AD conversion to one and the same pixel signal and a second memory group for holding a digital value obtained by performing second AD conversion of the same pixel signal. The first memory group has a bit width of N+1 bits (N is a natural number) and holds bits from the least significant bit up to the (N+1)th bit out of the digital value obtained by the first AD conversion, and the second memory group has a bit width of M bits (M is a natural number) greater than N+1 bits and holds bits from the least significant bit up to the M-th bit out of the digital value obtained by the second AD conversion.SELECTED DRAWING: Figure 2

Description

  The present invention relates to an imaging apparatus and an imaging system.

  One type of circuit configuration of a CMOS image sensor includes an analog-digital (AD) conversion circuit provided corresponding to each column of a plurality of pixels. In relation to such a CMOS image sensor, Patent Document 1 discloses that when an imaging apparatus operates by performing AD conversion of a signal from a pixel a plurality of times and adding a digital value obtained by AD conversion. It is described that the generated thermal noise can be reduced.

  Patent Document 2 discloses an imaging apparatus in which a counter outputs a count value to a storage unit in each column via a buffer. The storage means of each column of the imaging apparatus holds the count value at the timing when the magnitude relationship between the potential of the pixel signal and the potential of the ramp signal is reversed.

JP 2010-103913 A JP 2013-93837 A

  However, in the configuration of Patent Document 2, when AD conversion is performed a plurality of times on the input pixel signal, it is necessary to add storage means for holding each AD conversion result, and thus the number of elements is large. Can be.

  The present invention has been made in view of the above-described problems. In an imaging apparatus that includes an AD conversion circuit in each column of a plurality of pixels and performs AD conversion multiple times on an input pixel signal, the number of elements is It aims at reducing.

  An imaging apparatus according to an aspect of the present invention includes a plurality of pixels that are arranged to form a plurality of columns and that output pixel signals corresponding to incident light by photoelectric conversion, and the pixel signals are AD-converted for each column. An image pickup apparatus that obtains a digital value and is provided corresponding to each of the plurality of columns and holds the digital value obtained by performing a first AD conversion on the same pixel signal And a second memory group that holds the digital value obtained by performing the second AD conversion, and the first memory group has a bit width of N + 1 bits (N is a natural number). The digital value obtained by the first AD conversion holds the least significant bit to the (N + 1) th bit, and the second memory group has M bits (M is a natural number) larger than the N + 1 bit. A width of the second A Characterized by holding the least significant bit of said digital values obtained by the conversion to the M bits.

  An imaging apparatus according to another aspect of the present invention corresponds to each of a plurality of pixels that are arranged in a plurality of columns and that output a pixel signal corresponding to incident light by photoelectric conversion. A comparator for comparing a magnitude relationship between the pixel signal and a reference signal that changes according to time, and that outputs a control signal in response to the magnitude relationship being inverted, and a change in the reference signal A counter that outputs a count value indicating an elapsed time since the start of the first memory, and a first memory group that is provided corresponding to each of the plurality of columns and holds the count value at the time when the control signal is output And the second memory group, and the comparator performs the plurality of comparisons including the first comparison and the second comparison on the same pixel signal, and the first memory group and The second memory group is used for the first comparison. The count value obtained by the second comparison and the count value obtained by the second comparison are respectively held, and the first memory group has a bit width of N + 1 bits (N is a natural number), and The least significant bit to the (N + 1) th bit of the count value obtained by the comparison are held, and the second memory group has a bit width of M bits (M is a natural number) larger than the N + 1 bit, The least significant bit to the Mth bit of the count value obtained by the comparison of 2 are held.

  In an imaging device that includes an AD conversion circuit in each column of a plurality of pixels and performs AD conversion a plurality of times on an input pixel signal, the number of elements can be reduced.

FIG. 2A is a block diagram illustrating a configuration of an imaging apparatus according to the first embodiment. (B) is a circuit diagram showing a configuration of a pixel. FIG. 3A is a block diagram illustrating in more detail the configurations of a first memory group and a second memory group according to the first embodiment. (B) is a block diagram showing the configuration of the memory in more detail. FIG. 4A is a timing diagram illustrating an operation of the imaging apparatus according to the first embodiment. (B) is a timing chart showing a count signal. (C) is a timing chart showing a modification of the count signal. It is a figure explaining the processing method of the digital value which concerns on 1st Embodiment. It is a block diagram which shows the structure of the 1st memory group and 2nd memory group which concern on 2nd Embodiment in detail. (A) is a timing diagram showing the operation of the entire imaging apparatus according to the second embodiment. (B) is a timing chart showing count signals in periods N1 and N2. (C) is a timing chart showing count signals in periods S1 and S2. It is a block diagram which shows the structure of the imaging device which concerns on 3rd Embodiment. It is a block diagram which shows the structure of the 1st memory group and 2nd memory group which concern on 3rd Embodiment in detail. FIG. 10 is a timing diagram illustrating an operation of the imaging apparatus according to the third embodiment. (A) is a timing diagram which shows operation | movement of the imaging device which concerns on 4th Embodiment. (B) is a timing chart showing a count signal. It is a block diagram which shows the structure of the imaging system which concerns on 6th Embodiment. (A) is a block diagram showing the composition of the imaging device concerning a 5th embodiment. (B) is a circuit diagram showing a configuration of a pixel. It is a circuit diagram which shows the structure of the voltage generation circuit which concerns on 5th Embodiment. It is a block diagram which shows in more detail the structure of the 1st memory group and 2nd memory group which concern on 5th Embodiment.

[First Embodiment]
FIG. 1A and FIG. 1B show an imaging apparatus according to the first embodiment. FIG. 1A is a block diagram illustrating a configuration of an imaging apparatus, and FIG. 1B is a circuit diagram illustrating a configuration of a pixel.

  The imaging apparatus includes a pixel array 101, a vertical scanning circuit 102, a reference signal generation circuit 103, a plurality of comparators 104, a counter 105, a plurality of first memory groups 107, a plurality of second memory groups 108, a horizontal scanning circuit 109, and a plurality of The selection circuit 110 is provided. The pixel array 101 includes a plurality of pixels 100 arranged in a matrix including a plurality of rows and a plurality of columns. The comparator 104, the first memory group 107, the second memory group 108, and the selection circuit 110 are provided corresponding to each column of the pixel array 101.

  The pixel 100 includes a photoelectric conversion unit PD, a reset transistor M1, a transfer transistor M2, an amplification transistor M3, and a selection transistor M4. The photoelectric conversion unit PD generates charges according to incident light by photoelectric conversion. The photoelectric conversion unit PD is configured by, for example, a photodiode. The reset transistor M1, the transfer transistor M2, and the selection transistor M4 are controlled by control signals φR, φT, and φSEL supplied from the vertical scanning circuit 102, respectively. The photoelectric conversion unit PD is connected to the source of the transfer transistor M2, and the drain of the transfer transistor M2 is connected to the floating diffusion FD that is the gate node of the amplification transistor M3. By turning on the transfer transistor M2, the charge generated in the photoelectric conversion unit PD is transferred to the floating diffusion FD.

  The source of the reset transistor M1 is connected to the floating diffusion FD, and the drain of the reset transistor M1 is connected to a power supply line having a power supply voltage. By turning on the reset transistor M1, the voltage of the floating diffusion FD is reset. With such a configuration, the pixel 100 outputs a signal of a reset level corresponding to the state where the voltage of the floating diffusion FD is reset and an optical signal corresponding to the state after the charge is transferred to the floating diffusion FD after reset. Output is possible.

  The drain of the amplification transistor M3 is connected to the power supply line, and the source of the amplification transistor M3 is connected to the drain of the selection transistor M4. The source of the selection transistor M4 is connected to the output line of the pixel 100. The amplification transistor M3 can operate as a source follower by turning on the selection transistor M4 and connecting a current load (not shown). At this time, the amplification transistor M3 outputs a pixel signal VPIX corresponding to the charge transferred to the floating diffusion FD to the output line of the pixel 100. This output line is provided in common for each column of the pixel array 101 and is connected to the comparator 104.

  The vertical scanning circuit 102 outputs the control signals φR, φT, and φSEL described above to the pixels 100 in each row of the pixel array 101, and controls the operation of selecting and reading a predetermined row in the pixel array 101. The comparator 104 receives the pixel signal VPIX read from the pixel 100 and the reference signal VRMP generated by the reference signal generation circuit 103, and compares the magnitude relationship between the two. The comparator 104 outputs a control signal VCOMP indicating the comparison result to the selection circuit 110. When the magnitude relationship between the pixel signal VPIX and the reference signal VRMP is inverted, the polarity of the control signal VCOMP is inverted at that timing. The reference signal VRMP is a signal whose voltage changes with time. In the present embodiment, the reference signal VRMP is a ramp signal whose voltage changes linearly with respect to time, but is not limited thereto. For example, the reference signal VRMP may be a signal whose voltage changes stepwise with respect to time. The selection circuit 110 selects either the first memory group 107 or the second memory group 108 as an output destination of the control signal VCOMP.

  The counter 105 outputs a count signal group 106 including, for example, an 11-bit gray code signal via a plurality of signal lines. A plurality of signal lines from which the count signal group 106 is output from the counter 105 are commonly connected to the first memory group 107 and the second memory group 108 in each column. The value (count value) indicated by the count signal group 106 corresponds to the elapsed time since the change of the reference signal VRMP started. The first memory group 107 and the second memory group 108 hold the count value as a digital value that is an AD conversion result at the time when the polarity of the control signal VCOMP is inverted. The digital values held in the first memory group 107 and the second memory group 108 are sequentially transmitted to the subsequent circuit of the imaging device via the output line 114 at the timing when the scanning control signal is input from the horizontal scanning circuit 109. Is output. In the present embodiment, the first memory group 107 and the second memory group 108 are provided in the imaging apparatus as memory groups that hold the AD conversion results. Therefore, the imaging apparatus can perform AD conversion twice and hold the AD conversion results for two times. Although specific processing will be described later, in the present embodiment, these two AD conversion results can be added to reduce noise in the output signal.

  FIGS. 2A and 2B correspond to one column of the pixel array 101 in order to explain the configuration of the first memory group 107 and the second memory group 108 of the first embodiment in more detail. It is a figure which shows the structure of the column circuit to perform. (A) is a block diagram showing in more detail the configuration of the first memory group and the second memory group according to the first embodiment, and (b) is included in the first memory group and the second memory group. It is a block diagram which shows the structure of a memory in detail.

  The counter 105 outputs a count signal group 106 including 12 count signals via a total of 12 signal lines. The count signals transmitted through the signal lines are referred to as count signals 106-0 to 106-10 and 106-3M. The count signals 106-0 to 106-10 constitute an 11-bit gray code signal in which the count signal 106-0 is the least significant bit and the count signal 106-10 is the most significant bit. The count signals 106-0, 106-1, 106-2, and 106-3M constitute a 4-bit gray code signal having 106-0 as the least significant bit and 106-3M as the most significant bit.

  The first memory group 107 includes 4-bit memories 107-0 to 107-3. Count signals 106-0, 106-1, 106-2, and 106-3M are input to the memories 107-0 to 107-3, respectively. The second memory group 108 includes 11-bit memories 108-0 to 108-10. Count signals 106-0 to 106-10 are input to the memories 108-0 to 108-10, respectively.

  FIG. 2B shows a configuration example of the memories 107-0 to 107-3 and 108-0 to 108-10. As a representative of these memories, only the configuration of the memory 108-0 will be described, but other memories may have the same configuration. The memory 108-0 of the present embodiment has a configuration capable of holding two pieces of data in order to perform digital CDS (Correlated Double Sampling) processing in the video signal processing unit in the imaging apparatus or at the subsequent stage of the imaging apparatus. . The memory 108-0 includes an N latch 200-N that holds an AD conversion result of a reset level signal and an S latch 200-S that holds an AD conversion result of an optical signal. Here, the number of memories included in the first memory group 107, that is, the bit width of the first memory group 107 is the difference value of the AD conversion result of each time when the AD conversion is performed a plurality of times on the same signal. Specify a value larger than the maximum value. This difference value is mainly caused by a random noise component superimposed on the pixel signal VPIX and the reference signal VRMP and a random noise component generated by the comparator 104. As a result, a plurality of bit values whose values can vary between the two AD conversion results can be held.

For example, when the absolute value of the difference value between the first and second AD conversion results is 2 ^N −1 [LSB] or less, the bit width required for the first memory group 107 is N + 1 bits. In the present embodiment, it is assumed that N = 3, that is, the absolute value of the difference value is 7 [LSB] or less, whereby the bit width of the first memory group 107 is set to 4 bits. This is because the upper 7 bits (= 11 bits−4 bits) of each AD conversion result have the same value in the first AD conversion and the second AD conversion, so the bit width of the first memory group 107 is at least 4 This is because a bit is sufficient.

  Next, the operation of the imaging apparatus according to the present embodiment will be described with reference to the timing charts of FIGS. 3A, 3B, and 3C. FIG. 3A is a timing diagram illustrating the operation of the entire imaging apparatus according to the first embodiment. FIG. 3B is a timing chart showing the count signal. FIG. 3C is a timing chart showing a modified example of the count signal.

  First, in the period from time T0 to time T1, the control signal φR becomes high level and the reset transistor M1 is turned on. As a result, the voltage of the floating diffusion FD is reset to a predetermined voltage level. Thereafter, in a period N1 from time T2 to time T3 and a period N2 from time T4 to time T5, AD conversion is performed twice on the pixel signal VPIX at the reset level.

  First, the first AD conversion in the period N1 will be described. In the period N1, the selection circuit 110 selects the first memory group 107 as the output destination of the control signal VCOMP. At time T2, the voltage of the reference signal VRMP output from the reference signal generation circuit 103 starts to decrease. At the same time, the count value indicated by the count signal group 106 output from the counter 105 starts to increase with time. At this time, since the voltage of the reference signal VRMP is larger than the voltage of the pixel signal VPIX at the reset level, the control signal VCOMP that is the output of the comparator 104 is at the high level.

  Thereafter, at time T2A when the voltage of the reference signal VRMP becomes smaller than the voltage of the pixel signal VPIX at the reset level, the magnitude relationship between the voltage of the reference signal VRMP and the voltage of the pixel signal VPIX at the reset level is inverted, and the control signal VCOMP Goes low. The first memory group 107 holds the count value indicated by the count signal group 106 at the time T2A as a digital value of the reset level after AD conversion. The first memory group 107 includes four memories 107-0 to 107-3. In other words, since the first memory group 107 has a bit width of 4 bits, the digital value held in the first memory group 107 in the period N1 is the second least significant bit of the count value indicated by the count signal group 106. Only the lower 4 bits up to the 4th bit.

  After that, second AD conversion is performed in the period N2. In the period N2, the selection circuit 110 selects the second memory group 108 as an output destination of the control signal VCOMP. AD conversion similar to that described above is performed, and at time T4A, the second memory group 108 holds the count value indicated by the count signal group 106 at the time T4A as a digital value of the reset level after AD conversion. The second memory group 108 includes eleven memories 108-0 to 108-10. In other words, since the second memory group 108 has a bit width of 11 bits, the digital value held in the second memory group 108 in the period N2 is the 11th bit from the least significant bit of the count value indicated by the count signal group 106. Until the eyes. Note that digital values obtained by AD conversion in the periods N1 and N2 are held in the N latch 200-N of each memory. The waveform of the reference signal VRMP used for the second AD conversion in the period N2 is the same as the waveform of the reference signal VRMP used for the first AD conversion in the period N1.

  Thereafter, in the period from time T6 to time T7, the control signal φT becomes high level, and the transfer transistor M2 is turned on. Thereby, the electric charge which generate | occur | produced in photoelectric conversion part PD with incident light is transferred to floating diffusion FD. Along with this charge transfer, the voltage of the pixel signal VPIX decreases. At time T7, the voltage of the pixel signal VPIX becomes a value corresponding to the optical signal by charge transfer. Thereafter, in a period S1 from time T8 to time T9 and a period S2 from time T10 to time T11, AD conversion is performed twice on the pixel signal VPIX at the level of the optical signal.

  The AD conversion operation in the periods S1 and S2 is the same as the AD conversion operation in the periods N1 and N2 except that the digital value is held in the S latch 200-S of each memory, and thus description thereof is omitted.

  Next, the operation timing of the count signal group 106 will be described with reference to FIG. FIG. 3B shows waveforms of the count signals 106-0 to 106-5 of the lower 6 bits of the count signal group 106 and the count signal 106-3M in the period S1 and the period S2.

  At time T8, which is the start time of the period S1, the count signals 106-0 to 106-2 and 106-3M indicate “0000” as the gray code value (“0” in decimal). After time T8, the value increases as time elapses. When the gray code value becomes “1000” (decimal number “15”), the value then returns to “0000” again. The count signals 106-3 to 106-10 are always at a low level (0). Thus, in the period S1, the 4-bit gray code signal composed of the count signals 106-0 to 106-2 and 106-3M repeats counting from 0 to 15. Therefore, at time T8A when the level of the control signal VCOMP is inverted, one of the count values from 0 to 15 is held in gray code in the S latch 200-S of the first memory group 107.

  At time T10, which is the start time of the period S2, the count signals 106-0 to 106-10 indicate “0... 0000” (“0” in decimal) as the gray code value. After time T10, the value indicated by the count signals 106-0 to 106-10 increases with the passage of time. Thus, in the period S2, counting is performed with an 11-bit gray code composed of the count signals 106-0 to 106-10. Therefore, at time T10A when the level of the control signal VCOMP is inverted, the count value is held in the 11-bit gray code in the S latch 200-S of the second memory group 108.

  Thus, in the present embodiment, AD conversion is performed twice in the two periods S1 and S2. The count value held in the period S2 is 11 bits, that is, all the bits of the count signal group 106, and the count value held in the period S1 is the lower 4 bits of the count signal group 106. By using the digital values obtained in the periods S1 and S2 in this way and adding or averaging the results of performing AD conversion twice, noise included in the AD conversion results can be reduced.

  Note that in the count signal in FIG. 3B, the count signal output in the period S1 is different from the count signal output in the period S2. In particular, in the period S1, the count signals 106-3 to 106-10 that are not related to the AD conversion operation are always at a low level. As a result, the power consumption is reduced as compared with the case where the level of the count signals 106-3 to 106-10 is also changed in the period S1. However, as in the modified example of the count signal shown in FIG. 3C, the count signals in the periods S1 and S2 may have the same operation timing. In other words, the count value output from the counter 105 during the first AD conversion may be the same as the count value output from the counter 105 during the second AD conversion. In this case, the operation of the counter 105 is simplified.

  Next, a processing method for obtaining a signal corresponding to a result obtained by adding two AD conversion results using the digital values held in the first memory group 107 and the second memory group 108 will be described with reference to FIG. I will explain. As described above, the digital values held in each memory group are the lower 4-bit digital value held in the period S1 and the total 11-bit digital value held in the period S2. Therefore, even if these are simply added, the desired value is not obtained, and the arithmetic processing described below is required. Note that the arithmetic processing for these digital values is performed after conversion from gray code to binary code.

Here, it is assumed that the lower 4 bits held in the period S1 are S1 (Lo). Further, all the bits held in the period S2 are S2 (ALL), the lower 4 bits are S2 (Lo), and the upper 7 bits are S2 (Hi). Further, in this embodiment, the upper 7 bits are not held in the digital value held in the period S1, but if all 11 bits exist in this digital value, the value is S1 (ALL), and the upper 7 bits are S1 ( Hi). However, since the high-order bits of the digital value after AD conversion performed a plurality of times as described above are assumed to be the same value, the following equation is established.
S1 (Hi) = S2 (Hi)

The purpose of this processing is to obtain S1 (ALL) + S2 (ALL), which is the sum of two AD conversion results, using the digital values held in the first memory group 107 and the second memory group 108. . The known values held in each memory group are S1 (Lo) and S2 (ALL). From this point of view, S1 (ALL) + S2 (ALL) is transformed as follows.
S1 (ALL) + S2 (ALL)
= S1 (Hi) + S1 (Lo) + S2 (Hi) + S2 (Lo)
= 2 × S2 (Hi) + S2 (Lo) + S1 (Lo)
= 2 * {S2 (Hi) + S2 (Lo)} + S1 (Lo) -S2 (Lo)
= 2 × S2 (ALL) + diff
Here, diff = S1 (Lo) −S2 (Lo).

  That is, by adding twice the value S2 (ALL), which is the value held in the second memory group 108, and the difference value diff (4-bit value), S1 (the sum of two AD conversion results) ALL) + S2 (ALL) can be calculated.

However, since the possible values of S1 (Lo) and S2 (Lo) are 0 to 15, if the difference value diff of the above expression is applied as it is, an error due to carry-up or carry-down from the lower bits to the higher bits may occur. . Therefore, depending on the combination of S1 (Lo) and S2 (Lo) with respect to the difference value diff, it may be necessary to carry out carry-up or carry-down digit processing. The contents of the digit processing are determined by the value of S1 (Lo) -S2 (Lo) as follows.
(Case 1) −8 <S1 (Lo) −S2 (Lo) <8 ⇒ No digit processing (diff = S1 (Lo) −S2 (Lo))
(Case2) When S1 (Lo) −S2 (Lo) ≦ −8 ⇒ Digit processing (diff = S1 (Lo) −S2 (Lo) +2 ⁴ )
(Case3) 8 ≦ S1 (Lo ) -S2 Yes ⇒ digit processing case (Lo) (diff = S1 ( Lo) -S2 (Lo) and - ²⁴⁾

Hereinafter, the contents of the digit processing will be described with reference to FIG.
When (Case1) -8 <S1 (Lo) -S2 (Lo) <8 Bin [0] to Bin [3] are the lower 4 bits of the waveform for each bit after binary conversion of S1 or S2. Show. The S2 (ALL) line shows an example of values that can be taken by Bin [0] to Bin [3].

  Hereinafter, in this case, a case where S2 (ALL) is “55” (binary value “110111”) will be described. The S2 (Lo) line indicates the lower 4 bits of value “7” (binary value “0111”) when S2 (ALL) is “55”. When S2 (ALL) is “55”, the possible range of S1 (ALL) is “55” ± 7 [LSB]. The S1 (Lo) row indicates “0” to “14” (binary values “0000” to “1110”) which are the lower 4 bits of S1 (ALL).

  The S1 (Lo) -S2 (Lo) row is a value obtained by subtracting S2 (Lo) from S1 (Lo), and the diff row shows the result after digit processing. Since digit processing does not occur in this case, the value is the same as that in the S1 (Lo) -S2 (Lo) line.

  The S1 + S2 (expected value) line indicates that when S2 (ALL) is “55”, the AD conversion result addition value S1 (ALL) + S2 (in the range that can be taken by S1 (ALL) (“55” ± 7 [LSB]) ALL) is an expected value.

The S1 + S2 (Simple) line shows the following expression, which is a calculated value obtained when the above digit processing is not performed.
2 × S2 (ALL) + S1 (Lo) −S2 (Lo)

The S1 + S2 line shows the following expression, which is a calculated value after digit processing.
2 x S2 (ALL) + diff

  Digit processing needs to be performed so that this value is equal to S1 + S2 (expected value). In this case, since −8 <S1 (Lo) −S2 (Lo) <8, there is no difference between S1 + S2 (Simple) and S1 + S2 (expected value) in the illustrated range of S1. Therefore, digit processing is not necessary in this case.

(Case 2) S1 (Lo) −S2 (Lo) ≦ −8 In this case, S2 (ALL) is “63” (binary value “111111”), and S2 (Lo) is “15” (binary). In this case, the value is “1111”).

Here, for example, consider the case where S1 (ALL) is “64” (binary value “1000000”) which is “1” larger than S2 (ALL). At this time, the value S1 (Lo) actually held in the first memory group 107 is “0” (binary value “0000”), and when digit processing is not performed, the following equation is obtained.
S1 (Lo) -S2 (Lo) = 0-15 = -15

Therefore, the value of the S1 + S2 (Simple) row corresponding to the sum of the two AD conversion results when the digit processing is not performed is expressed by the following equation.
2 * S2 (ALL) + S1 (Lo) -S2 (Lo) = 63 * 2-15 = 111

  This result is different from “127” which is S1 + S2 (expected value). The reason is as follows. The lower 4 bits S2 (Lo) of the value “63” of S2 (ALL) is “15” (binary value “1111”). Here, S1 (ALL), which is the value of the lower bit of S1 (ALL) which is larger by “1” than “63” of S2 (ALL), is “0” instead of “16” which is the next value of “15”. Become. This is because the bit width of the lower bits is only 4 bits. Therefore, when digit processing is not performed, S1 + S2 (Simple) is a value shifted from S1 + S2 (expected value) by “16”.

Therefore, it is necessary to define diff as a carry-up digit process by the following equation in order to correct this value deviation “16”.
diff = S1 (Lo) −S2 (Lo) +2 ⁴

When S1 (ALL) + S2 (ALL) is calculated using this diff, the value of S1 (ALL) + S2 (ALL) after the carry-over process is expressed by the following equation.
2 × S2 (ALL) + diff = 2 × 63−15 + 16 = 127

  As a result, a result matching S1 + S2 (expected value) is obtained. The above example is a case where S1 (Lo) is “0”, but the same processing is required in the case of “1” to “6”. When S1 (Lo) is “8” to “15”, the above digit processing is not performed.

(Case 3) 8 ≦ S1 (Lo) −S2 (Lo) In this case, S2 (ALL) is “64” (binary value “1000000”), and S2 (Lo) is “0” (binary value). Is “0000”).

Here, for example, consider the case where S1 (ALL) is “63” (binary value “111111”) which is “1” smaller than S2 (ALL). At this time, the value S1 (Lo) actually held in the first memory group 107 is “15” (binary value “1111”), and when digit processing is not performed,
S1 (Lo) -S2 (Lo) = 15-0 = 15

Therefore, the value of the S1 + S2 (Simple) row corresponding to the sum of the two AD conversion results when the digit processing is not performed is expressed by the following equation.
2 * S2 (ALL) + S1 (Lo) -S2 (Lo) = 64 * 2 + 15 = 143

This result is different from “127” which is S1 + S2 (expected value). In this case, it is necessary to define diff by the following equation as a carry-down digit process, contrary to Case2.
diff = S1 (Lo) -S2 (Lo) -2 ⁴

When S1 (ALL) + S2 (ALL) is calculated using this diff, the value of S1 (ALL) + S2 (ALL) after the carry-down process is expressed by the following equation.
2 * S2 (ALL) + diff = 2 * 64 + 15-16 = 127

  As a result, a result matching S1 + S2 (expected value) is obtained. The above example is a case where S1 (Lo) is “15”, but the same processing needs to be performed in the case of “9” to “14”. Further, when S1 (Lo) is “0” to “7”, the above digit processing is not performed.

  The above description of the digit processing is for the AD conversion result of the optical signal, but the same processing can be performed for the AD conversion result of the pixel reset level. After the digit processing is completed, digital CDS processing can be performed to obtain image data from which noise included in the reset level is removed. Note that the digit processing method described above may be performed inside the imaging device as long as it is a subsequent stage of each memory group, or may be performed by a video signal processing unit or the like subsequent to the imaging apparatus.

  As described above, according to this embodiment, noise is reduced by performing multiple AD conversions on pixel signals output from the same pixel and adding the AD conversion results obtained thereby. be able to. In this addition, the bit width of the first memory group 107 is made smaller than the total number of bits of the signal according to the assumed noise. As a result, the number of memories in the first memory group 107 can be reduced as compared with the case where the number of bits of the signal is set equal to the total number of bits. For example, in the above example, the number is reduced from 11 to 4. Therefore, the number of elements of the imaging device can be reduced.

  In the above description, the count signal output from the counter 105 is a gray code, but may be in a format other than the gray code. For example, it may be a binary code using a normal binary number. However, since the gray code has only one bit to be inverted when the count value increases, the influence of the timing difference between the increase in the count value and the change in the comparator output is reduced. It is more preferable to apply.

In the above description, the bit width of the first memory group 107 is 4 bits, the bit width of the second memory group 108 is 11 bits, and the count value indicated by the count signal group 106 is 11 bits. It is not limited to. That is, the number of bits can be set to an arbitrary value without departing from the gist of the present invention. More specifically, it is generalized as follows. When the absolute value of the difference value between the first and second AD conversion results is 2 ^N −1 [LSB] (N is a natural number) or less, the bit width of the first memory group 107 is N + 1 bits. At this time, the bit width of the second memory group 108 and the number of bits of the count value indicated by the count signal group 106 are set to M bits (M is a natural number) larger than N + 1. In this case, the first memory group 107 holds from the least significant bit to the (N + 1) th bit of the count signal group 106. The second memory group 108 holds the least significant bit to the Mth bit of the count signal group 106.

In this case, the above digit processing can be generalized using N as follows.
(Case 1) − (2 ^N −1) <S1 (Lo) −S2 (Lo) <(2 ^N −1) ⇒ No digit processing (Case 2) S1 (Lo) −S2 (Lo) ≦ − (2 ^N -1) => Digit processing (diff = S1 (Lo) -S2 (Lo) +2 ^{N + 1} )
When (Case 3) (2 ^N −1) ≦ S1 (Lo) −S2 (Lo) ⇒ Digit processing (diff = S1 (Lo) −S2 (Lo) −2N ^{+ 1} )

  In the above description, the imaging apparatus is configured to perform AD conversion twice and hold the AD conversion results in two memory groups. However, the number of AD conversions and the number of memory groups are limited to two. Absent. For example, the AD conversion may be performed three or more times, and the AD conversion result may be held in three or more memory groups.

  In the above description, digital values obtained by a plurality of AD conversions are simply added. However, this addition may not be simple addition. For example, the above-described addition process may be replaced with an averaging process by dividing the added value by the number of added signals.

[Second Embodiment]
FIG. 5 is a diagram for explaining the configuration of the first memory group 107 and the second memory group 118 according to the second embodiment. In the present embodiment, the configuration of the imaging apparatus is the same as that of the first embodiment shown in FIG.

  The configuration of the first memory group 107 is the same as that of the first embodiment. The configuration of the second memory group 118 is different from the configuration of the second memory group 108 of the first embodiment in that the memories 108-4 to 108-10 are replaced with a 7-bit width ripple counter 118-4. That is, the second memory group 118 includes lower-order 4-bit memories 118-0 to 118-3 and a ripple counter 118-4. The same count signals 106-0, 106-1, 106-2, 106-3M as the first memory group 107 are input from the counter 105 to the memories 118-0 to 118-3. Further, the count signal 106-3M is input to the ripple counter 118-4 via the memory 118-3. The ripple counter 118-4 counts the falling edge of the count signal 106-3M. That is, when the count signal 106-3M changes from the high level to the low level, the value held in the ripple counter 118-4 increases or decreases. Here, the method for setting the bit width of the first memory group 107 is the same as that described in the first embodiment, and thus the description thereof is omitted.

  Next, the operation of the imaging apparatus according to the present embodiment will be described with reference to the timing charts of FIGS. 6 (a), 6 (b), and 6 (c). FIG. 6A is a timing chart showing the operation of the entire imaging apparatus according to the second embodiment. FIG. 6B is a timing chart showing count signals in the periods N1 and N2. FIG. 3C is a timing chart showing count signals in the periods S1 and S2. The operation timings of the control signals φR and φT, the reference signal VRMP, the pixel signal VPIX, and the control signal VCOMP shown in FIG. 6A are the same as those in the first embodiment, and the periods N1, N2, S1, and S2 The AD conversion is performed in the same manner as in the first embodiment. Therefore, the detailed description about these is abbreviate | omitted.

  Hereinafter, the operation of the ripple counter 118-4 in the periods N2 and S2, which is a difference from the first embodiment in the present embodiment, will be described. As shown in FIG. 6B, in the period N2, the ripple counter 118-4 counts down according to the falling edge of the count signal 106-3M. In other words, when the lower bit count value returns from 15 to 0, the count value held in the ripple counter 118-4 decreases by one. Thereafter, at time T4A, the polarity of the control signal VCOMP is inverted. At this time, the values of the count signals 106-0 to 106-2 and 106-3M at that time are held in the N latches 200-N in the memories 118-0 to 118-3 of the second memory group 118. Further, at this time, the change of the count signal 106-3M supplied to the ripple counter 118-4 is controlled to stop, and the ripple counter 118-4 is also at time T4A until AD conversion in the period S2 starts thereafter. The count value N (Hi) is held.

  As illustrated in FIG. 6C, in the period S2 subsequent to the above-described operation, the ripple counter 118-4 performs count-up according to the falling edge of the count signal 106-3M. In this operation, the initial value of the count value of the ripple counter 118-4 is the count value N (Hi) at time T4A. Thereafter, at time T10A, the polarity of the control signal VCOMP is inverted. At this time, the values of the count signals 106-0 to 106-2 and 106-3M at that time are held in the S latches 200-S in the memories 118-0 to 118-3 of the second memory group 118. Further, at this time, control is performed so that the change of the count signal 106-3M supplied to the ripple counter 118-4 stops.

  Here, since the count in the period S2 is performed using the count value N (Hi) at the time T4A as an initial value, the upper bit value held in the ripple counter 118-4 is the value after the digital CDS processing is performed. Value. In other words, the ripple counter 118-4 holds the upper bit value after the CDS processing corresponding to (S2 (Hi) −N2 (Hi)).

Next, a method for processing digital values held in each memory group will be described. As described above, the upper bits subjected to the digital CDS processing have already been obtained. Therefore, it is necessary to process only the lower bits. A difference value between lower bit values obtained by two AD conversions for the reset level is diff_N, and a difference value between lower bit values obtained by two AD conversions for the optical signal is diff_S. The digit processing described in the first embodiment is performed on the difference values diff_N and diff_S to obtain the difference values after digit processing. A signal after digital CDS can be obtained by calculating the following value using the obtained difference value and the value held in the ripple counter.
2 × (S2 (Hi) −N2 (Hi)) + (diff_S) − (diff_N)

Also in this embodiment, the same effect as that of the first embodiment can be obtained.
In the above description, the bit width of the first memory group 107 is 4 bits, and the bit width corresponding to the memories 118-0 to 118-3 of the second memory group 118 is also 4 bits. The bit width of the ripple counter 118-4 is 7 bits. However, the number of bits is not limited as in the first embodiment. That is, the number of bits can be set to an arbitrary value without departing from the gist of the present invention. More specifically, it is generalized as follows. When the absolute value of the difference value between the first and second AD conversion results is 2 ^N −1 [LSB] (N is a natural number) or less, the bit width of the first memory group 107 is N + 1 bits. At this time, the bit widths of the plurality of memories in the second memory group 118 are also set to N + 1 bits. The bit width of the ripple counter 118-4 in the second memory group 118 is M- (N + 1) bits (M is a natural number). In this case, the first memory group 107 and the plurality of memories in the second memory group 118 hold the least significant bit to the (N + 1) th bit of the count signal group 106. The second memory group 118 holds from the (N + 2) th bit to the Mth bit of the count signal group 106.

[Third Embodiment]
FIG. 7 is a diagram illustrating a configuration of an imaging apparatus according to the third embodiment. Unlike the imaging device of the first embodiment shown in FIG. 1, the imaging device of this embodiment has a first comparator 111 and a second comparator 112 instead of the comparator 104. In addition, the imaging apparatus according to the present embodiment includes a selection circuit 113 in front of the first comparator 111 and the second comparator 112 instead of the selection circuit 110. The reference signal VRMP is input to the first comparator 111 and the second comparator 112 via the selection circuit 113. A control signal VCOMP1 output as a comparison result from the first comparator 111 is input to the first memory group 107. The control signal VCOMP2 output as a comparison result from the second comparator 112 is input to the second memory group 108.

  FIG. 8 is a block diagram showing in more detail the configuration of the first memory group 107 and the second memory group 108 according to the third embodiment. The control signal VCOMP1 output from the first comparator 111 is input to each of the memories 107-0 to 107-3 in the first memory group 107. The control signal VCOMP2 output from the second comparator 112 is connected to the memories 108-0 to 108-10 in the second memory group 108. Since other configurations are the same as those of the first embodiment, description thereof is omitted.

  Next, with reference to the timing chart of FIG. 9, the operation of the present embodiment will be described, particularly regarding differences from the first embodiment. Note that the operation of the count signal group 106 is the same as that in FIG. 3B or FIG.

  The selection circuit 113 inputs the reference signal VRMP to the first comparator 111 during AD conversion in the periods N1 and S1. As a result, AD conversion is performed in the first comparator 111, and the digital value is held in the first memory group 107. The selection circuit 113 inputs the reference signal VRMP to the second comparator 112 during AD conversion in the periods N2 and S2. Thereby, AD conversion is performed in the second comparator 112, and the digital value is held in the second memory group 108. Since other processes are the same as those in the first embodiment, description thereof is omitted.

Also in this embodiment, the same effect as that of the first embodiment can be obtained.
In this embodiment, two comparators and memory groups corresponding to each column of the pixels 100 are provided. However, the number can be arbitrarily changed as long as it is plural, for example, three or more. There may be.

[Fourth Embodiment]
Next, a fourth embodiment will be described. FIG. 10A is a timing diagram illustrating an operation of the imaging apparatus according to the fourth embodiment. FIG. 10B is a timing chart showing the count signal. The configuration of the imaging apparatus of the present embodiment is the same as that shown in FIGS. In the present embodiment, AD conversion is performed by applying a predetermined input offset voltage Voff to the input terminal of the second comparator 112, thereby overlapping the AD conversion period of the period N1 and the AD conversion period of the period N2. This is different from the third embodiment. Similarly, the AD conversion period of the period S1 and the AD conversion period of the period S2 can be overlapped. As an example, the addition of the input offset voltage Voff can be realized by changing the voltage of the reference signal VRMP input to the second comparator 112. In FIG. 10A, the waveform obtained by adding the input offset voltage Voff to the reference signal VRMP input to the second comparator 112 is indicated by a broken line.

  The operation in the period up to T2 is the same as that in FIG. In a period N1 from time T2 to time T3, AD conversion of the reset level in the first comparator 111 is performed. In a period N2 from time T2 to time T4, the AD conversion at the reset level in the second comparator 112 is performed. Since the input offset voltage Voff is added to the reference signal VRMP input to the second comparator 112, the AD conversion range in the period N1 and the AD conversion range in the period N2 are matched, so that the period N2 is longer than the period N1. become longer.

  In the period from time T6 to time T7, the control signal φT becomes high level, and the transfer transistor M2 is turned on. Thereby, the electric charge which generate | occur | produced in photoelectric conversion part PD with incident light is transferred to floating diffusion FD.

  In a period S1 from time T8 to time T9, AD conversion of the optical signal in the first comparator 111 is performed. In a period S2 from time T8 to time T10, AD conversion of the optical signal in the second comparator 112 is performed. Similar to the above-described relationship between the period N1 and the period N2, the period S2 is longer than the period S1.

  An example of the AD conversion operation will be described together with a timing chart of the count signal group 106 in the periods S1 and S2 shown in FIG. As shown in FIG. 10B, during the periods S1 and S2, the count signals 106-0 to 106-10 and 106-3M both vary and are used for counting during AD conversion.

  At timing T8A when the magnitude relationship between the pixel signal VPIX and the reference signal VRMP (solid line) is inverted, the polarity of the control signal VCOMP1 output from the first comparator 111 is inverted. As a result, a 4-bit digital value composed of the count signals 106-0 to 106-2 and 106-3M is held in each S latch 200-S of the first memory group 107. Similarly, at the timing T8B when the magnitude relationship between the pixel signal VPIX and the reference signal VRMP (broken line) is inverted, the polarity of the control signal VCOMP2 output from the second comparator 112 is inverted. An 11-bit digital value composed of the count signals 106-0 to 106-10 is held in each S latch 200-S of the second memory group 108.

  The subsequent processing for the acquired digital value is the same as the processing described above except that the conversion result held in the period S2 requires subtraction of a value corresponding to the predetermined input offset voltage Voff. Omitted.

  In the first embodiment, the waveform of the reference signal VRMP used for the second AD conversion in the period N2 is the same as the waveform of the reference signal VRMP used for the first AD conversion in the period N1, and the period N1 And the period N2 are different periods. In contrast, in the present embodiment, the imaging apparatus includes a plurality of comparators, and performs AD conversion by applying a predetermined input offset voltage Voff to the input terminal of the second comparator 112. Therefore, according to this embodiment, in addition to obtaining the effects of the first embodiment, at least a part of the period N1 and the period N2 can be overlapped, and at least a part of the period S1 and the period S2 can be overlapped. You can also.

  In the present embodiment, the reference signal VRMP is described as being added with a voltage corresponding to the input offset voltage Voff. However, the input offset voltage Voff may be added to the pixel signal VPIX.

  As a modification of the above-described third or fourth embodiment, the reference signal generation circuit 103 is configured to be able to output two reference signals VRMP, and the first comparator without the two reference signals VRMP via the selection circuit 113 111 and the second comparator 112 may be input. In this case, at each AD conversion, the reference signal generation circuit 103 can individually control the waveforms of the two reference signals VRMP. Accordingly, the AD conversion period of the period N1 and the AD conversion period of the period N2 can be overlapped, and the AD conversion period of the period S1 and the AD conversion period of the period S2 can be overlapped. Further, each memory group of the third or fourth embodiment may have the same configuration as that of the second embodiment shown in FIG. 5, and the same operation is possible.

[Fifth Embodiment]
Next, a fifth embodiment will be described. FIG. 12A is a block diagram illustrating a configuration of an imaging apparatus according to the fifth embodiment, and FIG. 12B is a circuit diagram illustrating a configuration of the pixel 100. Unlike the imaging device illustrated in FIGS. 1 and 7, the imaging device according to the present embodiment illustrated in FIG. 12A includes a successive approximation AD conversion circuit 210 including a comparator 104, a control circuit 201, and a voltage generation circuit 202. The first memory group 207 and the second memory group 208 are provided for each column. Further, the image pickup apparatus of this embodiment is not provided with the reference signal generation circuit 103 and the counter 105. The configuration of the pixel 100 illustrated in FIG. 12B is the same as that in FIG.

  A pixel signal VPIX output from the pixel 100 is input to one input terminal of the comparator 104. Based on the control signal VCTRL output from the control circuit 201, the voltage generation circuit 202 outputs a voltage signal VDAC for a successive comparison operation that sequentially performs a binary search to the other input terminal of the comparator 104. Further, the voltage generation circuit 202 receives a reference voltage VREF from a voltage source (not shown). The comparator 104 sequentially compares the pixel signal VPIX and the voltage signal VDAC and outputs a signal indicating the comparison result to the control circuit 201. The control circuit 201 receives the signal from the comparator 104 and outputs a control signal VCTRL to the voltage generation circuit 202. In addition, the control circuit 201 outputs the comparison result obtained by the successive comparison to the selection circuit 110. The selection circuit 110 selects either the first memory group 207 or the second memory group 208 as an output destination of the digital value that is the comparison result.

  FIG. 13 is a circuit diagram showing a configuration of the voltage generation circuit 202. The voltage generation circuit 202 includes a plurality of capacitors cp0 to cp12 having a binary weight capacitance value, and a plurality of switches sw1 to sw12 connected in series to the plurality of capacitors cp1 to cp12, respectively. The binary weight is a set of weights (capacity values) forming a geometric sequence with a common ratio of 2. In the example of FIG. 13, the capacitors cp <b> 0 to 12 have capacitance values of 1C, 1C, 2C, 4C,.

  The voltage generation circuit 202 is a circuit that divides the input reference voltage VREF and outputs it as a voltage signal VDAC by switching each of the plurality of switches sw1 to sw12 based on the control signal VCTRL. One ends of the capacitors cp0 to cp12 are connected to the output terminal of the voltage generation circuit 202. The other end of the capacitor cp0 is connected to the ground potential GND. The other ends of the plurality of capacitors cp1 to cp12 are respectively connected to one ends of the corresponding plurality of switches sw1 to sw12. The other ends of the plurality of switches sw1 to sw12 are terminals that can be switched to be connected to either the reference voltage VREF or the ground potential GND based on the control signal VCTRL. That is, the plurality of switches sw1 to sw12 constitute a switch circuit that performs an operation of selecting one or more of the capacitors cp1 to cp12 or not selecting any of them.

  The reference voltage VREF is a constant voltage supplied from the outside of the successive approximation AD converter circuit 210 and has a voltage value higher than the ground potential GND. When the connection state of the plurality of switches sw1 to sw12 is switched, the reference voltage VREF or the ground potential GND is supplied to each of the plurality of capacitors cp1 to cp12. As a result, the combined capacitance value connected between the terminal to which the reference voltage VREF is input and the terminal to which the voltage signal VDAC is output changes, and the voltage of the voltage signal VDAC changes. In other words, the voltage generation circuit 202 is a digital-analog conversion circuit that changes the voltage of the voltage signal VDAC based on the control signal VCTRL that controls the switches sw1 to sw12. In the configuration of FIG. 13, since the number of switches sw1 to sw12 is 12, a 12-bit successive approximation operation can be realized.

  FIG. 14 is a diagram illustrating a configuration of column circuits corresponding to one column of the pixel array 101 in the first memory group 207 and the second memory group 208 of the fifth embodiment. The first memory group 207 has a plurality of memories 207-0 to 207-3 holding comparison results for 4 bits from the least significant bit, and the second memory group 208 is for 12 bits from the least significant bit to the most significant bit. A plurality of memories 208-0 to 208-11 holding comparison results are provided. Each memory has a configuration capable of holding two pieces of data as in FIG. The bit width of the first memory group 207 is based on the maximum value of the difference value of each AD conversion result when AD conversion is performed a plurality of times on the same signal, as in the first embodiment. Specify a large value. The difference value in this embodiment is mainly caused by the random noise component superimposed on the pixel signal VPIX and the voltage signal VDAC that is the output of the voltage generation circuit 202 and the random noise component generated by the comparator 104. As a result, a plurality of bit values whose values can vary between the two AD conversion results can be held.

  Next, the AD conversion operation will be described. Also in this embodiment, AD conversion is performed twice for each of the pixel reset level and the optical signal level, as in the other embodiments described so far. Each AD conversion operation is performed by the successive approximation operation by the successive approximation AD conversion circuit 210. The first AD conversion result of the reset level and the optical signal level is held in the first memory group 207 from the least significant 4 bits, and the second AD conversion result is stored in the second memory group 208 from the least significant 12 bits. All bits up to the bit are retained.

  After that, if the held AD conversion result is not a binary code, it is converted into a binary code, and if it is a binary code, a process for obtaining a signal corresponding to the result of adding the two AD conversion results is performed. . The contents of the process are the same as the processes after conversion to binary code among the contents described in the first embodiment, and thus detailed description thereof is omitted.

  As described above, according to the present embodiment, even in an imaging apparatus having a successive approximation AD conversion circuit, a plurality of AD conversions are performed on the pixel signal output from the same pixel, and thus obtained. By adding the AD conversion results, noise can be reduced.

[Sixth Embodiment]
FIG. 11 shows a configuration of an imaging system 800 according to the sixth embodiment. The imaging system 800 can include, for example, a digital still camera, a digital camcorder, a surveillance camera, and the like. The imaging system 800 includes an optical unit 810, an imaging device 10, a video signal processing unit 830, a recording / communication unit 840, a timing control unit 850, a system control unit 860, and a playback / display unit 870. As the imaging device 10, the imaging devices according to the first to fifth embodiments described above are used.

  An optical unit 810 that is an optical system such as a lens forms an image of a subject by forming light from the subject on a pixel array 101 in which a plurality of pixels 100 are two-dimensionally arranged. The imaging device 10 outputs a signal corresponding to the light imaged on the pixel array 101 at a timing based on the signal from the timing control unit 850. The signal output from the imaging device 10 is input to a video signal processing unit 830 that is a video signal processing unit, and the video signal processing unit 830 performs signal processing according to a method determined by a program or the like. Note that the signal processing performed by the video signal processing unit 830 may include the digital CDS, digit processing, and the like described in the first embodiment. The signal obtained by the processing in the video signal processing unit 830 is sent to the recording / communication unit 840 as image data. The recording / communication unit 840 sends a signal for forming an image to the reproduction / display unit 870 and causes the reproduction / display unit 870 to reproduce / display a moving image or a still image. Alternatively, an output signal from the video signal processing unit 830 may be directly sent to the reproduction / display unit 870 to reproduce / display a moving image or a still image. The recording / communication unit 840 receives a signal from the video signal processing unit 830 and communicates with the system control unit 860, and also records an operation for recording a signal for forming an image on a recording medium (not shown). Do.

  The system control unit 860 comprehensively controls the operation of the imaging system, and controls driving of the optical unit 810, the timing control unit 850, the recording / communication unit 840, and the reproduction / display unit 870. Further, the system control unit 860 includes a storage device (not shown) that is a recording medium, for example. Programs and the like necessary for controlling the operation of the imaging system are recorded in this storage device. Further, the system control unit 860 supplies a signal for switching the drive mode in accordance with, for example, a user operation in the imaging system. Specific examples include a change in a row to be read, a change in a row to be reset, a change in the angle of view associated with electronic zoom, and a shift in angle of view associated with electronic image stabilization. The timing control unit 850 controls the drive timing of the imaging device 10 and the video signal processing unit 830 based on control by the system control unit 860.

  As described above, the imaging system 800 of this embodiment can perform an imaging operation by applying the imaging device 10 of any of the first to fifth embodiments described above.

  Embodiments to which the present invention can be applied are not limited to the above-described embodiments. For example, an embodiment in which a part of the configuration of any of the embodiments is added to another embodiment, or an embodiment in which a part of the configuration of another embodiment is replaced is also an embodiment to which the present invention can be applied. Should be understood.

  The imaging system shown in the sixth embodiment is an example of an imaging system to which the imaging apparatus of the present invention can be applied. An imaging system to which the imaging apparatus of the present invention can be applied is shown in FIG. It is not limited to the configuration.

100 pixels 104 comparator 105 counter 107 first memory group 108 second memory group

Claims (18)

An imaging apparatus that includes a plurality of pixels arranged in a plurality of columns and that outputs a pixel signal corresponding to incident light by photoelectric conversion, and obtains a digital value by performing AD conversion on the pixel signal for each column. ,
A first memory group and a second AD conversion which are provided corresponding to each of the plurality of columns and hold the digital value obtained by performing the first AD conversion on the same pixel signal. A second memory group for holding the digital value obtained by performing,
The first memory group has a bit width of N + 1 bits (N is a natural number) and holds from the least significant bit to the (N + 1) th bit of the digital value obtained by the first AD conversion,
The second memory group has a bit width of M bits (M is a natural number) larger than N + 1 bits, and includes the least significant bit to the Mth bit of the digital value obtained by the second AD conversion. An imaging device characterized by being held.   The first AD conversion and the second AD are performed by sequentially performing a binary search by comparing the pixel signal and a voltage signal for successive approximation operation, provided corresponding to each of the plurality of columns. The imaging apparatus according to claim 1, further comprising a successive approximation AD conversion circuit that performs AD conversion. Obtaining a difference value obtained by subtracting a value from the least significant bit to the (N + 1) th bit of the digital value held in the second memory group from the digital value held in the first memory group;
The imaging apparatus according to claim 1, wherein a value obtained by adding twice the digital value held in the second memory group and the difference value is output. Obtaining a difference value obtained by subtracting a value from the least significant bit to the (N + 1) th bit of the digital value held in the second memory group from the digital value held in the first memory group;
When the difference value is equal to or greater than − (2 ^N −1) [LSB] and equal to or less than 2 ^N −1 [LSB], the digital value held in the second memory group is doubled; Output the value obtained by adding the difference value,
When the difference value is larger than 2 ^N −1 [LSB], the digital value held twice in the second memory group and the difference value are added, and 2 ^{N + 1} is calculated from the result of the addition. Output the value obtained by subtraction,
When the difference value is smaller than − (2 ^N −1) [LSB], the difference value is added to twice the digital value held in the second memory group, and the result of the addition is added. The value obtained by adding 2 ^{N + 1} is output. The imaging apparatus according to claim 1, wherein the imaging apparatus outputs the value obtained by adding 2 ^{N + 1} . A plurality of pixels arranged in a plurality of columns and outputting a pixel signal corresponding to incident light by photoelectric conversion;
Comparing the magnitude relationship between the pixel signal and a reference signal that changes with time, provided corresponding to each of the plurality of columns, and outputs a control signal in response to the magnitude relationship being inverted. A comparator;
A counter that outputs a count value indicating an elapsed time from the start of the change of the reference signal;
A first memory group and a second memory group which are provided corresponding to each of the plurality of columns and hold the count value at the time when the control signal is output;
The comparator performs a plurality of the comparisons including a first comparison and a second comparison on the same pixel signal;
The first memory group and the second memory group respectively hold the count value obtained by the first comparison and the count value obtained by the second comparison,
The first memory group has a bit width of N + 1 bits (N is a natural number), and holds from the least significant bit to the N + 1th bit of the count value obtained by the first comparison,
The second memory group has a bit width of M bits (M is a natural number) larger than N + 1 bits, and holds from the least significant bit to the Mth bit of the count value obtained by the second comparison. An imaging apparatus characterized by:   The imaging apparatus according to claim 5, wherein the count value is a gray code including a plurality of bits.   The imaging apparatus according to claim 5, wherein the counter outputs the common count value to each of the comparators.   The imaging device according to claim 5, wherein one comparator is provided corresponding to each of the plurality of columns.   The imaging device according to claim 5, wherein a plurality of the comparators are provided corresponding to each of the plurality of columns.   The imaging apparatus according to claim 9, wherein the plurality of comparators corresponding to the same column among the plurality of columns have different input offset voltages. The count value output by the counter during the first comparison is an N + 1 bit Gray code,
11. The imaging apparatus according to claim 5, wherein the count value output by the counter in the second comparison is an M-bit Gray code. 11. The count value output by the counter during the first comparison and the count value output by the counter during the second comparison are the same. The imaging apparatus according to item 1. The second memory group includes
A plurality of memories having a bit width of N + 1 bits and holding from the least significant bit to the (N + 1) th bit of the count value obtained by the second comparison;
A bit width of M− (N + 1) bits, and the first of the count values corresponding to the difference between the count value obtained by the second comparison and the count value obtained by the first comparison The imaging apparatus according to claim 5, further comprising a ripple counter that holds N + 2 bits to the Mth bit. The comparator performs the comparison using the same reference signal in the first comparison and the second comparison,
The imaging device according to any one of claims 5 to 13, wherein the first comparison and the second comparison are performed in different periods. The comparator is
In the first comparison, the magnitude relationship between the pixel signal and the first reference signal is compared,
15. The magnitude relation between the pixel signal and a second reference signal different from the first reference signal is compared in the second comparison. The imaging device described in 1. Obtaining a difference value obtained by subtracting a value from the least significant bit to the (N + 1) th bit of the count value held in the second memory group from the count value held in the first memory group;
16. The value obtained by adding twice the count value held in the second memory group and the difference value is output. 16. Imaging device. Obtaining a difference value obtained by subtracting a value from the least significant bit to the (N + 1) th bit of the count value held in the second memory group from the count value held in the first memory group;
When the difference value is equal to or greater than − (2 ^N −1) [LSB] and equal to or less than 2 ^N −1 [LSB], the count value held in the second memory group is doubled; Output the value obtained by adding the difference value,
If the difference value is larger than 2 ^N −1 [LSB], the difference value is added to twice the count value held in the second memory group, and 2 ^{N + 1} is calculated from the result of the addition. Output the value obtained by subtraction,
When the difference value is smaller than − (2 ^N −1) [LSB], the difference value is added to twice the count value held in the second memory group, and the result of the addition is added. The imaging apparatus according to claim 5, wherein a value obtained by adding 2 ^{N + 1} is output. An imaging device according to any one of claims 1 to 17,
An image pickup system comprising: a signal processing unit that processes a signal output from the image pickup apparatus.

Images