JP2020078024A - Solid-state imaging element and control method of the same, imaging apparatus, and program - Google Patents

Abstract

To suppress a decrease in signal acquisition speed.SOLUTION: A first operation is an operation in which a phase signal A (first signal) which is a signal of a part (PDs 12a) of a plurality of PDs 12 in each of the unit pixels 10 in a pixel array unit 100 is read out to AD convert the phase signal A. A second operation is an operation in which an imaging signal (second signal), which is a signal obtained by adding signals of all PDs 12 (PDs 12a and 12b) in each of the unit pixels 10, is read out to AD convert the imaging signal. In a first read mode, a read control circuit 30 controls an AD conversion circuit 20 so that the second operation is continuously performed a plurality of times (twice) and the first operation is performed a number of times less than the second operation (once) when reading the signals output from all the unit pixels 10 in the pixel array unit 100.SELECTED DRAWING: Figure 4

Description

  The present invention relates to a solid-state imaging device having a pixel unit in which a plurality of unit pixels having a plurality of pupil-divided photoelectric conversion units are arranged in a matrix, a control method thereof, an imaging device, and a program.

  Conventionally, there is known a method of suppressing random noise with respect to a signal by performing AD conversion a plurality of times and then performing addition or arithmetic averaging when reading a signal from a pixel portion of a solid-state image sensor such as a CMOS type. For example, in Patent Document 1, the random noise included in the read signal is suppressed by AD-converting the output signal of the pixel continuously a plurality of times and adding the AD-converted results.

JP 2012-4727 A

  By the way, a solid-state imaging device having a pixel unit in which a pupil of an imaging optical system is divided and a plurality of unit pixels having a plurality of photodiodes (PD) which are photoelectric conversion units are arranged in a matrix for one microlens is provided. Are known. In the solid-state image sensor having such a pixel configuration, the signal read time increases according to the number of PDs per pixel. Therefore, if AD conversion is performed a plurality of times on each of the PD output signals, there is a problem that the signal acquisition speed may significantly decrease.

  An object of the present invention is to suppress a decrease in signal acquisition speed.

  In order to achieve the above-mentioned object, the present invention provides a pixel unit in which a plurality of unit pixels having a plurality of photoelectric conversion units into which light obtained by pupil division of an imaging optical system is incident are arranged in a matrix, and in each of the unit pixels. A first operation of reading a first signal, which is a signal of a part of the photoelectric conversion parts of the plurality of photoelectric conversion parts, and performing AD conversion, and adding all signals of the plurality of photoelectric conversion parts in each of the unit pixels And a control means for controlling the readout means when the signal output from the pixel portion is read out. The control means performs the second operation in succession a plurality of times when reading a signal output from at least a part of the unit pixels in the pixel unit, and the number of times of the second operation is less than the number of times of the second operation. It is characterized in that it has a read mode for controlling the read means so that the first operation is performed or the first operation is not performed.

  According to the present invention, it is possible to suppress a decrease in signal acquisition speed.

It is a circuit diagram which shows the structure of a solid-state image sensor. It is a circuit diagram which shows the structure of a unit pixel. It is a block diagram of a camera system. 6 is a timing chart showing a first signal reading operation. 6 is a timing chart showing a second signal reading operation. It is a figure explaining the read-out operation of a pixel array part. It is a timing chart which shows the 3rd signal read-out operation. It is a timing chart which shows the 4th signal read-out operation. It is a figure explaining the read-out operation of a pixel array part.

  Hereinafter, embodiments of the present invention will be described with reference to the drawings.

(First embodiment)
FIG. 1 is a circuit diagram showing a configuration of a solid-state image sensor according to the first embodiment of the present invention. The imaging unit 1 (FIG. 3) is applied to an imaging device such as a digital camera, for example. The imaging unit 1 includes, for example, a CMOS type solid-state imaging device. This solid-state imaging device has a pixel array section 100 as a pixel section and an AD conversion circuit 20 as a conversion section. The pixel array unit 100 is configured by arranging a plurality of unit pixels 10 in a matrix.

  FIG. 2 is a circuit diagram showing the configuration of the unit pixel 10. As shown in FIG. 2, the unit pixel 10 includes photodiodes (hereinafter referred to as PDs) 12 (12a) as a plurality of photoelectric conversion units to which light obtained by pupil division of the lens unit 1001 (FIG. 3) (shooting optical system) is incident. , 12b). Further, the unit pixel 10 includes a microlens 11, transfer switches 13a and 13b, a floating diffusion (hereinafter, referred to as FD) 14, an amplification MOS amplifier 15, a row selection switch 16, and a reset switch 17.

  The PDs 12a and 12b generate electric charges according to light incident through the photographing optical system. The PDs 12a and 12b are connected to the FD 14 via transfer switches 13a and 13b, respectively. The transfer switches 13a and 13b are driven by transfer pulses PTXa and PTXb input to their gate terminals, respectively, and transfer the charges generated in the PDs 12a and 12b to the FD 14. The FD 14 temporarily stores the transferred charges and converts the stored charges into a voltage signal.

  The amplification MOS amplifier 15 functions as a source follower in cooperation with the constant current circuit 22 (FIG. 1). To the gate of the amplification MOS amplifier 15, the signal in which the charge is converted into the voltage by the FD 14 is input. The row selection switch 16 is driven by the row selection pulse PSEL input to its gate. The drain of the row selection switch 16 is connected to the amplification MOS amplifier 15, and the source of the row selection switch 16 is connected to the vertical output line 21. The row selection switch 16 in which the row selection pulse PSEL becomes the active level (high level) becomes conductive, and the source of the corresponding amplification MOS amplifier 15 is connected to the vertical output line 21. The vertical output line 21 is shared by the plurality of unit pixels 10 and is connected to the constant current circuit 22 and the signal amplification circuit 23 (FIG. 1).

  The drain of the reset switch 17 is connected to the power supply line VDD. The reset switch 17 is driven by the reset pulse PRES input to its gate to remove the electric charge accumulated in the FD 14. The amplification MOS amplifier 15 outputs a reset signal to the vertical output line 21 when the FD 14 is reset by the reset pulse PRES. Further, when one of the charges generated in the PDs 12a and 12b is transferred by the transfer pulse PTXa or PTXb, the amplification MOS amplifier 15 outputs a phase signal including the photoelectric conversion signal of one PD 12. To do. Further, the amplification MOS amplifier 15 operates as follows when both the charges generated in the PDs 12a and 12b are transferred by the transfer pulse PTXa or PTXb. That is, the amplification MOS amplifier 15 outputs an imaging signal including photoelectric conversion signals of all PDs (here, PD 12a and PD 12b) included in the unit pixel 10.

  A signal reading circuit included in the imaging unit 1 will be described with reference to FIG. In the pixel array unit 100, the unit pixels 10 are arranged in a matrix, and the vertical output line 21 is shared for each column. A constant current circuit 22, a signal amplifier circuit 23, a comparator 24, a counter circuit 25, an averaging circuit 26 and a CDS circuit 27 are provided for each column of the pixel array section 100, corresponding to the vertical output line 21. Since the configuration corresponding to each vertical output line 21 is common, one vertical output line 21 will be focused and described. A constant current circuit 22 is connected to the vertical output line 21. The constant current circuit 22 functions as a source follower in cooperation with the amplification MOS amplifier 15 connected via the row selection switch 16. At this time, the signal potential of the FD 14 is reflected in the potential of the vertical output line 21.

  The signal amplification circuit 23 is an amplifier that applies a gain to the signal of the vertical output line 21, and the gain setting can be changed by the gain setting signal Gain output from the read control circuit 30. The signal amplification circuit 23 is useful from the viewpoint of noise reduction, but is not essential. The signal output from the signal amplification circuit 23 is input to one terminal of the comparator 24, and the gradually changing reference signal Vramp is input to the other terminal. The comparator 24 outputs the comparison result of these signals. The reference signal Vramp is output from the read control circuit 30.

  The AD conversion circuit 20 includes a comparator 24, a counter circuit (CNT) 25, and an averaging circuit 26. The AD conversion circuit 20 converts the analog signal from the signal amplification circuit 23 into a digital signal. The counter circuit 25 performs up-counting or down-counting according to the input reference clock CLK. Further, the counter circuit 25 stops or starts counting according to the comparison result output from the comparator 24. AD conversion is realized by these operations. The AD conversion method is not limited to the slope type AD conversion method described above, and other AD conversion methods can be adopted. The counter circuit 25 is capable of continuously performing AD conversion a plurality of times and accumulating the count value by restarting the count while holding the count value after the count is stopped. The averaging circuit 26 calculates an average value per AD conversion from the count value AD-converted by the comparator 24 and the counter circuit 25 and the number of times the AD conversion is continuously performed. If the AD conversion is performed once, the averaging circuit 26 outputs the count value as it is as an average value.

  The CDS circuit 27 holds the reset signal AD-converted by the comparator 24 and the counter circuit 25 and averaged by the averaging circuit 26. After that, the CDS circuit 27 subtracts the reset signal from each of the AD-converted and averaged phase signal and imaging signal. The horizontal transfer memory 28 acquires the subtraction result of the CDS circuit 27 of each column of the pixel array unit 100 and sequentially outputs the subtraction result to the outside of the imaging unit 1.

  FIG. 3 is a block diagram of a camera system as an image pickup apparatus equipped with the image pickup unit 1. The lens unit 1001 forms an optical image of a subject on the imaging unit 1. The lens drive unit 1002 executes zoom control, focus control, aperture control, and the like. The shutter drive unit 1004 controls the mechanical shutter 1003, so that the mechanical shutter 1003 controls the exposure and light blocking of the imaging unit 1. The signal processing circuit 1005 performs various corrections, data compression, and a combination processing of a plurality of images for obtaining a wide dynamic range image on the image signal output from the image pickup unit 1. The shooting mode / timing generation unit 1006 outputs a shooting mode instruction signal and various timing signals to the image pickup unit 1 and the signal processing circuit 1005. The memory unit 1007 functions as a memory for temporarily storing image data. The overall control calculation unit 1008 performs various calculations and controls the entire camera system. The medium I / F unit 1009 is an interface for performing recording or reading on the recording medium 1010. The recording medium 1010 is a detachable semiconductor memory and records image data. The display unit 1011 is a device that displays various information and captured images.

  Next, the operation of the camera system during shooting will be described. When the main power supply of the camera system is turned on, the control system (the shooting mode / timing generation unit 1006, the overall control calculation unit 1008, etc.) is turned on, and the image processing system circuits such as the signal processing circuit 1005 are also turned on. To be done. Then, when a release button (not shown) is pressed, the photographing operation is started.

  The shooting mode / timing generation unit 1006 instructs the imaging unit 1 to shoot. When the shooting operation is completed, the signal output from the image capturing unit 1 is input to the signal processing circuit 1005. Here, the image pickup signal corresponds to the sum of the phase signal A, which is the signal of the charge accumulated in the PD 12a, and the phase signal B, which is the signal of the charge accumulated in the PD 12b. The signal processing circuit 1005 calculates the phase signal B by subtracting the input phase signal A from the image pickup signal. After that, the image pickup signal is subjected to image processing by the signal processing circuit 1005, and is written as image data in the memory unit 1007 according to an instruction from the overall control calculation unit 1008. The image data written in the memory unit 1007 is recorded on the recording medium 1010 via the medium I / F unit 1009 under the control of the overall control calculation unit 1008. Alternatively, the image data written in the memory unit 1007 may be directly transferred to a computer or the like via an external I / F unit (not shown).

  On the other hand, the phase signal A and the phase signal B are subjected to noise reduction processing in the signal processing circuit 1005 as necessary, and then sent to the overall control calculation unit 1008. The overall control calculation unit 1008 calculates the driving amount of the focus position of the lens unit 1001 by applying the phase signal A and the phase signal B to the correlation calculation, and outputs the driving amount to the lens driving unit 1002. The lens drive unit 1002 operates the lens unit 1001 based on the input drive amount to change the focus position.

  Regarding the reading by the AD conversion circuit 20 of the signal output from the pixel array unit 100, the imaging unit 1 has at least one reading mode. In the present embodiment, the read control circuit 30 as the control means controls the AD conversion circuit 20 as the read means in the first read mode.

  FIG. 4 is a timing chart showing the first signal read operation in the first read mode. The AD conversion circuit 20 can perform the “first operation” and the “second operation”. Here, “first operation” and “second operation” in the signal reading operation are defined. The first operation is an operation of reading a phase signal A (first signal) which is a signal of a part (PD12a) of the plurality of PDs 12 in each of the unit pixels 10 in the pixel array section 100, and AD-converting the phase signal A. Is. The second operation is an operation of reading an image pickup signal (second signal) which is a signal obtained by adding signals of all the PDs 12 (PDs 12a and 12b) in each of the unit pixels 10 and AD-converting the image pickup signal. In the first read mode, the read control circuit 30 continuously performs the second operation a plurality of times when reading the signals output from all the unit pixels 10 in the pixel array section 100, and the number of times of the second operation. The first operation is performed a smaller number of times. The number of executions of the second operation is two in the example of FIG. 4, and the number of executions of the first operation is one in the example of FIG.

  The first signal read operation will be described with reference to FIG. The row selection pulse PSEL, the reset pulse PRES, and the transfer pulses PTXa and PTXb shown in FIG. 2 are input to the pixel array unit 100 from the read control circuit 30 (FIG. 1). Hereinafter, (n) is added to the pulse relating to the unit pixel 10 in the nth row.

  When the row selection pulse PSEL (n) becomes “H” at time t1, the unit pixels 10 in the nth row output signals to the corresponding vertical output lines 21. At time t1, the reset pulse PRES (n) becomes “H”, unnecessary charges of the FD 14 are discharged, and the reset pulse PRES (n) becomes “L” after the potential of the FD 14 is reset. At this time, the unit pixel 10 in the nth row outputs a reset signal to the vertical output line 21. The reset signal is reflected on the vertical output line 21 over a settling time, and is input to the comparator 24 via the signal amplification circuit 23.

  At time t2, the read control circuit 30 outputs the gradually changing comparison signal Vramp to the comparator 24. At time t2, the reference clock CLK is also input to the counter circuit 25, so that the counter circuit 25 starts counting, and thus AD conversion related to the reset signal is started. After that, at time t3 when the comparison signal Vramp falls below the reset signal, the comparator 24 inverts the output Comp. The counter circuit 25 temporarily stops the counting operation when the output Comp of the comparator 24 is inverted. At time t4, when the comparison signal Vramp reaches the first predetermined potential, the comparison signal Vramp is reset to the initial value and the reference clock CLK is stopped.

  At time t5, the read control circuit 30 outputs the gradually changing comparison signal Vramp to the comparator 24, as at time t2. At time t5, the reference clock CLK is also input to the counter circuit 25, so that the counter circuit 25 restarts counting, thereby restarting AD conversion. Then, at time t6 when the comparison signal Vramp falls below the reset signal, the comparator 24 inverts the output Comp. The counter circuit 25 stops the counting operation when the output Comp of the comparator 24 is inverted. At time t7, when the comparison signal Vramp reaches the first predetermined potential, the comparison signal Vramp is reset to the initial value and the reference clock CLK is stopped.

  Since the AD conversion of the reset signal is performed twice from the time t2 to the time t7, the count value of the counter circuit 25 becomes a value obtained by accumulating the count values of the two AD conversions. When the AD conversion is performed three times or more, the operations from time t5 to t7 are continuously repeated so that the AD conversion is performed a desired number of times.

  At time t8, when the transfer pulse PTXa (n) becomes “H”, the charge accumulated in the PD 12a is transferred to the FD 14. After that, when the transfer pulse PTXa (n) becomes “L”, the phase signal A is output from the unit pixel 10 in the nth row to the vertical output line 21. The phase signal A is reflected on the vertical output line 21 over a settling time. At time t8, the counter reset signal RST becomes “H”, and the counter circuits 25 in each column output the count values to the averaging circuit 26 and then reset the count values. The counter reset signal RST is input from the read control circuit 30. The averaging circuit 26 calculates the average value of the input count values according to the number of AD conversions to obtain the AD conversion result of the reset signal per AD conversion, and outputs the result to the CDS circuit 27. To do. The CDS circuit 27 holds the AD-converted reset signal.

  At time t9, the read control circuit 30 outputs the gradually changing comparison signal Vramp to the comparator 24. At time t9, the reference clock CLK is input to the counter circuit 25, so that the counter circuit 25 starts counting, and thus AD conversion of the phase signal A is started. After that, at time t10 when the comparison signal Vramp falls below the phase signal A, the comparator 24 inverts the output Comp. The counter circuit 25 stops the counting operation when the output Comp of the comparator 24 is inverted. At time t11, when the comparison signal Vramp reaches the second predetermined potential, the comparison signal Vramp is reset to the initial value and the reference clock CLK is stopped. The number of AD conversions of the phase signal A is one, and thereafter AD conversion is not performed. Therefore, the first operation is performed once from time t9 to time t11.

  At time t12, the transfer pulses PTXa (n) and PTXb (n) become “H”, and thus the electric charges accumulated in the PDs 12a and 12b are transferred to the FD 14. After that, the transfer pulses PTXa (n) and PTXb (n) become “L”, so that the unit pixel 10 in the nth row outputs the image pickup signal to the vertical output line 21. As described above, the image pickup signal corresponds to the sum of the phase signal A which is the signal of the charge accumulated in the PD 12a and the phase signal B which is the signal of the charge accumulated in the PD 12b. The image pickup signal is reflected on the vertical output line 21 over a settling time. At time t12, the counter reset signal RST becomes “H”, so that the counter circuits 25 in each column output the count values to the averaging circuit 26 and then reset the count values.

  The averaging circuit 26 calculates the average value of the input count values according to the number of AD conversions. However, since the number of AD conversions of the phase signal A is one here, the averaging circuit 26 outputs the input count value as it is to the CDS circuit 27. The CDS circuit 27 subtracts the reset signal held at time t8 from the AD-converted phase signal A, and outputs the subtraction result to the horizontal transfer memory 28. The horizontal transfer memory 28 acquires the subtraction result of the CDS circuit 27 from each column and sequentially outputs it to the subsequent stage.

  At time t13, the read control circuit 30 outputs the gradually changing comparison signal Vramp to the comparator 24. At time t13, the reference clock CLK is input to the counter circuit 25, so that the counter circuit 25 starts counting, and thus AD conversion related to the image pickup signal is started. After that, at time t14 when the comparison signal Vramp falls below the image pickup signal, the comparator 24 inverts the output Comp. The counter circuit 25 temporarily stops the counting operation when the output Comp of the comparator 24 is inverted. At time t15, when the comparison signal Vramp reaches the second predetermined potential, the comparison signal Vramp is reset to the initial value and the reference clock CLK is stopped.

  At time t16, the read control circuit 30 outputs the gradually changing comparison signal Vramp to the comparator 24. At time t16, the reference clock CLK is input to the counter circuit 25, so that the counter circuit 25 restarts counting. After that, at time t17 when the comparison signal Vramp falls below the image pickup signal, the comparator 24 inverts the output Comp. The counter circuit 25 stops the counting operation when the output Comp of the comparator 24 is inverted. At time t18, when the comparison signal Vramp reaches the second predetermined potential, the comparison signal Vramp is reset to the initial value and the reference clock CLK is stopped. Therefore, the second operation is repeated twice from time t13 to time t18.

  Since the AD conversion of the image pickup signal is performed twice from time t13 to time t18, the count value of the counter circuit 25 becomes a value obtained by accumulating the count values of the two AD conversions. When AD conversion is performed three times or more, the operations from time t16 to t18 are continuously repeated so that the AD conversion is performed a desired number of times.

  At time t19, the row selection pulse PSEL (n) becomes “L”, so that the unit pixel 10 in the nth row is disconnected from the corresponding vertical output line 21. At time t19, the counter reset signal RST becomes “H”, so that the counter circuits 25 in each column output the count values to the averaging circuit 26 and then reset the count values. The averaging circuit 26 calculates the average value of the input count values according to the number of AD conversions to obtain the AD conversion result of the image pickup signal per AD conversion, and outputs the result to the CDS circuit 27. To do. The CDS circuit 27 subtracts the reset signal held at time t8 from the AD-converted image pickup signal, and outputs the subtraction result to the horizontal transfer memory 28. The horizontal transfer memory 28 acquires the subtraction result of the CDS circuit 27 from each column and sequentially outputs it to the subsequent stage.

  By the way, the phase signal B corresponding to the signal of the PD 12b alone is calculated by subtracting the phase signal A from the imaging signal by the signal processing circuit 1005 (FIG. 3) in the subsequent stage of the imaging unit 1.

  In the first read operation, random noise is suppressed by performing AD conversion twice for the reset signal and the image pickup signal and adding and averaging them. On the other hand, since the AD conversion is performed only once for the phase signal A, the signal acquisition speed is improved as compared with the case where the AD conversion is performed twice or more. On the other hand, random noise is not reduced in the phase signal as compared with the image pickup signal. However, the phase signal is a signal used inside the camera system, such as being mainly used for autofocus (AF) in the camera system. Therefore, with respect to the phase signal, noise can be reduced by a separate process such as an addition and averaging process or a noise filter process using the signals of a plurality of adjacent unit pixels 10. Therefore, these separate processes are applied. do it.

  In this way, it is possible to suppress deterioration of the reading speed by reducing the number of AD conversions of the phase signal to be smaller than the AD conversion of the imaging signal while obtaining good image quality by performing the AD conversion of the reset signal and the imaging signal a plurality of times. Become. In particular, by mounting the image pickup unit 1 on the camera system, it is possible to simultaneously perform AF while obtaining good image quality and realize them at a high frame rate.

  According to the present embodiment, the number of AD conversions (first operation) of the phase signal is made smaller than the continuous number (two times) of AD conversion (second operation) of the imaging signal in the first read mode. It is possible to suppress a decrease in the signal acquisition speed.

(Second embodiment)
In the first embodiment, the first read mode is applied to the signal read from all the unit pixels 10 in the pixel array section 100. On the other hand, in the second embodiment of the present invention, the first read mode is applied to the signal read from some unit pixels 10 in the pixel array section 100, and the signal read from other unit pixels 10 is performed. The second read mode is applied to. In the present embodiment, the signal acquisition speed is reduced by reducing the number of unit pixels 10 that read a phase signal used for AF among the plurality of unit pixels 10 included in the pixel array unit 100, as compared with the first embodiment. Further improve.

  FIG. 5 is a timing chart showing the second signal read operation in the second read mode. FIG. 6 is a diagram for explaining the read operation of the pixel array section 100.

  As shown in FIG. 6, the read control circuit 30 can perform either the first read operation or the second read operation row by row. The imaging unit 1 has a first read mode and a second read mode. In the present embodiment, the read control circuit 30 controls the AD conversion circuit 20 using both the first read mode and the second read mode. Specifically, when reading the signals output from the unit pixels 10 of the first group in which the pixel areas of the pixel array unit 100 are divided, the read control circuit 30 performs AD in the first read operation in the first read mode. The conversion circuit 20 is controlled. In addition, the read control circuit 30 controls the AD conversion circuit 20 by the second read operation in the second read mode when reading the signals output from the unit pixels 10 of the second group different from the first group. Here, the second read mode is a read mode in which the second operation is continuously performed a plurality of times and the first operation is not performed. The second signal read operation in the second read mode will be described with reference to FIG.

  The second signal read operation is the same as the first signal read operation (FIG. 4) except for some portions, and therefore the different points will be mainly described. The second signal read operation corresponds to the operation in which the operations from time t8 to t11 in the first signal read operation are omitted. In other words, the operation from time t21 to t27 is equivalent to the operation from time t1 to t7 of the first signal read operation, and the operation from time t28 to t35 is the operation from time t12 to t19 of the first signal read operation. Is equivalent to

  The second signal read operation improves the signal read speed by omitting the operation of acquiring the phase signal A, as compared with the first signal read operation. However, if the signal output from the unit pixel 10 is read only by the second signal reading operation, the phase signal required for AF cannot be acquired. Therefore, the read control circuit 30 performs the first read operation, not the second signal read operation, for some (first group) of the plurality of unit pixels 10 included in the pixel array section 100. As a result, AF is realized while ensuring the reading of the phase signal used for AF.

  6, a column read circuit 200 includes a plurality of constant current circuits 22, a signal amplification circuit 23, a comparator 24, a counter circuit 25, an averaging circuit 26, a CDS circuit provided in each column shown in FIG. 27 and a horizontal transfer memory 28. The unit pixels 10 of the first group and the unit pixels 10 of the second group are divided in row units and are alternately arranged in the column direction. In the present embodiment, as compared with the first embodiment in which the first read operation is performed in all rows, the unit pixel 10 in which the phase signal is not read is present, and thus the read speed per frame is improved. Since the number of rows from which the phase signal used for AF is read decreases, it is particularly effective when the frame rate is prioritized over the followability of AF, or when the range of AF measurement is narrow.

  According to the present embodiment, the first and second read modes are used in combination, and the reading of the signals output from the unit pixels 10 of the second group is controlled by the second read operation in the second read mode. It Therefore, it is possible to further suppress the decrease in the signal acquisition speed.

(Third Embodiment)
A third embodiment of the present invention will be described with reference to FIGS. In the second embodiment, since the read time per row differs between the first read mode and the second read mode, unnatural rolling distortion may occur when a moving subject is imaged. . Therefore, in the present embodiment, a method is adopted in which the reading time per row is made as common as possible between the rows. In the present embodiment, the third read mode is applied to the signal read from some unit pixels 10 in the pixel array section 100, and the fourth read mode is applied to the signal read from other unit pixels 10. Apply the mode.

  FIG. 7 is a timing chart showing a third signal read operation in the third read mode. FIG. 8 is a timing chart showing a fourth signal read operation in the fourth read mode. FIG. 9 is a diagram for explaining the read operation of the pixel array section 100.

  As shown in FIG. 9, the read control circuit 30 can perform either the third read operation or the fourth read operation row by row. The imaging unit 1 has a third read mode and a fourth read mode. In the present embodiment, the read control circuit 30 controls the AD conversion circuit 20 using both the third read mode and the fourth read mode. Specifically, the read control circuit 30 controls the AD conversion circuit 20 by the third read operation in the third read mode when reading the signals output from the unit pixels 10 of the first group. Further, the read control circuit 30 controls the AD conversion circuit 20 by the fourth read operation in the fourth read mode when reading the signals output from the unit pixels 10 of the second group.

  Here, the third read mode is a mode in which both the first operation and the second operation are performed the same predetermined number of times. The fourth read mode is a mode in which the second operation is continuously performed twice the predetermined number of times and the first operation is not performed. The third and fourth signal read operations in the third and fourth read modes will be described with reference to FIGS. 7 and 8.

  As shown in FIG. 7, the third signal read operation is the same as the first signal read operation (FIG. 4) except for a part, and therefore the different points will be mainly described. The operation from time t41 to t51 of the third signal read operation is the same as the operation from time t1 to t11 of the first signal read operation. At time t52, when the transfer pulses PTXa (n) and PTXb (n) become “H”, the charges accumulated in the PDs 12a and 12b are transferred to the FD 14. After that, the transfer pulses PTXa (n) and PTXb (n) become “L”, so that the unit pixel 10 in the nth row outputs the image pickup signal to the vertical output line 21. The image pickup signal is reflected on the vertical output line 21 over a settling time. At time t52, the counter reset signal RST becomes “H”, so that the counter circuits 25 in each column output the count values to the averaging circuit 26 and then reset the count values.

  The averaging circuit 26 calculates the average value of the input count values according to the number of AD conversions. However, since the number of AD conversions of the phase signal A is one here, the averaging circuit 26 outputs the input count value as it is to the CDS circuit 27. The CDS circuit 27 subtracts the reset signal held at time t48 from the AD-converted phase signal A, and outputs the subtraction result to the horizontal transfer memory 28. The horizontal transfer memory 28 acquires the subtraction result of the CDS circuit 27 from each column and sequentially outputs it to the subsequent stage.

  At time t53, the read control circuit 30 outputs the gradually changing comparison signal Vramp to the comparator 24. At time t53, the reference clock CLK is also input to the counter circuit 25, so that the counter circuit 25 starts counting, whereby AD conversion related to the image pickup signal is started. After that, at time t54 when the comparison signal Vramp falls below the image pickup signal, the comparator 24 inverts the output Comp. The counter circuit 25 temporarily stops the counting operation when the output Comp of the comparator 24 is inverted. At time t55, when the comparison signal Vramp reaches the second predetermined potential, the comparison signal Vramp is reset to the initial value and the reference clock CLK is stopped. Here, in the third read mode, the number of AD conversions of the image pickup signal is one, and thereafter AD conversion is not performed. Therefore, the second operation is performed once from time t53 to time t55.

  At time t56, the row selection pulse PSEL (n) becomes “L”, so that the unit pixel 10 in the nth row is disconnected from the corresponding vertical output line 21. At time t56, the counter reset signal RST becomes “H”, so that the counter circuits 25 in each column output the count values to the averaging circuit 26 and then reset the count values. The averaging circuit 26 calculates the average value of the input count values according to the number of AD conversions. However, since the number of AD conversions of the phase signal A is one here, the averaging circuit 26 outputs the input count value as it is to the CDS circuit 27. The CDS circuit 27 subtracts the reset signal held at time t48 from the AD-converted image pickup signal, and outputs the subtraction result to the horizontal transfer memory 28. The horizontal transfer memory 28 acquires the subtraction result of the CDS circuit 27 from each column and sequentially outputs it to the subsequent stage.

  As shown in FIG. 8, the fourth signal read operation is equivalent to the second signal read operation (FIG. 5) if the number of AD conversions of the image pickup signal is the same. In FIG. 8, in order to compare the fourth signal reading operation with the third signal reading operation, there is a portion where the time interval is different from that in FIG. FIG. 8 will be described in comparison with FIG. 7.

  In the third read mode (FIG. 7), AD conversion of the phase signal A is performed once, and then AD conversion of the image pickup signal is performed once. On the other hand, in the fourth read mode, instead of not acquiring the phase signal A, AD conversion of the image pickup signal is increased once, and a total of two times are performed. As a result, the total number of AD conversions of the phase signal A and the image pickup signal becomes the same two times as in the third read mode.

  In FIG. 8, at time t68 corresponding to time t48 in FIG. 7, not only the transfer pulse PTXa (n) but also the transfer pulse PTXb (n) becomes “H”, so that the charges accumulated in the PDs 12a and 12b are stored. It is transferred to the FD 14. As a result, during time t69 to t71, the AD conversion of the image pickup signal is performed instead of the phase signal A. At the time t72 corresponding to the time t52, the counter reset signal RST does not become "H" but is maintained at "L", so that the counter circuit 25 holds the count value. Therefore, from time t73 to t75 thereafter, the second AD conversion of the image pickup signal is performed. Therefore, the second operation is repeated twice from time t69 to time t75.

  At time t76 corresponding to time t56, the counter reset signal RST becomes “H”, so that the counter circuits 25 in each column output the count value to the averaging circuit 26 and then reset the count value. The averaging circuit 26 calculates the average value of the input count values according to the number of AD conversions to obtain the AD conversion result of the image pickup signal per AD conversion, and outputs the result to the CDS circuit 27. ..

  As shown in FIG. 9, the unit pixels 10 of the first group and the unit pixels 10 of the second group are divided in units of rows and are alternately arranged in the column direction. In the present embodiment, since the total number of AD conversions is the same in the fourth read operation and the third read mode, it is easier to align the read times between the rows as compared with the second read mode. ing. By the way, random noise is not reduced in the image pickup signal acquired in the third read mode as compared with the image pickup signal acquired in the fourth read mode. Therefore, it is desirable that the signal processing circuit 1005 (FIG. 3) perform noise reduction processing of the image pickup signal acquired in the third read mode.

  According to the present embodiment, the total number of AD conversions can be set to a minimum of two in both the third and fourth read modes, so that the decrease in the signal acquisition speed can be further suppressed. You can In addition, since the total number of AD conversions can be made the same in the fourth read operation and the third read mode, it is possible to align the time required for signal acquisition between the rows. Therefore, it is possible to suppress unnatural rolling distortion when a moving subject is imaged.

  In the second and third embodiments, the read control circuit 30 switches the read mode of the pixel array section 100 on a row-by-row basis. However, by increasing the number of control wirings, it is possible to support various switching patterns. That is, each group is not limited to the unit pixel group of each row.

  The above embodiments may be combined. Therefore, from the viewpoint of suppressing the decrease in the signal acquisition speed, the read control circuit 30 may control the AD conversion circuit 20 as follows. The read control circuit 30 continuously performs the second operation a plurality of times when reading the signals output from at least some of the unit pixels 10 in the pixel array section 100. At the same time, the read control circuit 30 performs the first operation or does not perform the first operation less than the number of the second operations.

  Therefore, the number of times of the first operation and the second operation in each read mode is not limited to the example. For example, in the first read mode in the first and second embodiments, the second operation may be performed three times or more, the first operation is not limited to one, and may be less than the number of second operations. In addition, in the second read mode in the second embodiment, the second operation may be performed three times or more. Further, in the third read mode in the third embodiment, the same predetermined number of times of the first operation and the second operation may be three times or more. From the viewpoint of aligning the time required for signal acquisition between the rows, the number of second operations may be twice the predetermined number in the fourth read mode. The reason for double is that the number of PDs that are pupil-divided is two. The number of PDs that are pupil-divided may be three or more. If the number of pupil-divided PDs is three, the number of second operations may be three times the predetermined number in the fourth read mode.

  In the second and third embodiments, the number of groups into which the pixel area of the pixel array section 100 is divided may be three or more. When the number of groups is three or more, in the second embodiment, the first read mode is applied to at least one of the plurality of groups and the second read mode is applied to other groups. Good. Further, in the third embodiment, the third read mode may be applied to at least one of the plurality of groups, and the fourth read mode may be applied to other groups.

(Other embodiments)
The present invention is also realized by executing the following processing. That is, software (program) that realizes the functions of the above-described embodiments is supplied to a system or device via a network or various storage media, and the computer (or CPU, MPU, etc.) of the system or device reads the program code. This is the process to be executed. In this case, the program and the storage medium storing the program constitute the present invention.

  Although the present invention has been described in detail above based on its preferred embodiments, the present invention is not limited to these specific embodiments, and various embodiments within the scope not departing from the gist of the present invention are also included in the present invention. included. Part of the above-described embodiments may be combined as appropriate.

10 unit pixel 12 PD
20 AD conversion circuit 30 readout control circuit 100 pixel array section

Claims (10)

A pixel unit in which a plurality of unit pixels having a plurality of photoelectric conversion units into which light obtained by pupil division of the photographing optical system is incident are arranged in a matrix, and
A first operation of reading and AD converting a first signal that is a signal of a part of the photoelectric conversion units of the plurality of photoelectric conversion units in each of the unit pixels, and the plurality of photoelectric conversion units of each of the unit pixels. Read out means capable of executing a second operation of AD-converting a second signal which is a signal obtained by adding all the signals of
A control unit that controls the reading unit when reading a signal output from the pixel unit,
The control unit performs the second operation in succession a plurality of times when reading a signal output from at least a part of the unit pixels in the pixel unit, and the number of times of the second operation is less than the number of times of the second operation. A solid-state image sensor having a read mode for controlling the read means so as to perform one operation or not perform the first operation.   The control unit performs the second operation in succession a plurality of times when reading the signals output from all the unit pixels in the pixel unit, and the first operation is performed a number of times less than the number of the second operations. The solid-state imaging device according to claim 1, wherein the reading unit is controlled in a first reading mode for performing the above.   The control unit performs the second operation in succession a plurality of times when reading a signal output from the unit pixel of the first group in the pixel unit, and the number of times of the second operation is less than the number of times of the second operation. In the first readout mode for performing one operation, the readout means is controlled, and when the signals output from the unit pixels of the second group different from the first group in the pixel unit are read out, a plurality of the second operations are performed. 2. The solid-state image sensor according to claim 1, wherein the read-out means is controlled in a second read-out mode in which the read-out operation is continuously performed and the first operation is not performed.   The solid-state imaging device according to claim 2, wherein the number of times of the first operation in the first read mode is one.   The control means performs the read operation in a third read mode in which both the first operation and the second operation are performed a predetermined number of times when reading the signals output from the first group of unit pixels in the pixel unit. And controlling the means to read the signal output from the unit pixel of the second group different from the first group in the pixel unit, the second operation is continuously performed twice the predetermined number of times. The solid-state image sensor according to claim 1, wherein the read-out means is controlled in a fourth read-out mode in which the first operation is not performed.   The solid-state imaging device according to claim 5, wherein the predetermined number of times is one.   The solid-state image sensor according to claim 3, 5 or 6, wherein the first group and the second group are divided in units of rows in the pixel unit. A pixel unit in which a plurality of unit pixels having a plurality of photoelectric conversion units into which light obtained by pupil division of the photographing optical system is incident are arranged in a matrix, and
A first operation of reading and AD converting a first signal that is a signal of a part of the photoelectric conversion units of the plurality of photoelectric conversion units in each of the unit pixels, and the plurality of photoelectric conversion units of each of the unit pixels. Reading out a second signal that is a signal obtained by adding all the signals in (1) and performing a second operation of AD conversion,
A method for controlling a solid-state imaging device, comprising controlling the reading means when reading a signal output from the pixel section,
When reading signals output from at least some unit pixels in the pixel unit, the second operation is continuously performed a plurality of times, and the first operation is performed a number of times less than the number of the second operations. Alternatively, the method for controlling a solid-state image pickup device has a read mode for controlling the read means so that the first operation is not performed.   An image pickup apparatus comprising the solid-state image pickup device according to any one of claims 1 to 8.   A program for causing a computer to function as each unit of the solid-state imaging device according to claim 1.

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