JP2011171950A - Signal processing apparatus, semiconductor device, solid-state imaging device, imaging apparatus, electronic device, and method of suppressing noise - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To achieve noise suppression processing, while simultaneously improving respective problems concerning simultaneity, resolution and processing load. <P>SOLUTION: A device for performing nondestructive and random read out is used (S100). The same information held by elements is read m-times (S114), the dispersion of the signal is calculated (S116), and the element with the dispersion larger than a reference value is selected as a specific element (S118). The signal based on the same information held by the specific element is read M-times with the specific element as a processing target (S126), and then, the average value of the respective signals in M times is obtained to thereby obtain a signal with the noise suppressed therein (S128). The average value of the M signals based on the same information held by the element is obtained to thereby secure the simultaneity. The specific elements with larger noise are selected and averaging procedure is performed on the selected elements, so that the resolution is not deteriorated and a signal processing load is reduced compared with a case where the averaging procedure is performed on the whole elements. <P>COPYRIGHT: (C)2011,JPO&INPIT

Description

  The present invention relates to a signal processing device, a semiconductor device, a solid-state imaging device, an imaging device, an electronic apparatus, and a noise suppression method. More specifically, the present invention relates to a signal processing technique for suppressing random noise contained in a signal acquired from an element.

  Various types of signal processing are performed in various electronic devices based on signals read from the elements. For example, a semiconductor device such as a ROM (Read Only Memory) or a RAM (Random Access Memory) using a semiconductor as a memory element, and a RAM (for example, a flash memory which is a nonvolatile semiconductor memory element) are used. Electronic devices such as a silicon disk unit (SDD: Solid State Drive) are known.

  Further, a physical quantity distribution detecting semiconductor device in which a plurality of unit components (for example, pixels) that are sensitive to electromagnetic waves input from the outside such as light and radiation are arranged in a line or matrix, and this physical quantity distribution Electronic equipment using a detection semiconductor device is used in various fields.

  For example, in the field of video equipment, a CCD (Charge Coupled Device) type, a MOS (Metal Oxide Semiconductor) type, or a CMOS (Complementary Metal-oxide Semiconductor) type solid-state imaging device that detects light (an example of an electromagnetic wave) of a physical quantity. It is used. These read out, as an electrical signal, a physical quantity distribution converted into an electrical signal by a unit component (a pixel in a solid-state imaging device).

  Further, in some solid-state imaging devices, an amplifying solid-state imaging device (APS; Active Pixel Sensor) that has a driving transistor for amplification in a pixel signal generation unit that generates a pixel signal corresponding to the signal charge generated in the charge generation unit. There is an amplification type solid-state imaging device including a pixel having a configuration (also called a gain cell).

  Here, an active element such as a MOS structure (MOS transistor) is generally used for an output stage for reading a signal from the element. When reading a signal, various noises are generated from the element, and there is a problem that the signal quality is lowered.

  For example, in a video system such as a digital camera, an image is captured by using a solid-state imaging device equipped with a CCD, a CMOS, or the like as an imaging device. I am letting.

  For example, as the pixel size is reduced, random noise called RTS (Random Telegraph Signal) noise has become a problem. RTS noise usually has a low occurrence frequency on the order of ppm, but because the noise amplitude is large, it is very conspicuous as an image (see Non-Patent Document 1).

  An “averaging method” is known as a technique for reducing random noise and improving image quality by subsequent signal processing (see Patent Document 1).

  In the mechanism of Patent Document 1, the noise is randomly generated by averaging the signals to improve the image quality S / N, and the signal processing load (memory, bandwidth) in the subsequent stage is reduced. I try to reduce it. Since a destructive readout CCD is used as a plurality of signals necessary for averaging, a so-called multiple exposure method in which exposure is performed a plurality of times is used.

JP 2004-289846 A

“A Modeling and Evaluation of the Random Telegraph Signal Noiseon a CMOS Image Sensor in Motion Pictures”, 2009 International Image Sensor Workshop (IISW) Proceedings, Session5, P13

  However, in the random noise compression method using the multiple exposure method as described in Patent Document 1, the object to be photographed moves or the photographing conditions change at the time of multiple exposures. There's a problem.

  In order to solve the problem of “non-simultaneousness”, for example, as another method of averaging without using the multiple exposure method, so-called space using information of other elements (adjacent elements) around a specific element is used. It is conceivable to use a correction method.

  The spatial correction method obtains a signal from a single exposure, so that there is “simultaneity”, but there is a problem of “decrease in resolution” because averaging is performed using signals from adjacent elements.

  In addition, the conventional “averaging method” is a method in which the signals of all the elements are processed, the average value is obtained and used as the signal of the elements, and there is a drawback that the processing load increases. For example, a large-scale data storage memory is required, and the processing speed is reduced.

  Thus, the noise suppression method to which the conventional averaging method is applied has not been able to simultaneously improve the problems relating to simultaneity, resolution, and processing load.

  The present invention has been made in view of the above circumstances, and an object of the present invention is to provide a mechanism that can simultaneously improve problems related to simultaneity, resolution, and processing load.

  According to one embodiment of the present invention, first, the same information held by an element is read m times (m is an integer of 2 or more), and a variation in each signal is obtained. An element having a larger variation than the reference value is selected as the specific element by comparing with the determined reference value.

  Then, a signal based on the same information held by the specific element is read M times (M is an integer of 2 or more), and noise is suppressed based on the read M signals. Get the signal.

  “Based on the read M signals” is not limited to using all of the read M signals. For example, when the averaging method is applied, an average value of all M signals may be taken, or an average value of MN signals excluding N (N <M) from the top of the noise amount. It may be taken. In addition, the averaging method is preferably applied. However, the value is not limited to the averaging method, and a value representative of M (or MN) signals such as a median may be used. In any case, it is only necessary to use M signals (not necessarily all) so as to obtain a signal in which noise is suppressed as compared with the prior art to which the present invention is not applied.

  The selection of the specific element may be either a method performed every time a signal is acquired or a method performed in advance separately from the signal acquisition. In the latter case, the position information of the selected specific element is held in the storage unit, and the position information read from the storage unit is referred to when acquiring a signal.

  By adopting such a mechanism, the noise suppression process can target only a specific element whose variation is larger than the reference value, not all of the plurality of elements.

  In noise suppression processing, a signal with suppressed noise is acquired using M signals (not all) based on the same information held by the element, so that "simultaneity" is ensured. . In addition, since a noise-suppressed signal is acquired by selecting a specific element having particularly large noise (for example, averaging processing is performed), the “resolution” does not decrease, and averaging processing is performed for all of a plurality of elements. The “signal processing load” can be reduced as compared with the case of performing the above.

  According to one aspect of the present invention, it is possible to implement noise suppression processing while simultaneously improving problems related to simultaneity, resolution, and processing load.

It is a schematic block diagram of a CMD type solid-state imaging device. It is a figure which shows the structural example of the reference signal production | generation part used in a solid-state imaging device. It is a simple circuit diagram of a solid-state imaging device focusing on AD conversion processing and CDS processing. It is an image figure explaining operation | movement of multiple addition AD conversion. It is a timing chart explaining multiple addition AD conversion and CDS processing. It is a figure explaining RTS noise. It is a figure explaining the basic principle of the RTS noise suppression process of this embodiment. It is a figure explaining the example which applied the RTS noise suppression process of this embodiment. It is a figure explaining 2nd Embodiment of the RTS noise suppression process of this embodiment. It is a figure explaining 3rd Embodiment of the RTS noise suppression process of this embodiment. It is a schematic block diagram of the imaging device of this embodiment. FIG. 5 is a diagram (part 1) illustrating an electronic device to which an RTS noise suppression process and a multiple addition AD conversion process are applied. It is FIG. (2) explaining the electronic device to which RTS noise suppression processing and multiple addition AD conversion processing are applied. It is a detailed explanatory view of an example of application of RTS noise suppression processing to a semiconductor memory device.

  Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings.

The description will be made in the following order.
1. 1. Overview of solid-state imaging device Basic operation of solid-state imaging device (normal AD conversion processing, multiple addition AD conversion processing)
3. RTS noise suppression processing: first embodiment (basic principle, example)
4). 4. RTS noise suppression processing: second embodiment 5. RTS noise suppression processing: third embodiment Imaging device 7. Electronic equipment: Application example for pixel defect diagnosis Electronic equipment: Other application examples (schematic structure, application examples to semiconductor memory devices)

  In the following, a case where a CMD solid-state imaging device having a charge modulation element (CMD) as a pixel, which is an example of an XY address type solid-state imaging device, is used as a device will be described as an example. However, this is an example, and the target device is not limited to the CMD solid-state imaging device. A plurality of unit components that are sensitive to electromagnetic waves input from the outside, such as light and radiation, are arranged in a line or matrix form, and signals are read by address control (particularly preferably, random address control The embodiments described later can be similarly applied to all semiconductor device for physical quantity distribution detection capable of non-destructive reading.

  Incidentally, the CMD is an example of an amplification type solid-state imaging device (amplification type light receiving device). For example, Japanese Patent Application Laid-Open No. 60-140752, Japanese Patent Application Laid-Open No. 5-95514, 1986, IEDM (International Electron Device Meeting) Preliminary Book, P353-356.

<Outline of solid-state imaging device>
FIG. 1 is a schematic configuration diagram of a CMD type solid-state imaging device (CMD image sensor) which is an embodiment of the solid-state imaging device. Note that the solid-state imaging device is also an embodiment of a semiconductor device.

  In the present specification, in the following description, the horizontal direction of the paper surface will be described as the row direction, and the vertical direction will be described as the column direction. The row direction is the direction in which the row extends, the column direction is the direction in which the column extends, and the direction in which the rows are arranged (row arrangement direction) corresponds to the column direction, and the direction in which the columns are arranged (Column arrangement direction) corresponds to the row direction.

  The solid-state imaging device 1 includes a pixel unit in which a plurality of pixels including a light receiving element (an example of a charge generation unit) that outputs a signal corresponding to an incident light amount is arranged in rows and columns (that is, in a two-dimensional matrix). . The solid-state imaging device 1 includes a current-voltage conversion circuit, a digital conversion circuit (AD conversion circuit), and the like provided in parallel in a column. “A current-voltage conversion circuit or a digital conversion circuit is provided in parallel with a column” means that a plurality of current-voltage conversion circuits are substantially parallel to a vertical signal line 19 (an example of a column signal line) in a vertical column. This means that a digital conversion circuit is provided.

  As shown in FIG. 1, the solid-state imaging device 1 includes a drive control unit 7, a pixel array unit 10, a current / voltage conversion unit 24, a column AD conversion unit 26, a reference signal generation unit 27, and an output unit 28. The pixel array unit 10 includes unit pixels 3 having CMD pixels as basic elements arranged in rows and columns, and is also referred to as a pixel unit or an imaging unit. The drive control unit 7 is provided outside the pixel array unit 10. A signal processing device that performs processing for suppressing random noise is configured by each unit except the pixel array unit 10 of the solid-state imaging device 1.

  The column AD conversion unit 26 treats a specific pixel in which noise among the plurality of unit pixels 3 is larger than a predetermined reference value as a processing target, and outputs a signal based on the same information held by the specific pixel M times ( M has a function of a signal reading unit for reading over an integer of 2 or more.

  The current-voltage conversion unit 24 converts a current signal supplied from the unit pixel 3 (CMD pixel) of the pixel array unit 10 through the vertical signal line 19 into a voltage signal (pixel signal voltage Vx), and converts the vertical signal line 19a into the voltage signal. To the column AD converter 26.

  The column AD conversion unit 26 includes an AD conversion unit 250 arranged for each vertical column. The reference signal generation unit 27 supplies the column AD conversion unit 26 with a reference signal SLP_ADC for AD conversion. Each of these functional units is provided on the same semiconductor substrate. The reference signal SLP_ADC only needs to have a waveform that changes linearly with a certain slope as a whole. The reference signal SLP_ADC may have a smooth slope shape or a stepwise change in sequence. It may be.

  When adopting the reference signal comparison type AD conversion method, as a way of thinking, it is conceivable to provide the reference signal generation unit 27 in parallel in each column (for each pixel column). For example, a configuration in which a comparator and a reference signal generator are provided in each pixel column, and the value of the reference signal is sequentially changed by the reference signal generator of the corresponding column based on the comparison result of the comparator in its own column. This is the case. However, this increases the circuit scale and power consumption. Therefore, in the present embodiment, a configuration in which the reference signal generation unit 27 is commonly used for all the columns is adopted, and a configuration in which the AD conversion unit 250 of each pixel column commonly uses the reference signal SLP_ADC generated from the reference signal generation unit 27. To.

  The AD conversion unit 250 has at least an AD conversion function, but may also have a difference processing function as necessary. The AD conversion function converts the pixel signal voltage Vx into digital data. The function of the difference processing is, for example, an AD conversion result (first phase conversion result) of dark level Sdark or reset level Srst and an AD conversion result (second phase conversion result) of light level Slight or signal level Ssig. The digital data Dsig of the signal component Vsig indicated by the difference between the dark level Sdark and the light level Slight or the difference between the reset level Srst and the signal level Ssig is acquired. The dark level Sdark and the reset level Srst are referred to as a first phase level S_1st, and the bright level Slight and the signal level Ssig are referred to as a second phase level S_2nd.

  The drive control unit 7 includes a horizontal scanning unit 12 (column scanning circuit), a vertical scanning unit 14 (row scanning circuit), and a communication / timing control unit for realizing a control circuit function for sequentially reading signals from the pixel array unit 10. 20 is provided. The communication / timing control unit 20 includes a clock conversion unit 20a having a function of a clock conversion unit that generates an internal clock, and a system control unit 20b having a communication function and a function of controlling each unit. Although not shown, for example, the horizontal scanning unit 12 includes a horizontal address setting unit and a horizontal driving unit that control column addresses and column scanning, and the vertical scanning unit 14 includes a vertical address setting unit that controls row addresses and row scanning. It has a vertical drive part.

  In the present embodiment, the horizontal scanning unit 12 and the vertical scanning unit 14 perform a typical “scanning process” for sequentially reading out the pixel positions during normal reading, but perform random access processing when performing noise reduction processing. Do. This point will be described in detail later.

  The output unit 28 includes a sense amplifier 28a (S · A) that detects a signal (digital data but small amplitude) on the horizontal signal line 18, and an interface unit 28b that functions as an interface between the solid-state imaging device 1 and the outside. I / F part). The output of the interface unit 28b is connected to the output terminal 5c, and the video data is output to the subsequent circuit.

  In the present embodiment, a digital operation unit 29 (signal processing block) that performs various digital operation processes is provided between the sense amplifier 28a and the interface unit 28b. The digital arithmetic unit 29 has at least a function of a noise suppression processing unit (averaging processing unit) that performs noise suppression processing (for example, averaging processing) not in the AD conversion unit 250 but in the subsequent stage of the AD conversion unit 250.

  The noise suppression process may be any process that can acquire a signal with suppressed noise, based on the read signals of a plurality of times (not necessarily all), as compared to the conventional technique to which the present embodiment is not applied. Typically, an averaging process can be applied. The averaging process means that the digital data output from the AD conversion unit 250 obtained by repeating a plurality of AD conversion processes is averaged corresponding to the plurality of times.

  The averaging process is not limited to taking the average value of all signals, but may take the average value of the remaining signals excluding some from the top of the noise amount. Preferably, the averaging method is applied, but not limited to the averaging method, the median value such as the median value (which may be the remainder excluding the one with a large amount of noise) is used as a representative value. Also good. Hereinafter, unless otherwise specified, the averaging process is applied.

  The purpose of noise suppression is the case of multiple addition AD conversion processing performed for all pixels for the purpose of reducing noise generated by AD conversion, and the pixel signal from the unit pixel 3 of the pixel array unit 10 to the column AD conversion unit 26. There are cases where this is performed for individual pixels for the purpose of reducing random noise called RTS (Random Telegraph Signal) noise generated when reading.

  In the former case, the digital operation unit 29 typically applies a plurality of digital data to the digital data output from the AD conversion unit 250 obtained by repeating a plurality of AD conversion processes by the column AD conversion unit 26. Averaging processing is performed corresponding to the number of times (not all but the remaining noise may be excluded).

  In the latter case, the digital arithmetic unit 29 obtains a signal in which noise is suppressed based on M (not necessarily all) signals read by the column AD conversion unit 26, and an averaging processing unit (noise suppression unit). With the function of. In the averaging process (noise suppression process), an average value of M signals may be taken, or an average value of MN signals obtained by removing N (N <M) from the top of the noise amount. It may be taken.

  In the latter case, the digital calculation unit 29 reads the same information held by the element (unit pixel 3) m times (m is an integer of 2 or more), and obtains the variation of the signal each time. It has a function of a specific element selection unit (specific pixel selection unit) that selects, as a specific element (specific pixel), an element (unit pixel 3) in which the variation of each signal of m times is larger than a predetermined reference value.

  The AD converter 250 may be configured to have the function of a noise suppression processing unit (such as an averaging processing unit). In this case, the AD conversion unit 250 is configured to suppress noise using a plurality of signals. A configuration corresponding to processing (such as averaging processing) must be provided, and the circuit space of the AD conversion unit 250 increases. On the other hand, if the digital operation unit 29 having the function of a noise suppression processing unit (such as an averaging processing unit) is provided at the subsequent stage of the AD conversion unit 250, noise suppression is achieved without increasing the circuit space of the AD conversion unit 250. Processing (such as averaging processing) can be realized.

  The clock conversion unit 20a has a built-in multiplication circuit that generates a pulse having a clock frequency higher than that of the master clock CLK0 based on the master clock CLK0 from the terminal 5a. The clock conversion unit 20a includes internal clocks such as the count clock CKcnt1 and the count clock CKdac1. Is generated. As the multiplication circuit of the clock conversion unit 20a, a k1 multiplication circuit may be provided when k1 is a multiple of the frequency of the master clock CLK0. Various known circuits such as a phase-locked loop (PLL) Can be used. By making the frequency of the count clock CKcnt1 and the count clock CKdac1 higher than the master clock CLK0, AD conversion processing, data output processing, and the like can be operated at high speed. In addition, when the digital arithmetic unit 29 is provided, a high-speed clock can be used to perform motion extraction or compression processing that requires high-speed calculation.

  In FIG. 1, for the sake of simplicity, some of the rows and columns are omitted, but in reality, each row and each column has a unit pixel 3 (CMD pixel) having several tens to thousands of signal charge amplification functions. ) Is arranged.

  The solid-state imaging device 1 can make the pixel array unit 10 compatible with color imaging by using a color separation (color separation) filter composed of a combination of a plurality of color filters for capturing a color image. That is, any color filter of the color separation filter is made to be, for example, a so-called Bayer array on the light receiving surface on which the electromagnetic wave (light in this example) of each charge generation unit (photodiode or the like) in the pixel array unit 10 is incident. To provide color image capture.

  The unit pixel 3 includes a vertical scanning unit 14 via a row control line 15 for row selection, and a column AD conversion unit 26 in which an AD conversion unit 250 is provided for each vertical column via a vertical signal line 19. , Each connected. Here, the row control line 15 indicates all the wirings that enter the unit pixel 3 from the vertical scanning unit 14.

  The elements of the drive control unit 7 such as the horizontal scanning unit 12 and the vertical scanning unit 14 are formed integrally with the pixel array unit 10 in a semiconductor region such as single crystal silicon using a technique similar to the semiconductor integrated circuit manufacturing technique. It shall be assumed. That is, a so-called one-chip device (provided on the same semiconductor substrate) is configured to form a part of the solid-state imaging device 1 as a CMOS image sensor which is an example of a semiconductor system.

  Thus, the solid-state imaging device 1 is not limited to a form in which each unit is formed as a single chip integrally formed in the semiconductor region. Although not shown in the figure, an imaging function that is packaged together in a state including other function units of various signal processing units such as the pixel array unit 10, the drive control unit 7, and the column AD conversion unit 26 is provided. It is good also as the modular form which has. Other functional units include, for example, an optical system such as a photographing lens, an optical low-pass filter, or an infrared light cut filter.

  The horizontal scanning unit 12 and the vertical scanning unit 14 start a shift operation (scanning) in response to control signals CN1 and CN2 given from the communication / timing control unit 20. For this reason, for example, the row control line 15 includes various pulse signals for driving the unit pixel 3 (for example, a pixel reset pulse RST that defines an initialization control potential, a transfer pulse TRG that defines a transfer control potential, a vertical selection) Pulse VSEL, etc.).

  The system control unit 20b of the communication / timing control unit 20 includes a functional block of a timing generator TG (an example of a read address control device) and a functional block of a communication interface. The functional block of the timing generator TG supplies a clock necessary for the operation of each unit and a pulse signal with a predetermined timing. The functional block of the communication interface receives the master clock CLK0 supplied from the terminal 5a (external main control unit), and receives data instructing the operation mode supplied from the terminal 5b (external main control unit). The functional block of the communication interface further outputs data including information on the solid-state imaging device 1 to the external main control unit.

  The communication / timing control unit 20 outputs, for example, a horizontal address signal to the horizontal scanning unit 12 and a vertical address signal to the vertical scanning unit 14, and each of the scanning units 12 and 14 receives the corresponding row or column. Select. At this time, since the unit pixels 3 are arranged in a two-dimensional matrix, analog pixel signals (current signals) generated by the unit pixels 3 and output in the column direction via the vertical signal lines 19 are displayed in units of rows ( It is better to access and capture (vertical) scan reading (in column parallel). Furthermore, after this, the pixel signal is obtained by performing a (horizontal) scan reading in which the pixel signal (in this example, digitized pixel data) is accessed to the output side in the row direction which is the arrangement direction of the vertical columns. It is better to speed up the reading of pixel data.

  Of course, not only scan reading but also random access (particularly referred to as full random access) for reading out only the information of the necessary unit pixel 3 is possible by directly addressing the unit pixel 3 to be read out. It is also conceivable that only the row position is set as necessary, and random access (in particular, referred to as semi-random access) is performed to read out signals at once for all pixels on the same line. In the case of this embodiment, column reading is performed, so it is preferable to apply semi-random access rather than full random access.

  In the present embodiment, during the averaging process for the purpose of reducing the RTS noise, the accumulated signal is read a plurality of times and averaged for the unit pixel 3 (particularly referred to as the specific pixel 3a) having a large RTS noise. Thus, a technique of selectively suppressing noise of the specific pixel 3a is adopted. Further, during the selection process or the averaging process of the specific pixel 3a, the signal of the same pixel is read out a plurality of times, so that a structure in which signal charges are continuously accumulated in the unit pixel 3 after the signal is read out (so-called non-destructive) It is necessary to have a structure capable of reading. CMD pixels are typical for meeting such demands.

  Furthermore, in the present embodiment, at the time of averaging processing aiming to reduce RTS noise, a method of accessing the position of the specific pixel 3a by applying random access is adopted. However, it is not essential to apply random access. When the pixel position is scanned in order and the position where the specific pixel 3a exists, the signal is read and averaged multiple times for the specific pixel 3a. You may make it perform. However, in this case, there is a problem that it takes more processing time than when random access is applied.

  Further, in the communication / timing control unit 20, a clock synchronized with an input clock CLK0 (master clock) input via the terminal 5a is used for each unit in the device, for example, the horizontal scanning unit 12, the vertical scanning unit 14, and the column AD conversion unit. 26 and the like.

  The AD clocks CKcnt1 are commonly supplied to the AD converters 250 of the column AD converter 26, receive the analog pixel signal voltage Vx of the unit pixel 3 in the corresponding column, and process the pixel signal voltage Vx. To do. For example, each AD converter 250 includes an ADC (Analog Digital Converter) circuit that converts the pixel signal voltage Vx into digital data using the count clock CKcnt1.

  As an AD conversion process in the column AD conversion unit 26, analog signals (pixel signal voltages Vx) held in parallel in units of rows are converted in parallel for each row using the AD conversion unit 250 provided for each column. A method of AD conversion is adopted. At this time, a reference signal comparison type AD conversion technique is used. Since this method can realize an AD converter with a simple configuration, it has a feature that the circuit scale does not increase even if it is provided in parallel.

[Details of column AD circuit and reference signal generator]
In the reference signal comparison type AD conversion, the count operation valid period (a signal indicating the period is referred to as a count enable signal EN) based on the time from the conversion start (comparison process start) to the conversion end (comparison process end). ) And the analog processing target signal is converted into digital data based on the count enable signal EN.

  As the count operation effective period, when the AD conversion unit 250 performs the difference process between the first phase conversion result and the second phase conversion result, various methods can be employed. For example, generally, at the time of processing of each phase, the count start is the change start time of the reference signal SLP_ADC, and the count end is the time when the reference signal SLP_ADC and the signal voltage to be processed coincide (effectively crossing time: The same example can be taken. In this case, in the first-phase / second-phase count processing for acquiring the digital data Dsig of the signal component Vsig of one pixel, the counter is operated by switching between the down-count operation and the up-count operation.

  Alternatively, when the AD converter 250 performs difference processing between the first phase component and the second phase component, the following second processing example may be employed. In one of the processes of each phase, the count start is set as the change start time of the reference signal SLP_ADC, and the count end is set as the time when the reference signal SLP_ADC matches the processing target signal voltage. On the other hand, the count start is the time when the reference signal SLP_ADC coincides with the signal voltage to be processed, and the count end is the time when the desired count is reached (typically, when the maximum AD conversion period is reached). In this case, the counter only needs to operate in one of the down-count operation and the up-count operation in the first-phase / second-phase count processing.

  As a way of thinking, it is also conceivable to perform difference processing between the first phase component and the second phase component in the subsequent stage of the AD conversion unit 250 (for example, the digital calculation unit 29). In this case, the following third processing example can be taken. In each phase processing, the count start is set as the change start time of the reference signal SLP_ADC. When the count ends when the reference signal SLP_ADC and the processing target signal voltage match, or when the count starts when the reference signal SLP_ADC and the processing target signal voltage match, and when the count end reaches the desired count of that time ( Typically, when the maximum AD conversion period is reached. In this case, the counter only needs to operate in one of the down-count operation and the up-count operation in the first-phase / second-phase count processing.

  The third processing example is not taken when the AD converter 250 completes the difference process. However, the first phase data and the second phase data may be individually transferred to the output unit 28 side, and the difference process may be performed at the subsequent stage of the AD conversion unit 250 (for example, in the digital calculation unit 29).

  Although three processing examples have been described here, various reference signal comparison type AD conversion methods in which the AD conversion unit 250 performs AD conversion and difference processing (for example, CDS processing) are also known. Basically, they can also be adopted in the embodiments described later.

  In any processing example, in principle, a ramp-like reference signal SLP_ADC is supplied to a comparator (voltage comparator), and an analog pixel signal voltage Vx input via the vertical signal line 19a is used as a reference signal SLP_ADC. Compare with In this process, when the count operation valid period is entered, the clock signal starts counting (counting), and the AD conversion is performed by counting the number of clocks in the designated count operation valid period.

  The AD conversion unit 250 includes a comparison unit 252 (COMP: comparator) and a counter unit 254. The comparison unit 252 provides an analog pixel signal obtained from the unit pixel 3 via the vertical signal lines 19 (H1, H2,..., Hh) for each of the reference signal SLP_ADC generated by the reference signal generation unit 27 and the row control line 15. Compare The counter unit 254 counts the active period of the count enable signal EN having a fixed relationship with the time until the comparison unit 252 completes the comparison process, using the count clock CKcnt1, and holds the count result.

  The reference signal generation unit 27 includes a DA conversion unit 270 (DAC: Digital Analog Converter). The reference signal generation unit 27 generates a stepped sawtooth wave (ramp waveform; hereinafter also referred to as reference signal SLP_ADC) in synchronization with the count clock CKdac1 from the initial value indicated by the control data CN4 from the communication / timing control unit 20. It is generated by the DA conversion unit 270. The reference signal generation unit 27 supplies the generated stepped sawtooth reference signal SLP_ADC to each AD conversion unit 250 of the column AD conversion unit 26 as a reference voltage (ADC standard signal) for AD conversion. It has become. Although illustration is omitted, a noise prevention filter may be provided. The count clock CKdac1 may be the same as the count clock CKcnt1 for the counter unit 254.

  The control data CN4 supplied from the communication / timing control unit 20 to the DA conversion unit 270 of the reference signal generation unit 27 corresponds to the time so that the reference signal SLP_ADC for each comparison process basically has the same slope (rate of change). It also includes information that makes the rate of change of digital data the same. Specifically, using an output type DA converter circuit, the count value is changed by 1 every unit time in synchronization with the count clock CKdac1, and a current corresponding to the count value is output. . Then, the current signal is converted into a voltage signal by a resistance element for current-voltage conversion.

  In the column AD conversion processing, the reference signal SLP_ADC is commonly supplied from the DA conversion unit 270 to the comparison unit 252 arranged for each column, and the common reference signal is used for the pixel signal voltage Vx that each comparison unit 252 is responsible for processing. Perform comparison using SLP_ADC. The counter unit 254 performs count processing based on the count clock CKcnt1 during the active period (when H level) of the count enable signal EN, and holds the count result at the end of the count processing.

  A control signal CN5 for instructing various control information is input from the communication / timing control unit 20 to the counter unit 254 of each AD conversion unit 250. The control signal CN5 is, for example, whether the counter unit 254 operates in the down-count mode or the up-count mode for the first-phase / second-phase count process, the initial value Dini in the first-phase count process, Instructs reset processing and the like.

  One input terminal (+) of the comparator 252 receives the reference signal SLP_ADC generated by the reference signal generator 27 in common with the input terminal (+) of the other comparator 252. In the comparison unit 252, the vertical signal lines 19a of the corresponding vertical columns are connected to the other input terminals (−), respectively, and the pixel signal voltages Vx subjected to current-voltage conversion by the current-voltage conversion unit 24 are individually input. The

  The count clock CKcnt1 from the communication / timing control unit 20 is input to the clock terminal CK of the counter unit 254 in common with the clock terminals CK of the other counter units 254. The counter unit 254 is not illustrated in the configuration, but can be realized by changing the wiring form of the data storage unit configured by a latch to a synchronous counter form or a ripple counter form, and an input of one count clock CKcnt1 The internal count is performed.

  The counter unit 254 takes a first processing example in which the down-count operation and the up-count operation are switched in the first-phase / second-phase count processing for acquiring the digital data Dsig of the signal component Vsig of one pixel. obtain. In this case, it is preferable to use an up / down counter capable of switching between a down count operation and an up count operation.

  On the other hand, in the case of the second processing example and the third processing example in which only one of the down-counting operation and the up-counting operation needs to be performed in the first-phase / second-phase counting processing, this corresponds to the operation. Either an up counter or a down counter is sufficient. However, in principle, as an application form, an up / down counter capable of switching between a down count operation and an up count operation may be used to operate either the down count operation or the up count operation. However, normally, an up / down counter requires a circuit configuration for mode switching, and the circuit scale is larger than a configuration corresponding to only a single count mode such as an up counter or a down counter. For this reason, it is better not to employ an up / down counter when only one of them needs to be operated.

  A control pulse is input to the counter unit 254 from the horizontal scanning unit 12 through the control line 12c. The counter unit 254 has a latch function for holding the count result, and holds the counter output value until an instruction by a control pulse through the control line 12c is given.

  For example, the output side of each AD conversion unit 250 can connect the output of the counter unit 254 to the horizontal signal line 18. Alternatively, as shown in the figure, a data storage unit 256 (memory device) having a latch that holds the count result held by the counter unit 254 at the subsequent stage of the counter unit 254, and between the counter unit 254 and the data storage unit 256 It may be configured to include a switch unit 258 arranged in the. The switch unit 258 has a switch SW for each vertical column.

  In the case of the configuration including the data storage unit 256, the memory transfer instruction pulse CN 8 as a control pulse is supplied to the switch SW from the communication / timing control unit 20 at a predetermined timing in common with the switches SW in the other vertical columns. Is done. When the memory transfer instruction pulse CN8 is supplied, the switch SW of the switch unit 258 transfers the count value of the corresponding counter unit 254 to the data storage unit 256. The data storage unit 256 holds and stores the transferred count value.

  The mechanism for holding the count value of the counter unit 254 in the data storage unit 256 at a predetermined timing is not limited to the configuration in which the switch unit 258 is arranged therebetween. For example, it can be realized by controlling the output enable of the counter unit 254 with the memory transfer instruction pulse CN8 while directly connecting the counter unit 254 and the data storage unit 256. This can also be realized by using the memory transfer instruction pulse CN8 as a latch clock for determining the data take-in timing of the data storage unit 256.

  A control pulse is input to the data storage unit 256 from the horizontal scanning unit 12 through the control line 12c. The data storage unit 256 holds the count value fetched from the counter unit 254 until there is an instruction by a control pulse through the control line 12c.

  The horizontal scanning unit 12 reads the count value held by each data storage unit 256 in parallel with each comparison unit 252 and counter unit 254 of the column AD conversion unit 26 performing the processing that they are responsible for. It has the function of a readout scanning unit.

  The output of the data storage unit 256 is connected to the horizontal signal line 18. The horizontal signal line 18 has a signal line corresponding to the bit width of the AD conversion unit 250 or a double width thereof (for example, complementary output), and an output unit 28 having a sense amplifier 28a corresponding to each output line. Connected to.

  If the data storage unit 256 is provided, the count result held by the counter unit 254 can be transferred to the data storage unit 256. Therefore, the counting operation of the counter unit 254, that is, the AD conversion processing and the reading operation of the count result to the horizontal signal line 18 can be controlled independently, and the AD conversion processing and the signal reading operation to the outside are performed in parallel. The pipeline operation to be performed can be realized.

  In such a configuration, the AD conversion unit 250 performs a count operation in a predetermined pixel signal readout period and outputs a count result at a predetermined timing. That is, first, the comparison unit 252 compares the reference signal SLP_ADC from the reference signal generation unit 27 with the pixel signal voltage Vx input via the vertical signal line 19a. When both voltages become the same, the comparison output Co (comparative output) of the comparison unit 252 is inverted. For example, the comparison unit 252 sets the H level such as the power supply potential to the inactive state, and transitions to the L level (active state) when the pixel signal voltage Vx matches the reference signal SLP_ADC.

  The counter unit 254 uses the comparison output Co from the comparison unit 252 as the count enable signal EN. The counter unit 254 completes AD conversion by latching (holding / storing) the number of count clocks CKcnt1 during the period when the count enable signal EN is active (the period when the comparison output Co of the comparison unit 252 is H) as pixel data. .

  The communication / timing controller 20 generates a reference signal so that it performs AD conversion with n bits during normal AD conversion processing, and performs W digital conversion with n bits during multi-addition AD conversion processing. The unit 27 and the counter unit 254 are controlled. To cope with this, in the present embodiment, the counter unit 254, the data storage unit 256, the switch unit 258, and the horizontal signal line 18 each have a configuration corresponding to “n + M” bits.

  Here, the number of times W when the reference signal comparison type AD conversion processing is repeated a plurality of times and the number of bits M incremented from n bits for the counter unit 254 are “2 ^ (M−1) <W ≦ 2 ^. M ”is satisfied. For example, when the number of repetitions W is 2, it is increased by 1 bit, when the number of repetitions W is 3 or 4, it is increased by 2 bits, and when the number of repetitions W is 5-8, it is increased by 3 bits. . When the reference signal comparison type AD conversion process is repeated W times, the digital data of the signal is multiplied by W, and is defined from the relationship of the number of bits necessary to process this without problems.

[Reference signal generator]
FIG. 2 is a diagram illustrating a configuration example of the DA conversion unit 270 of the reference signal generation unit 27 used in the solid-state imaging device 1. The DA conversion unit 270 includes a current source unit 302 configured by a combination of constant current sources, a counter unit 312, an offset generation unit 314, a current source control unit 316, and a reference current source that sets a reference current value I_0. The unit 330 includes a current output type DA converter circuit. A resistance element 340 having a resistance value R_340 is connected to the current output terminal of the current source unit 302 as an element for current-voltage conversion.

  The current source unit 302 includes a constant current source 304 that outputs a predetermined specified current value. How to set the current value of each constant current source 304 of the current source unit 302 and how to control the arrangement are various. Here, for ease of understanding, as an example, the constant current source 304 includes constant current sources 304 for bits, and each constant current source 304 has a reference current value I_0 set by the reference current source unit 330. It is assumed that a current having a bit weight is output.

  For example, in the case of 13-bit correspondence, the 0-bit constant current source 304_0 is 2 ^ 0 × I_0, the 1-bit constant current source 304_1 is 2 ^ 1 × I_0,..., The 11-bit constant current source 304_11 is 2 ^ 11 × I_0, 12th bit constant current source 304_12 outputs 2 ^ 12 × I_0. “^” Indicates a power. The current output terminals of the constant current source 304 are connected in common, and are further connected to a reference power source Vref corresponding to the initial potential SLP_ini of the reference signal SLP_ADC via the resistance element 340. The reference power supply Vref is set based on information indicating the initial value of the reference signal SLP_ADC for each comparison process included in the control data CN4. What is the circuit configuration for setting the reference power supply Vref? There may be.

  The reference current source unit 330 includes a constant current source 332, a Pch-type transistor 334 serving as a load of the constant current source 332, a gain changing unit 336, and the current output from the gain changing unit 336 in each current source unit 302. An Nch transistor 338 is provided to the constant current source 304. The constant current source 332 generates an initial current Iini having one end connected to a negative power supply or ground. The transistor 334 has a source connected to a positive power supply, a drain and a gate commonly connected to the output terminal of the constant current source 332, and a current mirror connection with a transistor (not shown) of the gain changing unit 336.

  The gain changing unit 336 supplies a reference current value I_0 obtained by multiplying the mirror current from the transistor 334 by a predetermined value to the transistor 338, although details thereof are not shown. The transistor 338 has a source connected to a negative power supply or ground, a drain and a gate commonly connected to the output terminal of the gain changing unit 336, and a current mirror connection to each constant current source 304 of the current source unit 302.

  The gain changing unit 336 sets the voltage change ΔSLPdac (= I_0 × R_340) per clock based on the information indicating the slope of the reference signal SLP_ADC for each comparison process included in the control data CN4, and count clock The count value is changed by 1 for each CKdac. Actually, it is only necessary to set the maximum voltage width for the maximum count number (for example, 1024 in 10 bits) of the count clock CKdac. By changing the gain for the initial current amount Iini of the constant current source 332 of the reference current source unit 330, ΔSLPdac per clock is adjusted, and as a result, the slope (rate of change) of the reference signal SLP_ADC is adjusted.

  The counter unit 312 performs a counting operation based on the count clock CKdac1 from the communication / timing control unit 20, and supplies the count result to the current source control unit 316. The offset generation unit 314 gives a constant potential to the reference signal SLP_ADC separately from the change based on the count value of the counter unit 312, and supplies the information to the current source control unit 316. The constant potential is “offset”. The current source control unit 316 determines which constant current source 304 is to be turned on / off based on the count value of the counter unit 312 and the offset amount information from the current source control unit 316, and determines the constant current source based on the determination result. The current source 304 is turned on / off.

  In order to facilitate understanding, hereinafter, the offset amount is assumed to be zero unless otherwise specified. Therefore, each time the count value of the counter unit 312 advances, the DA conversion unit 270 changes the voltage by ΔSLPdac for each count clock CKdac1 from the voltage indicating the initial value included in the control data CN4. If the up-counting operation is performed, the voltage decreases by ΔSLPdac so that it has a negative slope. If the down-counting operation is performed, the voltage increases by ΔSLPdac, and thus the positive slope.

  The configuration of the reference signal generation unit 27 shown here is merely an example, and the method of adjusting the slope of the reference signal SLP_ADC is not limited to such a method. For example, it is only necessary to include α (initial value) and slope (change rate) β in the control data CN4 and to generate a reference signal SLP_ADC that satisfies the function y = α−β * x, and the reference signal can be used without using the counter unit 312. The generation unit 27 may be configured. However, the configuration using the counter unit 312 has an advantage that the generation of the reference signal SLP_ADC is easy and the operation with the counter unit 254 can be easily taken.

  For example, a configuration is possible in which the counter output value is x and the potential calculated by y = α−β * x is output while the period of the count clock CKdac given to the reference signal generator 27 is constant. At this time, the adjustment of the voltage change ΔSLPdac (that is, the inclination β of the reference signal SLP_ADC) for each count clock CKdac based on the information indicating the inclination β is realized by changing the number of clocks, for example. In addition, ΔSLPdac per clock can be adjusted by changing the resistance value for current-voltage conversion or changing the amount of current of the unit current source.

<Basic operation of solid-state imaging device>
3 to 3B are diagrams for explaining the basic operation of the solid-state imaging device 1. Here, FIG. 3 is a simple circuit configuration diagram of the solid-state imaging device 1 focusing on AD conversion processing and difference processing. FIG. 3A is an image diagram for explaining the operation of multiple addition AD conversion. FIG. 3B is a timing chart illustrating multiple addition AD conversion and digital difference processing in the solid-state imaging device 1. Here, although the case where difference processing is used together is described, it is not essential to use difference processing together.

  As shown in FIG. 3, the pixel array unit 10 arranges CMD3_1,1 to CMD3_h, v as unit pixels 3 in a matrix, and a video voltage Vd (> 0) is commonly applied to each drain terminal. ing. The gate terminals of the CMD groups in each row arranged in the horizontal direction are connected to the row control lines 15_1 to 15_v, respectively, and the source terminals of the CMD groups in each column arranged in the vertical direction are connected to the vertical signal lines 19_1 to 19_h, respectively. ing.

  The vertical signal lines 19_1 to 19_h are connected to the P-type switch transistors 33 (PMOS: in detail, the reset transistor 34, the light transistor 36, and the dark transistor 38) for reset, light, and dark, respectively. Has been. The opposite side of the vertical signal line 19 of the reset transistor 34 is connected to the reset line 57, and the opposite side of the bright transistor 36 and the dark transistor 38 to the vertical signal line 19 is connected to the current-voltage converter 24.

  Each switch transistor 33 has a gate connected to the vertical scanning unit 14 or the system control unit 20b of the communication / timing control unit 20, and is supplied with corresponding control signals φrst, φlight, and φdark, respectively.

  Although detailed description is omitted, when the readout period of the horizontal blanking period starts, the light transistor 36 or the dark transistor 38 is turned on, so that the source terminal of the CMD3_i, j and the current-voltage converter 24 are connected and selected. The source currents of the respective CMD3_i, j in the row i are simultaneously input to the current-voltage conversion unit 24 (current-voltage conversion circuit 24a (I → V)) and converted into the pixel signal voltage Vx.

  In this example, a light transistor 36 and a dark transistor 38 are provided, and a difference process is performed in the current mode at the time of current-voltage conversion so that the pixel signal voltage Vx from which fixed pattern noise has been removed is obtained. It is also possible. If difference processing in the current mode is not necessary, it is sufficient to have either the light transistor 36 or the dark transistor 38.

[Normal AD conversion processing]
In the AD conversion unit 250, first, the analog pixel signal voltage Vx output from the current-voltage conversion unit 24 is compared with the reference signal SLP_ADC by the comparison unit 252 of the AD conversion unit 250 arranged for each vertical signal line 19a. At this time, similarly to the comparison unit 252, the counter unit 254 arranged for each column is operated based on the count enable signal EN. Then, the pixel signal voltage Vx of the vertical signal line 19a is converted into digital data by changing a potential of the reference signal SLP_ADC and the counter unit 254 while taking a one-to-one correspondence.

  Here, in the conventional mechanism, first, during the processing of the first phase signal, that is, in the first phase processing period that is the AD conversion period for the first phase level S_1st, the count of each flip-flop of the counter unit 254 is counted. The value is reset to the initial value “0”. Then, by setting the counter unit 254 to the down-count mode, the comparison process between the reference signal SLP_ADC by the comparison unit 252 and the first phase level of the pixel signal voltage Vx and the count process by the counter unit 254 are operated in parallel. The AD conversion at the first phase level is performed. Thereby, the counter unit 254 holds a count value indicating the digital value (first phase data) D_1st corresponding to the magnitude of the first phase level S_1st (indicating -D_1st if the sign is added).

  During the subsequent processing of the second signal, that is, the second phase processing period, which is the AD conversion period for the second phase level S_2nd, the incident light amount for each unit pixel 3 is added to the first phase level S_1st. The corresponding signal component Vsig is read, and the same operation as the first phase reading is performed. First, the counter unit 254 is set to an up-count mode opposite to that in the first phase process, and the comparison process between the reference signal SLP_ADC and the second phase level of the pixel signal voltage Vx by the comparison unit 252 and the count by the counter unit 254 are performed. Operate processes in parallel. As a result, AD conversion at the second phase level is performed.

  At this time, the digital value (first phase data) D_1st of the first phase level S_1st of the pixel signal voltage Vx acquired at the time of reading and AD conversion of the first phase is used as the start point, and up-counting is performed in reverse to the first phase. . Since the second phase level S_2nd is a level obtained by adding the signal component Vsig to the first phase level S_1st, the count value of the AD conversion result of the second phase level S_2nd is basically “D_1st + D_2nd”. However, since the start point of the upcount is “−D_1st” that is the AD conversion result of the first phase level S_1st, the count value actually held in the counter unit 254 is “−D_1st + (D_2nd + D_1st) = D_2nd”. It becomes.

  That is, the counting operation in the counter unit 254 is different in the count mode from down-counting during the first-phase processing and up-counting during the second-phase processing. Processing) is automatically performed. Difference processing is performed between the count number “−D_1st” which is the AD conversion result of the first phase level S_1st and the count number “D_1st + D_2nd” which is the AD conversion result of the second phase level S_2nd. The corresponding count number D_2nd is held in the counter unit 254. The count number D_2nd held in the counter unit 254 corresponding to the difference processing result represents the signal data corresponding to the signal component Vsig.

  In this manner, the unit pixel 3 varies depending on the difference processing in the counter unit 254 by two readings and counting processes, such as the down-counting in the first-phase process and the up-counting in the second-phase process. The first phase level S_1st including can be removed. An AD conversion result of only the signal component Vsig corresponding to the amount of incident light for each unit pixel 3 can be acquired with a simple configuration. Therefore, the AD conversion unit 250 operates not only as a digital conversion unit that converts an analog pixel signal into digital pixel data but also as a functional unit for differential processing such as CDS (correlated double sampling) processing. .

[Multiple addition AD conversion processing]
On the other hand, in this embodiment, as shown in FIG. 3A, the relationship between the count modes of the first phase and the second phase within one horizontal scanning period is made the same as before. Further, the reference signal comparison type AD conversion processing is continuously performed a plurality of times (W times) for the same signal during each AD conversion processing of the first phase and the second phase. W is a positive integer greater than or equal to 2, and FIG. 3A (1) shows the case of W = 2, and FIG. 3A (2) shows the case of W = 3.

  Preferably, in the second and subsequent processing, the method of changing the reference signal SLP_ADC for AD conversion is the same as that in the first time, and the previous AD conversion result is used as the start point and count processing is performed in the same count mode. .

  By doing so, in each process of the first phase and the second phase, data (addition data) obtained by multiplying the AD conversion result of the same signal by W is obtained. A combination of reversing the count mode in the first phase and the second phase results in an operation result of “−W · D — 1st + W · (D — 2nd + D — 1st) = W · D — 2nd”. It can be understood that the counter unit 254 functions as a digital integrator. Since the signal is multiplied by W, but the noise is considered to be multiplied by √W, the noise characteristic is improved. Random noise can be reduced without the problem of dynamic range such as analog addition.

  If W · D_2nd is used as it is, the dynamic range can be expanded as output data. This means that an image obtained by adding the same image a plurality of times can be obtained by executing only the addition by executing the reference signal comparison type AD conversion processing a plurality of times for each of the first phase and the second phase. Even with the same gain setting, data with a double range can be acquired. For example, regarding the reference signal comparison type AD conversion processing of the first phase and the second phase, processing is performed once as usual when shooting at normal brightness, but the same signal is used when shooting under low illumination. By performing the W times of processing, it is possible to expand the imageable range on the low illuminance side. For an application that requires data of the same size as the original level, it is only necessary to average the added data W · D_2nd multiplied by W, that is, to perform an addition average.

  As can be seen from this, the AD conversion unit 250 obtains the added data W · D_2nd that is W times the bit width n when the present embodiment is not applied. When the number of repetitions W satisfies “2 ^ (M−1) <W ≦ 2 ^ M”, the counter unit 254, the data storage unit 256, the switch unit 258, and the horizontal signal line 18 are each “n + M”. A configuration corresponding to bits (M is a positive integer of 1 or more) is required (see FIG. 1). For example, when n = 12, M = 1, and W = 2, the counter unit 254, the data storage unit 256, the switch unit 258, and the horizontal signal line 18 each need a configuration corresponding to 13 bits.

  For example, FIG. 3B also shows the counter output when W = 2. First, at the time of the first phase processing, the count value of each flip-flop of the counter unit 254 is reset to the initial value “0”. Then, the counter unit 254 is set to the down-count mode, and the comparison process between the reference signal SLP_ADC and the first phase level S_1st by the comparison unit 252 and the count process by the counter unit 254 are operated in parallel. Level AD conversion is performed. Thus, the counter unit 254 that has completed the first process holds a count value indicating the digital value D_1st corresponding to the magnitude of the first phase level S_1st (indicating a sign, indicating −D_1st).

  In the subsequent second processing of the first phase, the digital value D_1st (here, a negative value) of the first phase level S_1st for the first time is used as a start point. Then, in the same down-count mode as the first time, the comparison process between the reference signal SLP_ADC and the first phase level S_1st by the comparison unit 252 and the count process by the counter unit 254 are operated in parallel, so that the first phase of the second time Level AD conversion is performed. As a result, the digital value 2 · D_1st corresponding to twice the magnitude of the first phase level S_1st is shown in the counter unit 254 after the second processing is completed (-2 · D_1st is shown if the sign is added). The count value is held. That is, for the first phase, the reference signal comparison type AD conversion process that is performed twice consecutively is held in the counter unit 254 as a negative count.

  In the subsequent second phase processing, the digital value 2 · D_1st (here, a negative value) corresponding to the first phase level S_1st of the pixel signal voltage Vx obtained during the first phase reading and AD conversion. Is the starting point. Then, in the up-count mode opposite to the first phase, the comparison process between the reference signal SLP_ADC and the second phase level S_2nd by the comparison unit 252 and the count process by the counter unit 254 are operated in parallel, so that the first time Second-phase level AD conversion is performed. Thus, the counter unit 254 that has completed the first process of the second phase holds a count value indicating “−2 · D_1st + (D_2nd + D_1st) = − D_1st + D_2nd”.

  In the second process of the second phase, the first count result (-D_1st + D_2nd) is used as a start point. Then, in the same up-count mode as the first time, the comparison process between the reference signal SLP_ADC and the second phase level S_2nd by the comparison unit 252 and the count process by the counter unit 254 are operated in parallel, so that the second phase of the second time Level AD conversion is performed. As a result, the counter unit 254 that has completed the second processing holds a count value indicating “−D_1st + D_2nd + (D_2nd + D_1st) = 2 · D_2nd”.

  As described above, in the present embodiment, the reference signal comparison type AD conversion processing in the down-count mode continued W times for the first phase is performed, and then the reference signal in the up-count mode continued W times for the second phase. A comparative AD conversion process is performed. By doing so, the addition operation processing of the data for W times for the first phase (a negative value when the sign is added) and the data for W times for the second phase is performed. The same first phase level S_1st and second phase level S_2nd can be differentially processed and added. Such AD conversion and difference processing by sampling W times are referred to as multiple addition AD conversion processing, digital integration processing, W addition AD conversion processing, W integration AD conversion processing, and the like.

  The addition data W · D_2nd obtained by the multiple addition AD conversion processing is sent to the output unit 28 by horizontal transfer. In the output unit 28, the digital arithmetic unit 29 divides by W by digital signal processing to obtain the addition averaged data D_2nd. Since the signal component is W times, but the random noise is √W, the noise characteristic (S / N) can be improved. In such multiple addition AD conversion processing, quantization noise and random noise can be reduced without worrying about a dynamic range such as analog addition. Further, as described above, if the application is performed by adding a digitized signal that is used as W · D — 2nd without taking the averaging, it is possible to increase the gain and expand the dynamic range.

<RTS Noise Suppression Processing: First Embodiment>
4 to 4B are diagrams illustrating the first embodiment of the RTS noise suppression process that is the greatest feature in the image acquisition method of the present embodiment. Here, FIG. 4 is a diagram for explaining the RTS noise. FIG. 4A (1) is a flowchart for explaining the basic principle of the RTS noise suppression processing of this embodiment, and FIG. 4A (2) is a timing chart at the vertical scanning rate. FIG. 4B is a diagram illustrating an example in which the RTS noise suppression process of the present embodiment is applied.

  In image sensors, it has been pointed out that RTS noise becomes apparent as pixels are reduced. RTS noise is caused by random capture and emission of electrons due to the interface state of the gate oxide film of the MOS transistor. Conventional 1 / f noise is observed by superimposing RTS noise with various time constants. It is thought that That is, each unit pixel 3 has a MOS transistor as an element driven as a source follower, but when an energy level exists in a channel portion in silicon Si immediately below the gate and electrons flow from the source to the drain. Furthermore, it is considered that this phenomenon appears as noise in the signal value due to the influence of this energy level. When there are a plurality of energy levels, RTS noise is detected as 1 / f noise and a relatively large noise is generated due to the influence of one energy level. Many white grain noises appear as a phenomenon that occurs randomly. Under the influence of the RTS noise, the noise is conspicuous in the image, and sensuously becomes unpleasant noise.

  FIG. 4 schematically shows the state of the RTS noise. In the figure, the horizontal axis represents time, and the vertical axis represents the magnitude of RTS noise. As shown in the figure, the magnitude of the RTS noise varies both positively and negatively with respect to the signal value. Noise appears as an image in response to this shake, and is noticeable because the noise level is high.

  Conventionally, as a technique for suppressing RTS noise, the main focus has been on improving the device structure, and any of them is a process technology that does not generate even one energy level in the channel portion. I can say that. For example, as with 1 / f noise countermeasures, gate area expansion, gate oxide film thinning, PMOS conversion, gate oxide film itself improved noise reduction technique, pixel source follower embedded channelization (effect of interface state The method to make it difficult to receive) is considered. However, in reality, RTS noise has not been completely suppressed yet.

  Therefore, this embodiment proposes a technique for suppressing RTS noise from the aspect of signal processing, not from the aspect of device structure.

[Basic principle]
The RTS noise suppression process of the present embodiment employs a technique for simultaneously solving “asynchrony”, “resolution reduction”, and “large signal processing load”. Here, the first embodiment is characterized in that a series of processes including a process target pixel specifying process and a random noise suppressing process are performed for each exposure. The procedure will be described with reference to the flowchart shown in FIG. 4A (1) and the timing chart shown in FIG. 4A (2).

  First, a device capable of nondestructive and random reading is used as a device (pixel array unit 10) to be imaged (S100). In the present embodiment, the solid-state imaging device 1 includes the pixel array unit 10 including a CMD element that satisfies such requirements.

  Then, the signal accumulated in one exposure is read out a plurality of (m) times (S114), and the AD conversion result of each time is transferred to the digital operation unit 29. The digital calculation unit 29 calculates the variation of the m AD conversion results (S116), and selects the unit pixel 3 having a large variation as the specific pixel 3a (S118). The process from step S114 to step S118 is referred to as a process target pixel specifying process S11.

  At the time of signal reading each time, it is preferable to suppress noise accompanying AD conversion by applying the above-described multiple addition AD conversion processing. Of course, the combined use of the multiple addition AD conversion processing is not essential for the RTS noise suppression processing of the present embodiment.

  Here, there is no random noise if the signal values are the same for each of a plurality of readings. However, if there is a variation in the signal value, the portion where the noise amount is large is considered to be RTS noise, and the variation amount. Is the RTS noise level. Then, a comparison process with a predetermined reference value (threshold value Th_1) is performed, and if the level of the RTS noise exceeds the threshold value Th_1 (or more), the unit pixel 3 is treated as the specific pixel 3a, and the pixel position (Address data) is stored in a predetermined storage device (memory). In this case, the storage device need not be nonvolatile (data can be retained even when the power is turned off).

  For example, the 1st method of managing the positional information on the specific pixel 3a in the main control part outside the solid-state imaging device 1 can be considered. Alternatively, a second method in which a storage unit is provided in the solid-state imaging device 1 and managed by the system control unit 20b is also conceivable. In the case of the first embodiment in which a series of steps are performed for each exposure, it is considered that the second method that can be dealt with on the solid-state imaging device 1 side is preferable after the processing is started.

  Thereafter, the accumulated signal is read a plurality of (M) times for the specific pixel 3a (S126), and the AD conversion result of each time is transferred to the digital operation unit 29. M is preferably a value larger than m. The digital arithmetic unit 29 takes the average value (simple addition average) of the M AD conversion results and sets it as the pixel signal of the specific pixel 3a (S128). The processing from step S126 to step S128 is collectively referred to as random noise suppression processing S12.

  By averaging the read signals M times for the same pixel by the random noise suppression process S12, RTS noise with a large noise level that is randomly generated in the specific pixel 3a can be compressed, and the image quality S / N is improved. can do. That is, the noise of the specific pixel 3a having a large RTS noise can be selectively suppressed.

  At this time, since the column readout method is adopted in this embodiment, a plurality of specific pixels 3a on the same line can be processed simultaneously. In addition, the RTS noise suppression process can be applied not only to a plurality of specific pixels 3a on the same line, but also to unit pixels 3 originally present on the same line as the specific pixel 3a and having little RTS noise.

  Since the signal accumulated in one exposure is read many times (M times) in a non-destructive manner, “simultaneity” is ensured. In addition, since the processing is performed independently for each pixel, the “resolution” is not reduced. Further, since only the specific pixel 3a having a large RTS noise is selected or only the line (row) in which the specific pixel 3a having a large RTS noise exists is selected, the “signal processing load” is reduced. Is possible.

  For the unit pixel 3 that is not selected as the specific pixel 3a, the first method using any of the m times of information read in step S114 or the m times of averaging is used. Any of the second methods may be used. In the second method, the noise of the entire image is suppressed by the addition averaging for m times, while the processing time and circuit scale for the addition averaging increase. In contrast, the first method does not function to suppress the noise of the entire image, but there is no difficulty in increasing the processing time and circuit scale for the averaging of the m times.

  In addition, when compared with the normal imaging method that does not perform the RTS noise suppression process of the present embodiment, the entire processing cycle is performed by performing m processing target pixel specifying processes S11 and random noise suppressing processes S12. Will be added.

  For example, as shown in FIG. 4A (2-1), the entire process in the case where the normal image acquisition process S102 is simply repeated m times to obtain the process target pixel specifying process S11 and then the random noise suppression process S12 is performed. The time is longer in each stage than in normal processing. Although still image capturing may be permitted, a waiting time until the next still image capturing is required, and some improvement is desired.

  As a countermeasure for this, for example, as shown in FIG. 4A (2-2), it is conceivable to set the processing target pixel specifying process S11 by repeating signal reading m times in the same period as the normal image acquisition process S102. . In this case, however, m times of signal readout must be performed at a higher speed (preferably m times) than usual.

  Also, the random noise suppression processing S12 is added to the processing target pixel identification processing S11 (= normal image acquisition processing S102) in the same manner as shown in FIG. 4A (2-1). At this time, if the amount of random noise suppression processing S12 does not fall within the normal vertical blanking period (FIG. 4A (2-2b)), for example, it is necessary to lengthen the vertical blanking period. Processing time will be longer than usual.

  For example, even when M signals are read out at a higher speed than normal (preferably M times), if the number of specific pixels 3a having a large RTS noise increases, the amount of random noise suppression processing S12 becomes normal. It may happen that it does not fit within the vertical blanking period. In this case, the period of the random noise suppression process S12 is set as the vertical blanking period BLK1 longer than the normal vertical blanking period.

  As a countermeasure for this, for example, as shown in FIG. 4A (2-3), in step S118, the specific pixel 3a may be selected within the range of the threshold Th_2 regarding the number to be accommodated within the normal vertical blanking period. It is done. If the number of the specific pixels 3a is made to coincide with the threshold Th_2, the period of the random noise suppression process S12 coincides with the normal vertical blanking period.

  In this case, some of the selected specific pixels 3a may be below the threshold value Th_1 regarding the noise level. In order to increase the number of selected specific pixels 3a, it is necessary to increase the threshold value Th_2. In practice, M times of signal reading in the random noise suppression process S22 should be performed at a speed higher than normal. Necessary.

  With the method shown in FIG. 4A (2-3), m signals are read out in the processing target pixel specifying process S11 (preferably, M signals are read out in the random noise suppression process S12) faster than usual. However, it is thought that it can cope with moving image capturing. RTS noise is more problematic for moving images than for still images, but the problem can be solved by applying the method shown in FIG. 4A (2-3).

[Case]
FIG. 4B shows an application example of the basic principle of the RTS noise suppression process (noise compression method) of the present embodiment.

  The horizontal axis of the figure is linear and indicates the random noise level of the pixel, and the vertical axis is the logarithm and indicates the number of pixels having the noise in one chip. The noise level is a variation amount obtained from the designated number of captured images.

  The tail portion of the distribution (tailing with a large noise level) that becomes noticeable when the number of captured images is small is mainly due to RTS noise. Incidentally, the peak part is considered to be 1 / f noise.

  First, a signal is accumulated in each unit pixel 3 in one exposure in the pixel array section 10 having a CMD element that can be read nondestructively and randomly. The signal is read m times and the variation is calculated (S114 to S116). As an example, the double capture is indicated by an arrow line indicated by b, but there is a pixel with a large random noise level.

  A threshold Th_1 is provided for the random noise level, and the unit pixel 3 that is equal to or greater than the threshold Th_1 is selected (S118). In the figure, the threshold value Th_1 is set to 4, and the unit pixel 3 exceeding 4 is shown surrounded by an arrow line indicated by B in the figure, but there is a unit pixel 3 having a large random noise level. The unit pixel 3 surrounded by the arrow line indicated by B is selected as the specific pixel 3a.

  In this case, the number of selected specific pixels 3a is 1000 or less (up to 1000), which is very small in view of the total number of pixels of one chip.

  Next, the noise is compressed by reading out and averaging the signal M times only for the selected specific pixel 3a (S126 to S128). As an example, 16 times of capture is indicated by a line of arrows indicated by c. At this time, the noise level of the specific pixel 3a selected as the threshold Th_1 = 4 or more is compressed by the averaging process into a state surrounded by an arrow line indicated by C in the drawing. In the example shown in the figure, the noise level which is as large as 4 to 8.5 is almost halved to 2.5 to 4.5.

  In other words, when the specific pixel 3a indicated by the arrow B line whose variation of the signal read twice is greater than or equal to the threshold Th_1 is selected and the signal for the specific pixel 3a is read out 16 times and averaged, the arrow C indicates RTS noise can be suppressed as in the state surrounded by a line.

  In addition, since the averaging process at this time is selectively performed on the specific pixel 3a having a particularly high random noise level among the pixels in the chip, the signal processing load, specifically, the memory and the bandwidth are small. High-speed and inexpensive processing is possible.

  By such processing, the problems of the conventional random noise compression method, “non-simultaneousness”, “resolution reduction”, and “high signal processing load” have been solved. Noise in captured images, particularly random noise generated during reading, can be compressed while maintaining the resolution and maintaining the resolution, and the image quality can be improved. In addition, since subsequent signal processing can be performed with a light load, low cost and low power consumption can be realized.

  By using RTS noise suppression processing and multiple addition AD conversion processing together, it is possible to reduce random noise generated when reading out pixel signals, and to reduce quantization noise and random noise generated along with AD conversion. The overall noise can be greatly suppressed.

<RTS Noise Suppression Processing: Second Embodiment>
FIG. 5 is a diagram for explaining a second embodiment of the RTS noise suppression process of the present embodiment. Here, FIG. 5 (1) is a flowchart for explaining the basic principle of the RTS noise suppression processing of the present embodiment, and FIG. 5 (2) is a timing chart at the vertical scanning rate. Step numbers are shown in the 200s, and the same processing steps as those in the first embodiment are denoted by the same numbers as the 10s and 1s in the first embodiment.

  In the second embodiment, the processing target pixel specifying process is performed at an arbitrary exposure timing, the position information of the specific pixel 3a is stored in a predetermined storage device, and the position information of the specific pixel 3a is stored for each exposure. It is characterized in that it is read from the apparatus and used. Hereinafter, description will be made focusing on differences from the first embodiment.

  First, a device capable of nondestructive and random reading is used as a device (pixel array unit 10) to be imaged (S200). Then, the signal accumulated at a certain exposure timing is read out a plurality of times (m) (S214), the variation is calculated (S216), the unit pixel 3 having a large variation is selected as the specific pixel 3a (S218), and the position Information is stored (S219).

  Measurement for selecting a specific pixel 3a having a large random noise level is performed in advance, and the address data is stored in a storage device. In this case, it is considered that the first method of managing the position information of the specific pixel 3a by the main control unit outside the solid-state imaging device 1 is preferable.

  Since the power may be turned off until the next imaging, the specified position information of the specific pixel 3a may be stored in a non-volatile storage device (data that is retained even when the power is turned off). Preferred (S219). The process from step S214 to step S219 is referred to as a pre-processing target pixel specifying process S21. This pre-processing target pixel specifying process S21 does not have to be performed for each imaging, and may be performed at any imaging.

  Incidentally, when “at the time of arbitrary imaging” is set to “at the time of first imaging after power-on”, the position information of the specified specific pixel 3a may be stored in a “volatile” storage device. That is, when detecting the specific pixel 3a every time the power is turned on, the position information of the specified specific pixel 3a may be held in a volatile memory.

  In each subsequent imaging, first, image acquisition processing S222 (single signal readout) similar to the normal image acquisition processing S102 is performed. Thereafter, the position information of the specific pixel 3a is read from the storage device (S224), and the accumulated signal is read a plurality of (M) times for the specific pixel 3a as in the first embodiment (S226). The average value (which may be a simple addition average) is taken (S228). The processing from step S224 to step S228 is collectively referred to as random noise suppression processing S22.

  In the second embodiment, the effects of the first embodiment can be enjoyed in the same manner, and it is not necessary to perform the pre-processing target pixel specifying process S21 similar to the processing target pixel specifying process S11 for each image pickup. The load of signal processing can be further reduced.

  However, the matter regarding the random noise suppression process S22 similar to the random noise suppression process S12 is not different from the first embodiment. For example, as shown in FIG. 5 (2-1), the signal is read during the period of the image acquisition process S222 as in the normal case, but after that, the random noise suppression process S22 is added. This is similar to the case shown in 4A (2-1). At this time, even if the random noise suppression process S22 is performed in the vertical blanking period, if the amount of the random noise suppression process S22 does not fall within the vertical blanking period (FIG. 5 (2-2b)), The entire processing time will take longer than usual.

  Even when M signals are read out at a higher speed than normal (preferably M times), if the number of specific pixels 3a having a large RTS noise increases, the amount of random noise suppression processing S22 corresponds to the vertical blanking period. It can happen that it does n’t fit inside. In this case, the period of the random noise suppression process S22 is set as the vertical blanking period BLK1 longer than the normal vertical blanking period.

  As a countermeasure for this, for example, as shown in FIG. 5 (2-3), it is conceivable to select the specific pixel 3a in the range of the threshold value Th_2 regarding the number to be accommodated within the vertical blanking period in step S218. If the number of the specific pixels 3a is made to coincide with the threshold Th_2, the period of the random noise suppression process S22 coincides with the normal vertical blanking period.

  With the technique shown in FIG. 5 (2-3), it is preferable to read out M times of signals in the random noise suppression process S22 at a higher speed than normal, but it is considered that moving image capturing can also be handled. As described above, RTS noise is more problematic for moving images than for still images, but the problem can also be solved by applying the method shown in FIG. 5 (2-3).

  In the case of the second embodiment, the processing target pixel specifying process S21 is not performed for each imaging, and therefore, the noise of the entire image is suppressed by m-time averaging for the unit pixel 3 that is not selected as the specific pixel 3a. The second method in the first embodiment cannot be adopted.

<RTS Noise Suppression Processing: Third Embodiment>
FIG. 6 is a diagram for explaining a third embodiment of the RTS noise suppression process of the present embodiment. Here, FIG. 6A is a flowchart for explaining the basic principle of the RTS noise suppression processing of the present embodiment, and FIG. 6B is a timing chart at the vertical scanning rate and an outline of the vertical scanning. It is a figure to do. Step numbers are shown in the 300s, and processing steps similar to those in the second embodiment are denoted by the same numbers as the 10s and 1s in the second embodiment.

  As in the second embodiment, the third embodiment performs the processing target pixel specifying process at an arbitrary exposure timing, stores the position information of the specific pixel 3a in a predetermined storage device, and specifies each exposure. It is characterized in that the position information of the pixel 3a is read from the storage device and used. The difference from the second embodiment is that random noise suppression processing is performed in a normal signal reading process. Hereinafter, description will be made focusing on differences from the second embodiment.

  The process is the same as in the second embodiment until the pre-processing target pixel specifying process S31 is completed. In each subsequent imaging, the position information of the specific pixel 3a is first read from the storage device (S321). Then, in the process of performing the same image acquisition process (single signal readout) as the normal image acquisition process S102, in the line (row) where the vertical scanning position does not include the specific pixel 3a having a large RTS noise (S323-NO) ), The accumulated signal is read once (S325). On the other hand, in the line (row) where the specific pixel 3a having a large RTS noise exists in the vertical scanning position (S323-YES), the accumulated signal is read out a plurality of (M) times (S326), and the average value (simple addition) The average may be used) (S328). The processing from step S323 to step S328 is collectively referred to as random noise suppression processing S32.

  In the third embodiment, the effects of the first embodiment can be enjoyed in the same manner, and it is not necessary to perform the pre-processing target pixel specifying process S31 for each imaging as in the second embodiment. The processing load can be further reduced than in the first embodiment.

  However, since the random noise suppression process S32 is incorporated in the process of performing the image acquisition process S325 similar to the normal time, the processing cycle (vertical scanning progress speed) is performed between the line where the specific pixel 3a exists and the line where the specific pixel 3a does not exist. ) Will change. For this reason, a phenomenon occurs such that a difference in exposure time occurs between the lines, or the vertical scanning period (frame rate) varies according to the number of lines in which the specific pixel 3a exists.

  For example, as shown in FIG. 6 (2-1), the random noise suppression process S32 is performed not in the vertical blanking period but in the process of performing the image acquisition process S325 (single signal readout) similar to the normal time. . If M signals are read out at the same processing speed as in normal times, the progress of vertical scanning on the screen differs between a line where the specific pixel 3a does not exist and a line where it exists. The effect appears as a difference in exposure time (time difference corresponding to the “M−1” line). Further, the vertical scanning period becomes longer by “M−1” lines.

  As a countermeasure, for example, as shown in FIG. 6 (2-2), it is conceivable to read out M times of signals in step S326 at a higher speed than normal. For example, if M times of signal reading are performed at M times the normal time, the vertical scanning speed on the screen is the same for both the lines where the specific pixel 3a does not exist and the lines where the specific pixel 3a does not exist (the vertical scanning speed changes). do not do).

  With the method shown in FIG. 6 (2-2), it is necessary to read out the M number of signals in the random noise suppression process S32 at a higher speed than usual, but the number of lines in which the specific pixel 3a exists is reduced. It is considered that there is no fluctuation in the corresponding vertical scanning period and it can cope with moving image capturing. As described above, RTS noise is more problematic for moving images than for still images, but the problem can also be solved by applying the method shown in FIG.

<Imaging device>
FIG. 7 is a diagram for explaining another embodiment. In this embodiment, the mechanism of RTS noise suppression processing and multiple addition AD conversion processing employed in the above-described embodiment of the solid-state imaging device 1 is applied to an imaging device that is an example of a physical information acquisition device. FIG. 7 is a schematic configuration diagram of the imaging apparatus 8.

  The imaging apparatus also performs RTS noise suppression processing and multiple addition AD conversion processing on the pixel signal voltage Vx for at least one pixel, thereby reducing RTS noise at the time of pixel signal reading and quantization noise associated with AD conversion. A mechanism that can reduce or expand the dynamic range can be realized.

  At this time, for example, at least the control related to the RTS noise suppression process such as the setting of the number of repetitions m in the processing target pixel specifying process and the setting of the number of repetitions M in the random noise suppression process is performed by an external main control unit. Information can be arbitrarily designated by data setting for the communication / timing control unit 20.

  In addition, control related to the multiple addition AD conversion processing such as setting of the repeated addition W in the multiple addition AD conversion processing, the frequency setting of the count clocks CKcnt and CKdac, and the slope setting of the reference signal SLP_ADC is performed by an external main control unit. The instruction information can be arbitrarily designated by data setting for the communication / timing control unit 20.

  It is preferable that control of a normal reference signal comparison type AD conversion process in which the RTS noise suppression process and the multiple addition AD conversion process are not performed can be performed based on an instruction from the external main control unit.

  Specifically, the imaging device 8 includes a photographing lens 802, an optical low-pass filter 804, a color filter group 812, a pixel array unit 10, a drive control unit 7, a column AD conversion unit 26, a reference signal generation unit 27, and a camera signal processing unit. 810. As indicated by a dotted line in the drawing, an infrared light cut filter 805 that reduces an infrared light component can be provided together with the optical low-pass filter 804.

  The photographing lens 802 guides the light L carrying the image of the subject Z under illumination such as a fluorescent lamp or sunlight to the imaging device side to form an image. In the color filter group 812, for example, R, G, and B color filters are arranged in a Bayer array. The drive control unit 7 drives the pixel array unit 10. The read current control unit 24 controls the operation current of the pixel signal output from the pixel array unit 10. The column AD conversion unit 26 performs CDS processing, AD conversion processing, and the like on the pixel signal output from the pixel array unit 10. The reference signal generation unit 27 supplies the reference signal SLP_ADC to the column AD conversion unit 26. The camera signal processing unit 810 processes the imaging signal output from the column AD conversion unit 26.

  The camera signal processing unit 810 provided at the subsequent stage of the column AD conversion unit 26 includes an imaging signal processing unit 820 and a camera control unit 900 that functions as a main control unit that controls the entire imaging apparatus 8. The imaging signal processing unit 820 includes a signal separation unit 822, a color signal processing unit 830, a luminance signal processing unit 840, and an encoder unit 860.

  The signal separation unit 822 outputs digital image pickup signals supplied from the AD conversion function unit of the column AD conversion unit 26 as R (red), G (green), and B when a color filter other than the primary color filter is used. A primary color separation function for separating into (blue) primary color signals is provided. The color signal processing unit 830 performs signal processing on the color signal C based on the primary color signals R, G, and B separated by the signal separation unit 822. The luminance signal processing unit 840 performs signal processing on the luminance signal Y based on the primary color signals R, G, and B separated by the signal separation unit 822. The encoder unit 860 generates a video signal VD based on the luminance signal Y / color signal C.

  Although not shown, the color signal processing unit 830 includes, for example, a white balance amplifier, a gamma correction unit, a color difference matrix unit, and the like. Although not shown, the luminance signal processing unit 840 includes, for example, a high-frequency luminance signal generation unit, a low-frequency luminance signal generation unit, and a luminance signal generation unit. The high frequency luminance signal generation unit generates a luminance signal YH including even a component having a relatively high frequency based on the primary color signal supplied from the primary color separation function unit of the signal separation unit 822. The low frequency luminance signal generation unit generates a luminance signal YL including only a component having a relatively low frequency based on the primary color signal adjusted from the white balance supplied from the white balance amplifier. The luminance signal generation unit generates a luminance signal Y based on the two types of luminance signals YH and YL, and supplies the luminance signal Y to the encoder unit 860.

  The encoder unit 860 digitally modulates the color difference signals RY and BY with a digital signal corresponding to the color signal subcarrier, and then synthesizes the digital image with the luminance signal Y generated by the luminance signal processing unit 840. The signal is converted into a signal VD (= Y + S + C; S is a synchronization signal, and C is a chroma signal). The digital video signal VD output from the encoder unit 860 is further supplied to a camera signal output unit that is not shown in the subsequent stage, and is used for monitor output, data recording on a recording medium, and the like. At this time, the digital video signal VD is converted into the analog video signal V by DA conversion as necessary.

  The camera control unit 900 of this embodiment includes a microprocessor 902, a ROM 904 and a RAM 906 that are read-only storage units, and other peripheral members that are not shown. The microprocessor 902 is the same as the one that forms the center of an electronic computer whose representative example is a CPU (Central Processing Unit) that integrates the functions of computation and control performed by a computer into an ultra-small integrated circuit. Reference numeral 906 denotes an example of a volatile storage unit that can be written and read at any time. The microprocessor 902, the ROM 904, and the RAM 906 are collectively referred to as a microcomputer.

  The camera control unit 900 controls the entire system, and has a function of adjusting the number of repetitions m and M of pixel signal readout in relation to the RTS noise suppression process, and also a multiple addition AD conversion process , The frequency of addition, the frequency of the count clocks CKcnt and CKdac, and the function of adjusting the slope of the reference signal SLP_ADC. The ROM 904 stores a control program of the camera control unit 900. In this example, in particular, the camera control unit 900 performs normal reference signal comparison type AD conversion processing, RTS noise suppression processing, and multiple addition AD conversion processing. A program for controlling is stored. The microprocessor 902 controls the RTS noise suppression processing and the multiple addition AD conversion processing in cooperation with the module side having the same function unit as the solid-state imaging device 1 based on the program in the ROM 904. The RAM 906 stores data for the camera control unit 900 to perform various processes.

  In relation to the RTS noise suppression process, the camera control unit 900 also displays information on the pixel position of the specific pixel 3a specified in the pre-processing target pixel specifying process S21 or the pre-processing target pixel specifying process S31 even when the power is turned off. Save it so that it does not disappear. Therefore, as the RAM 906, an NVRAM that is an example of a non-volatile storage unit that is an example of a non-volatile storage medium that can be written and read at any time is used.

  The module-side drive control unit 7 (not shown communication / timing control unit 20) controls the position information of the specific pixel 3a acquired in the pre-processing target pixel specifying process S21 and the pre-processing target pixel specifying process S31. Section 900 is notified. The camera control unit 900 holds the position information of the specific pixel 3a in the NVRAM. The camera control unit 900 functions as a notification unit that reads the position information of the specific pixel 3a held in the NVRAM and notifies the drive control unit 7 (communication / timing control unit 20) on the module side every time imaging is performed.

  The camera control unit 900 is configured so that a recording medium 924 such as a memory card can be inserted and removed, and can be connected to a communication network such as the Internet. For example, the camera control unit 900 includes a memory reading unit 907 and a communication I / F (interface) 908 in addition to the microprocessor 902, the ROM 904, and the RAM 906.

  The recording medium 924 includes, for example, program data for causing the microprocessor 902 to perform software processing, a convergence range of the photometric data DL based on the luminance system signal from the luminance signal processing unit 840, and exposure control processing (including electronic shutter control). It is used for registering various data such as setting values of various control information for multiple addition AD conversion processing.

  The memory reading unit 907 stores (installs) the data read from the recording medium 924 in the RAM 906. The communication I / F 908 mediates transfer of communication data with a communication network such as the Internet.

  In the imaging device 8, the drive control unit 7 and the column AD conversion unit 26 are shown as modules separately from the pixel array unit 10, but as described for the solid-state imaging device 1. Needless to say, a one-chip solid-state imaging device 1 in which these are integrally formed on the same semiconductor substrate as the pixel array unit 10 may be used. In addition, in the figure, in addition to the pixel array unit 10, the drive control unit 7, the column AD conversion unit 26, the reference signal generation unit 27, and the camera signal processing unit 810, a photographing lens 802, an optical low-pass filter 804, or an infrared light cut The imaging device 8 is shown in a state including an optical system such as the filter 805, and this aspect is suitable for a module-like form having an imaging function packaged together.

  Here, in relation to the module in the solid-state imaging device 1 described above, as illustrated, the pixel array unit 10 (imaging unit) and the column AD conversion unit 26 having an AD conversion function and a difference (CDS) processing function are provided. A signal processing unit closely related to the pixel array unit 10 side (excluding the camera signal processing unit subsequent to the column A / D conversion unit 26) is solidly packaged in the form of a module having an imaging function. The imaging apparatus 1 is provided, and a camera signal processing unit 810 which is the remaining signal processing unit is provided at the subsequent stage of the solid-state imaging apparatus 1 provided in the module form so that the entire imaging apparatus 8 is configured. It may be.

  Alternatively, although not shown, the solid-state imaging device 1 is provided in a modular form having an imaging function in a state where the pixel array unit 10 and the optical system such as the photographing lens 802 are packaged together. In addition to the solid-state imaging device 1 provided in the form of a module, a camera signal processing unit 810 may be provided in the module to constitute the entire imaging device 8. Further, a camera signal processing unit 810 may be included as a module form in the solid-state imaging device 1, and in this case, the solid-state imaging device 1 and the imaging device 8 can be regarded as the same in effect. Such an imaging device 8 is provided as a portable device having an imaging function, for example, for performing “imaging”. Note that “imaging” includes not only capturing an image during normal camera shooting but also fingerprint detection in a broad sense.

  The imaging device 8 having such a configuration is configured to include all the functions of the solid-state imaging device 1 described above, and can be the same as the basic configuration and operation of the solid-state imaging device 1 described above. In addition to the normal reference signal comparison type AD conversion processing, a mechanism for performing RTS noise suppression processing and multiple addition AD conversion processing can be realized.

<Electronic equipment: Application to pixel defect diagnosis>
FIG. 8 is a diagram for explaining another embodiment. In this embodiment, the mechanism of the RTS noise suppression processing and the multiple addition AD conversion processing employed in the above-described embodiments of the solid-state imaging device 1 and the imaging device 8 is applied to an electronic device. That is, this embodiment shows an example in which the RTS noise suppression processing method, the multiple addition AD conversion processing method, and the multiple addition AD conversion processing device of the present embodiment are applied to electronic equipment other than the solid-state imaging device. FIG. 8 is a schematic configuration diagram of the electronic device.

  In the above-described embodiment, solid-state imaging is performed by performing RTS noise suppression processing for the specific pixel 3a in which the pixel signal is read from the pixel array unit 10 and multiple addition AD conversion processing that repeats the reference signal comparison type AD conversion processing W times for the same signal. Although the example applied to the device 1 and the imaging device 8 has been described, the application range is not limited to the solid-state imaging device and the imaging device.

  The RTS noise suppression processing for a specific element that can read a signal from the element can be applied to any electronic device that requires a memory device such as SRAM or DRAM. Even in such an electronic device, RTS noise can be reduced by applying the RTS noise suppression processing of the present embodiment as a mechanism for improving the problem of random noise when reading stored data.

  The illustrated electronic apparatus 700 has various processing functions based on the product-sum operation result, such as diagnosing a defective pixel of the solid-state imaging device 1 and performing a moving object detection process. Specifically, the electronic device 700 first includes a signal generation unit 701 that generates an analog processing target signal. The signal generation unit 701 is configured to use the pixel signal voltage Vx output from the pixel array unit 10 of the solid-state imaging device 1 as a processing target signal. That is, also in the present embodiment, the processing target signal is a pixel signal (pixel signal voltage Vx) based on the pixel signal current output from the pixel array unit 10 of the solid-state imaging device 1 as the processing target signal. Suppose that However, this is only an example, and may be an arbitrary signal, not limited to a pixel signal, as long as the signals have the same physical properties so as to withstand product-sum operations.

  The electronic device 700 is also arranged on the left side of the dividing line, and a control device 702 using a personal computer or the like that controls the overall operation of the electronic device 700, which is arranged on the left side of the dividing line shown in the center portion in the figure. In addition, an AD conversion device 705 is provided. A pixel signal voltage Vx is supplied from the signal generation unit 701 to the AD conversion device 705. Note that the control device 702 and the AD conversion device 705 are not separated by a dividing line, but include both of them, and a single data processing device function that obtains digital data of a product-sum operation result between a plurality of signals. You may comprise as AD conversion part 706 (AD conversion apparatus).

  The AD conversion unit 706 (AD conversion device 705) includes a comparison unit 752 and a counter unit 754. The comparison unit 752 converts the analog pixel signal captured from the signal generation unit 701 (solid-state imaging device 1) into digital data. The comparison unit 752 corresponds to the comparison unit 252, and the counter unit 754 corresponds to the counter unit 254, and their basic operations are the same as those of the comparison unit 252 and the counter unit 254 of the solid-state imaging device 1.

  The control device 702 includes, as functional elements that control the AD conversion device 705, a reference signal generation unit 727 that supplies a reference voltage for AD conversion to the comparison unit 752, and timing control that controls the reference signal generation unit 727 and the counter unit 754. Part 720. The timing control unit 720 corresponds to the communication / timing control unit 20, and the reference signal generation unit 727 corresponds to the reference signal generation unit 27, and their basic operations are the communication / timing control unit of the solid-state imaging device 1. 20 and the reference signal generation unit 27.

  The control device 702 diagnoses the solid-state imaging device 1 based on the data storage unit 728 that holds one piece of product-sum operation processing target data and the product-sum operation result data D8 obtained by the counter unit 754, and makes other determinations. A determination / diagnosis unit 730 having functions such as processing is provided.

  In such a configuration of the electronic apparatus 700, in order to realize a function of diagnosing a defective pixel of the solid-state imaging device 1, first, pixel data (normal data) of a normal (non-pixel defect) solid-state imaging device 1 to be compared. After that, a pixel signal is read from the solid-state imaging device 1 to be diagnosed, difference processing is performed with normal data, and the presence or absence of a defect is diagnosed based on the result. As the pixel defect, for example, a dark defect and a bright defect are preferably diagnosed. For the dark defect diagnosis, the solid-state imaging device 1 is set in a non-exposure state, and normal data is acquired and diagnosed. In order to diagnose a light-time defect, for example, normal data of the solid-state imaging device 1 is acquired and diagnosed in an all-white photographing state.

  When acquiring normal data, the AD conversion device 705 (AD conversion unit 706) acquires the pixel signal voltage Vx from the normal solid-state imaging device 1 to be compared, and in the same manner as described for the solid-state imaging device 1, The comparison unit 752 compares the reference signal SLP_ADC supplied from the reference signal generation unit 727 and the pixel signal voltage Vx.

  In the present embodiment, when acquiring normal data, a process target pixel specifying process for selecting a specific pixel having a large RTS noise is performed by repeating accumulated information obtained by one exposure m times. For a specific pixel, an instruction is given to perform random noise suppression processing that is repeated M times and read and averaged.

  Preferably, the timing control unit 720 performs W multiple addition AD conversion processing on the counter unit 754 and the reference signal generation unit 727 and averages the result corresponding to W times. To instruct. This means that the pixel signal voltage Vx is subjected to AD conversion repeatedly W times, thereby converting the digital signal to digital data with a high gain and returning the digital data to a normal level with a high gain.

  The counter unit 754 counts based on the count clock CK0 (CKcnt1 at normal time, CKcntW at the time of multiple addition, etc.) in the count mode instructed by the timing control unit 720 simultaneously with the generation of the reference signal SLP_ADC by the reference signal generation unit 727. Start processing. Here, the timing control unit 720 sets the count mode of the counter unit 754 to the down-count mode when processing the reset level, and sets the signal level to the up-count mode. This means that positive data is acquired as pixel data corresponding to the signal component Vsig.

  The counter unit 754 counts the count clock CK0 from the generation time of the reference signal SLP_ADC used in the comparison processing of the comparison unit 752 to the time point when the pixel signal voltage Vx and the reference signal SLP_ADC match, and the coefficient result is stored in its own registered data D9a. Are registered in the data storage unit 728 in association with each other. The AD conversion apparatus 705 repeats such processing for all pixels of the imaging signal.

  The acquisition of normal data does not necessarily have to be acquired using the AD conversion device 705. For example, normal data is acquired by an external device, and registered data D9b input from the external device. May be registered in the data storage unit 728 in association with the pixel position. Alternatively, the normal data can be constant (no unevenness) regardless of the pixel position. In this case, it is not necessary to acquire normal data.

  When diagnosing a dark defect or a light defect, the solid-state imaging device 1 is set to a predetermined exposure state corresponding to each diagnosis. The timing control unit 720 preferably instructs the random noise suppression processing to be performed in the same manner as when obtaining normal data.

  More preferably, the timing control unit 720 instructs to perform W multiple addition AD conversion processing in the same manner as when acquiring normal data. When dark defects are diagnosed, the gain-up data is obtained without performing the averaging process, and when the light defects are diagnosed, normal level data is obtained by performing the averaging process.

  The timing control unit 720 issues an initial value control signal CN7 to the counter unit 754, reads out normal pixel data at the same pixel position as the processing target pixel position from the data storage unit 728, and sets it as the initial value of the count process. To instruct. The AD conversion device 705 acquires the analog pixel signal voltage Vx from the solid-state imaging device 1 to be diagnosed, and first, in the comparison unit 752, the reference signal SLP_ADC and the pixel that change with a predetermined gradient supplied from the reference signal generation unit 727. The signal voltage Vx is compared. The counter unit 754 counts the count clock CK0 based on the comparison result.

  The determination / diagnosis unit 730 determines the presence / absence of a pixel defect by using the product-sum operation data D8 indicating the difference between normal operation and actual operation indicated by the count value obtained by the counter unit 754 as defect determination data. Here, as the count result, a value obtained by subtracting the pixel data during actual operation from the pixel data during normal operation is obtained. If there is no pixel defect, the obtained count value is only an error component and a noise component, and may be considered to be sufficiently small. On the other hand, when there is a pixel defect, a large difference appears between the pixel data during normal operation and during actual operation. Therefore, the determination / diagnosis unit 730 determines that the product sum calculation data D8 obtained by the counter unit 754 is equal to or greater than a certain value in order to prevent erroneous determination due to an error component, a noise component, or the like when determining a pixel defect. It is preferable to determine that there is a pixel defect.

  As described above, when the electronic apparatus 700 is used for pixel defect diagnosis, pixel data difference processing is performed between the normal device and the diagnosis target device using the AD conversion unit 706 including a combination of the comparison unit 752 and the counter unit 754. I tried to do it. Thus, when the digital data indicating the difference between the normal state and the normal state is AD-converted for the pixel signal in the normal state, the output of the counter unit 754 is directly output as described in the embodiment of the solid-state imaging device 1. Can be obtained as

  In the pixel defect diagnosis, noise affects the determination performance. However, by applying the RTS noise suppression processing described above, the present embodiment is not affected by random noise (particularly RTS noise) when reading a pixel signal. It is possible to make a more accurate determination than when not applied.

  Furthermore, by using the multiple addition AD conversion process together, pixel defect diagnosis can be performed using diagnostic data with good S / N. When a dark defect is diagnosed, a sufficient level of data for diagnosis can be obtained by using a gain-up function by multiple addition AD conversion processing.

  Here, the application example to the pixel defect diagnosis has been described, but application examples of the RTS noise suppression process and the multiple addition AD conversion process are not limited thereto. For example, when the moving object detection function is realized, the pixel signal voltage Vx of the current frame is read from the solid-state imaging device 1 and is subjected to a difference process with the pixel signal voltage Vx of the previous frame. Is detected. At this time, moving object detection data with good S / N can be acquired by applying RTS noise suppression processing and multiple addition AD conversion processing.

<Application examples to other electronic devices>
FIG. 9 is a diagram illustrating an example of another electronic device to which the RTS noise suppression process or the multiple addition AD conversion process is applied.

  The RTS noise suppression process and the multiple addition AD conversion process of the present embodiment can suppress noise associated with AD conversion and signal reading from elements in various electronic devices such as game machines, electronic books, electronic dictionaries, and mobile phones. It can be applied when required.

  For example, FIG. 9A is a diagram illustrating an external appearance example when the electronic apparatus 600 is a television receiver 602 using a display module 604 (a liquid crystal display device or an organic EL display device) which is an example of an image display device. It is. The television receiver 602 has a structure in which a display module 604 is disposed in front of a front panel 603 supported by a pedestal 606, and a filter glass 605 is provided on the display surface. The television receiver 602 uses an SDRAM (DDR2 specification or DDR3 specification) not shown, and the RTS noise suppression processing mechanism of the above-described embodiment is applied to data reading from the SDRAM. In addition, the television receiver 602 is configured to be detachable from the silicon disk unit 608 for recording functions, and the mechanism of the RTS noise suppression process of the above-described embodiment for reading data from the silicon disk unit 608 is used. Applied.

  FIG. 9B is a diagram illustrating an appearance example when the electronic apparatus 600 is a digital camera 612. The digital camera 612 includes a display module 614, a control switch 616, a shutter button 617, and others. The digital camera 612 is equipped with a solid-state imaging device (not shown), and the above-described mechanisms of the RTS noise suppression processing and the multiple addition AD conversion processing of the solid-state imaging device 1 and the imaging device 8 are applied as they are. In addition, the memory card 618 is detachably attached to the digital camera 612, and the RTS noise suppression processing mechanism of the above-described embodiment is applied to reading data from the memory card 618.

  FIG. 9 (3) is a diagram illustrating an appearance example when the electronic apparatus 600 is a video camera 622. The video camera 622 is provided with an imaging lens 625 for imaging a subject in front of the main body 623, and further, a display module 624, a shooting start / stop switch 626, and the like are arranged. The video camera 622 is equipped with a solid-state imaging device (not shown), and the mechanisms of the RTS noise suppression processing and the multiple addition AD conversion processing of the solid-state imaging device 1 and the imaging device 8 described above are applied as they are. In addition, the silicon disk unit 628 is detachably attached to the video camera 622, and the RTS noise suppression processing mechanism of the above-described embodiment is applied to reading data from the silicon disk unit 628.

  FIG. 9 (4) is a diagram illustrating an external appearance example when the electronic apparatus 600 is a mobile phone 632. The cellular phone 632 is a foldable type and includes an upper housing 633a, a lower housing 633b, a display module 634a, a sub display 634b, a camera 635, a connecting portion 636 (in this example, a hinge portion), a picture light 637, and the like. Yes. And regarding the camera 635 of the mobile phone 632, the mechanisms of the RTS noise suppression processing and the multiple addition AD conversion processing of the solid-state imaging device 1 and the imaging device 8 described above are applied as they are. In addition, a memory card 638 is detachably attached to the mobile phone 632, and the RTS noise suppression processing mechanism of the above-described embodiment is applied to reading data from the memory card 638.

  FIG. 9 (5) is a diagram illustrating an external appearance example when the electronic apparatus 600 is a computer 642. The computer 642 includes a lower casing 643a, an upper casing 643b, a display module 644, a Web camera 645, a keyboard 646, and the like. And regarding the Web camera 645 of the computer 642, the mechanism of the RTS noise suppression process and the multiple addition AD conversion process of the solid-state imaging device 1 or the imaging device 8 described above is applied as it is. In addition, the computer 642 has a PCI Express specification bus and uses an SDRAM (DDR2 specification or DDR3 specification) or a silicon disk unit (not shown), and has been described above for reading data from the SDRAM or the silicon disk unit. The mechanism of the RTS noise suppression process of the embodiment is applied. In addition, a portable storage medium 648 (for example, a USB memory) of various specifications is detachably attached to the computer 642, and the mechanism of the RTS noise suppression process of the above-described embodiment for reading data from the storage medium 648 is provided. Applied.

[Example of application to semiconductor memory devices]
FIG. 9A is a diagram for explaining details of an application example of the RTS noise suppression process to a semiconductor memory device (nonvolatile semiconductor memory device, nonvolatile memory device).

  Electronic devices 600 that use the semiconductor storage device 2 include memory cards, computer devices (including portable devices), AV (audio / video) devices such as digital still cameras, video cameras, and audio players, air conditioners, refrigerators, televisions, Applicable to home appliances such as washing machines and in-vehicle devices (see FIG. 9).

  As shown in FIG. 9A (1), the semiconductor memory device 2 includes a memory cell array unit 663, a write / read unit 664, a column control unit 667, and a row control unit 668 (word line selection unit). The writing / reading unit 664, the column control unit 667, and the row control unit 668 control the potential of the word line, the source line, and the bit line (all not shown) according to each operation of writing, erasing, and reading data. A drive control unit 666 is configured. A peripheral circuit that controls writing, erasing, and reading of the memory cell array unit 663 is provided around the memory cell array unit 663. The column control unit 667 and the row control unit 668 are assumed to support random access.

  In the memory cell array portion 663, memory cells 662 (nonvolatile memory elements, data holding portions) are arranged in a two-dimensional matrix. As a circuit for selecting (scanning) each memory cell 662 of the memory cell array unit 663, the column control unit 667 is connected to the bit line of each column, and the row control unit 668 is connected to the word line of each row. Although not shown, the bit lines of each column are connected not only to the column control unit 667 but also to the write / read unit 664. A write / read unit 664 is connected to the source line of each column.

  The write / read unit 664 writes data to each memory cell 662 of the memory cell array unit 663 or reads data from the memory cell 662. Then, when reading the information held in the memory cell 662 of the memory cell array unit 663, the mechanism of the RTS noise suppression process of the above-described embodiment is applied.

  The write / read unit 664 treats a specific element in which noise in a plurality of elements (memory cell 662) is larger than a predetermined reference value as a processing target, and outputs a signal based on the same information held by the specific element. It has a function of a signal reading unit that reads M times (M is an integer of 2 or more).

  The writing / reading unit 664 determines the source line selection by decoding processing by an address decoder (not shown) such as a byte unit. Although not shown, the write / read unit 664 includes a write buffer for supplying data to the bit line and holding the information in the memory cell 662 and a sense amplifier (Sense AMP) for amplifying the potential of the bit line. Have. The write buffer is also referred to as a write circuit or a write amplifier.

  Although not shown, a functional unit (column switch) for selecting the memory cell 662 to be processed in units of columns is provided between the write / read unit 664 and the bit line. The column switch has a function of supplying an operating voltage and a standby voltage to the bit line, that is, a function of supplying an arbitrary current to the bit line, in addition to a function of selecting the memory cell 662 to be processed in units of columns.

  As shown in FIG. 9A (1), when the electronic device 600 is configured as a memory card, in addition to the semiconductor memory device 2, the semiconductor memory device 2 and peripheral function units (not limited to the inside of the device but outside the device) may be used. It has a memory controller 672 that performs interface control.

  The memory controller 672 has a function of an averaging processing unit (noise suppression unit) that acquires a signal in which noise is suppressed by taking an average value of M signals read by the writing / reading unit 664. In addition, the memory controller 672 reads the same information held in the memory cell 662 m times (m is an integer equal to or greater than 2), obtains the variation of each signal, and the variation of each signal of m times It has a function of a specific element selection unit that selects a memory cell 662 larger than a predetermined reference value as a specific element. Since the power supply of the memory card may be in a non-refusal state, the memory controller 672 is provided with a mechanism for storing the position information of the specific element (corresponding to the specific pixel 3a) having a large noise in the nonvolatile storage device. .

  As shown in FIG. 9A (2), in the configuration in which the peripheral function unit is provided inside the device, a data acquisition unit 676 and an output data processing unit 678 are provided. The data acquisition unit 676 acquires data to be written in each memory cell 662 of the semiconductor memory device 2. The output data processing unit 678 processes data read from the data acquisition unit 676 and each memory cell 662. When the electronic device 600 is configured as a computer device, an AV device, a home appliance, an in-vehicle device, the CPU and the bus controller are in charge of the memory controller 672, and the other electric circuit units are the data acquisition unit 676 and the output data processing unit 678. In charge.

  Further, as shown in FIG. 9A (2), in the case of a digital still camera, a recording function unit that writes an image acquired by a solid-state imaging device such as a CCD as digital data corresponds to the data acquisition unit 676, and the read data The reproduction system function unit that displays an image on the display panel corresponds to the output data processing unit 678. The CPU controls each part of the camera based on a program stored in the EEPROM to which the semiconductor memory device 2a is applied, while storing / reading intermediate data and the like in / from a RAM as a work memory. Further, in the case of a digital still camera, the semiconductor storage device 2b as a memory card is configured to be detachable.

  As mentioned above, although this invention was demonstrated using embodiment, the technical scope of this invention is not limited to the range as described in the said embodiment. Various changes or improvements can be added to the above-described embodiment without departing from the gist of the invention, and embodiments to which such changes or improvements are added are also included in the technical scope of the present invention.

  Further, the above embodiments do not limit the invention according to the claims (claims), and all combinations of features described in the embodiments are not necessarily essential to the solution means of the invention. Absent. The embodiments described above include inventions at various stages, and various inventions can be extracted by appropriately combining a plurality of disclosed constituent elements. Even if some constituent requirements are deleted from all the constituent requirements shown in the embodiment, as long as an effect is obtained, a configuration from which these some constituent requirements are deleted can be extracted as an invention.

  For example, in the solid-state imaging device 1 according to the above-described embodiment, the CMD-type solid-state imaging device that is sensitive to electromagnetic waves input from the outside such as light and radiation has been illustrated. The mechanism described in the above embodiment can be applied to anything that detects a change. For example, a fingerprint authentication device that detects fingerprint images based on a change in electrical characteristics or optical characteristics based on pressure for information related to fingerprints (eg, JP 2002-7984 and 2001-125734). It can be applied to other physical change detection devices such as

  The RTS noise suppression process and the multiple addition AD conversion process can be applied not only to the CMD type but also to a so-called CMOS sensor including the unit pixel 3 having the CMOS structure. In this case, the unit pixel 3 having a general CMOS structure does not support non-destructive reading, but the CMOS structure can also support non-destructive reading by providing the pixel array unit 10 with an internal memory, for example.

  Furthermore, when the RTS noise suppression process is applied to the CMOS sensor, it is preferable that the horizontal scanning unit 12 and the vertical scanning unit 14 can be randomly accessed. However, as described above, it is essential to apply random access. Not.

Furthermore, based on the description of the embodiment, in addition to the invention according to the claims described in the claims, for example, the following configurations can be proposed as the invention. The following is listed.
<Supplementary Note 1> In a signal processing device, a semiconductor device, a solid-state imaging device, an imaging device, an electronic device, and a noise suppression method,
The signal reading unit reads the signal M times based on the same information held by the specific element at a higher speed than the normal process of reading the signal from a normal element that is not the specific element at a time.
<Supplementary Note 2> In Supplementary Note 1, the signal reading unit reads the signal M times at a speed M times faster than the normal processing.
<Supplementary Note 3> In a signal processing device, a semiconductor device, a solid-state imaging device, an imaging device, an electronic device, and a noise suppression method,
The specific element selection unit reads the signal m times based on the same information held by the element at a higher speed than the normal process of reading the signal from a normal element that is not the specific element at a time.
<Supplementary Note 4> In Supplementary Note 3, the specific element selection unit reads the signal m times at a speed m times faster than the normal processing.
<Supplementary Note 5> In a signal processing device, a semiconductor device, a solid-state imaging device, an imaging device, an electronic device, and a noise suppression method,
The noise suppression unit acquires a signal in which noise is suppressed by taking an average value of the signals acquired by the specific element selection unit m times for a normal element that is not a specific element.
<Supplementary Note 6> In a signal processing device, a semiconductor device, a solid-state imaging device, an imaging device, an electronic device, and a noise suppression method,
When column reading is possible, the signal reading unit reads a signal based on the same information held by each specific element for all the specific elements on the same line for M times.

  DESCRIPTION OF SYMBOLS 1 ... Solid-state imaging device, 10 ... Pixel array part, 12 ... Horizontal scanning part, 14 ... Vertical scanning part, 20 ... Communication / timing control part, 20b ... System control part, 20a ... Clock conversion part, 24 ... Current-voltage conversion part , 250 ... AD conversion unit, 252 ... comparison unit, 254 ... counter unit, 256 ... data storage unit, 26 ... column AD conversion unit, 27 ... reference signal generation unit, 270 ... DA conversion unit, 28 ... output unit, 29 ... Digital operation unit, 3... Unit pixel, 3a... Specific pixel, 7... Drive control unit, 8.

Claims (20)

Signals based on the same information held by the specific elements are processed M times (M is an integer equal to or greater than 2) with a specific element having a noise larger than a predetermined reference value as a processing target. A signal readout unit for reading over
A noise suppression unit that acquires a signal in which noise is suppressed based on the M signals read by the signal reading unit;
A signal processing apparatus comprising: A storage unit for holding position information of the specific element;
The signal processing apparatus according to claim 1, wherein the signal reading unit reads the M times of signals with reference to position information of the specific element held in the storage unit. The same information held by the element is read m times (m is an integer equal to or greater than 2), the variation of each signal is obtained, and the variation of each m times is more than a predetermined reference value. The signal processing apparatus according to claim 1, further comprising: a specific element selection unit that selects a large element as the specific element. A comparison unit for comparing a reference signal supplied from a reference signal generation unit that generates a reference signal whose level gradually changes and an analog processing target signal acquired based on information held by the element, and for AD conversion An AD converter that receives the count clock and performs a count operation based on the comparison result of the comparator, and obtains digital data of the processing target signal based on output data of the counter;
For the signal to be processed, the reference signal generation unit and the AD conversion are performed so as to execute digital integration processing in which n-bit AD conversion processing is repeated W times (W is the number of repetitions and is a positive integer of 2 or more). A control unit for controlling the unit,
The signal processing device according to claim 1, further comprising: An element portion in which a plurality of elements are arranged;
A position information acquisition unit that acquires position information in the element unit of a specific element in which noise among the plurality of elements is larger than a predetermined reference value;
Signal readout that reads out a signal based on the same information held by the specific element M times (M is an integer of 2 or more) with reference to the position information of the specific element acquired by the position information acquisition unit And
A noise suppression unit that acquires a signal in which noise is suppressed based on the M signals read by the signal reading unit;
A system control unit that controls the reading position of the element of the element unit, and controls the position information acquisition unit, the signal reading unit, and the noise suppression unit;
A semiconductor device comprising: A storage unit that holds position information of the specific element;
A notification unit that reads position information of the specific element held in the storage unit and notifies the signal reading unit;
With
The semiconductor device according to claim 5, wherein the signal reading unit reads the M times of signals with reference to position information of the specific element notified from the notification unit. The same information held by the element is read m times (m is an integer equal to or greater than 2), the variation of each signal is obtained, and the variation of each m times is more than a predetermined reference value. The semiconductor device according to claim 5, further comprising: a specific element selection unit that selects a large element as the specific element. A comparison unit for comparing a reference signal supplied from a reference signal generation unit that generates a reference signal whose level gradually changes and an analog processing target signal acquired based on information held by the element, and for AD conversion An AD converter that receives the count clock and performs a count operation based on the comparison result of the comparator, and obtains digital data of the processing target signal based on output data of the counter;
For the signal to be processed, the reference signal generation unit and the AD conversion are performed so as to execute digital integration processing in which n-bit AD conversion processing is repeated W times (W is the number of repetitions and is a positive integer of 2 or more). A control unit for controlling the unit,
The semiconductor device according to claim 5, further comprising: The semiconductor device according to claim 5, further comprising a scanning unit that randomly accesses a position of the specific element in the element unit. A pixel portion in which a plurality of unit pixels capable of nondestructive reading are arranged;
A position information acquisition unit that acquires position information in the pixel unit of a specific pixel in which noise among the plurality of unit pixels is larger than a predetermined reference value;
A signal that reads the pixel signal based on the same information held by the specific pixel M times (M is an integer of 2 or more) with reference to the position information of the specific pixel acquired by the position information acquisition unit A reading unit;
A noise suppression unit that acquires a pixel signal in which noise is suppressed based on the M pixel signals read by the signal reading unit;
A system control unit that controls the reading position of the unit pixel of the pixel unit and controls the position information acquisition unit, the signal reading unit, and the noise suppression unit;
A solid-state imaging device. A storage unit for holding position information of the specific pixel;
A notification unit that reads position information of the specific pixel held in the storage unit and notifies the signal reading unit;
With
The solid-state imaging device according to claim 10, wherein the signal reading unit reads the M times of signals with reference to position information of the specific pixel notified from the notification unit. The same information held by the unit pixel is read m times (m is an integer of 2 or more), the variation of the pixel signal of each time is obtained, and the standard of the variation of the pixel signal of m times is determined in advance. The solid-state imaging device according to claim 10, further comprising: a specific pixel selection unit that selects a unit pixel larger than the value as the specific pixel. Comparison unit and AD conversion for comparing the reference signal supplied from a reference signal generation unit that generates a reference signal whose level gradually changes and an analog processing target signal acquired based on information held by the unit pixel An A / D conversion unit that receives a count clock and performs a count operation based on a comparison result of the comparison unit, and acquires digital data of the processing target signal based on output data of the counter unit;
For the signal to be processed, the reference signal generation unit and the AD conversion are performed so as to execute digital integration processing in which n-bit AD conversion processing is repeated W times (W is the number of repetitions and is a positive integer of 2 or more). A drive control unit for controlling the unit;
The solid-state imaging device according to any one of claims 10, 11, and 12. The solid-state imaging device according to claim 10, further comprising a scanning unit that randomly accesses a position of the specific pixel in the pixel unit. A pixel portion in which a plurality of unit pixels capable of nondestructive reading are arranged;
A position information acquisition unit that acquires position information in the pixel unit of a specific pixel in which noise among the plurality of unit pixels is larger than a predetermined reference value;
A signal that reads the pixel signal based on the same information held by the specific pixel M times (M is an integer of 2 or more) with reference to the position information of the specific pixel acquired by the position information acquisition unit A reading unit;
A noise suppression unit that acquires a pixel signal in which noise is suppressed based on the M pixel signals read by the signal reading unit;
A system control unit that controls the reading position of the unit pixel of the pixel unit and controls the position information acquisition unit, the signal reading unit, and the noise suppression unit;
A main controller that controls the system controller;
An imaging apparatus comprising: A position information acquisition unit for acquiring position information in the element unit of a specific element in which noise in a plurality of elements is larger than a predetermined reference value;
Signal readout that reads out a signal based on the same information held by the specific element M times (M is an integer of 2 or more) with reference to the position information of the specific element acquired by the position information acquisition unit And
A noise suppression unit that acquires a signal in which noise is suppressed based on the M signals read by the signal reading unit;
A system control unit that controls the reading position of the element of the element unit, and controls the position information acquisition unit, the signal reading unit, and the noise suppression unit;
A main controller that controls the system controller;
With electronic equipment. Signals based on the same information held by the specific elements are processed M times (M is an integer equal to or greater than 2) with a specific element having a noise larger than a predetermined reference value as a processing target. A process of reading over,
Obtaining a noise-suppressed signal based on the read M signals;
Noise suppression method with Holding the position information of the specific element in the storage unit;
Reading the position information of the specific element held in the storage unit;
With
The noise suppression method according to claim 17, wherein the M signals are read with reference to position information of the specific element read from the storage unit. A step of reading the same information held by the element m times (m is an integer of 2 or more), a step of calculating a variation of each signal m times,
Selecting an element having the variation larger than a predetermined reference value as a specific element;
The noise suppression method of Claim 17 or Claim 18 provided with these. A comparison unit compares an analog processing target signal acquired based on information held by the element and a reference signal whose level gradually changes, and receives a count clock for AD conversion, and results of the comparison When the digital data of the signal to be processed is obtained based on the output data of the counter unit, the n-bit AD conversion process is performed W times (W is 2 or more). The noise suppression method according to claim 17, wherein the noise suppression method is performed repeatedly.

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