JP2018033173A - Method for driving imaging apparatus, imaging apparatus, and imaging system - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide an imaging apparatus that reduces fluctuations in reset potential generated when pixels are reset, a method of driving the same, and an imaging system.SOLUTION: An imaging apparatus having a pixel 100 having an AD conversion section 200, includes a first pixel and a second pixel. A start of a reset period for resetting at least one of potential of the AD conversion section, potential of an input section, and potential of a reference signal input section is made different between the first pixel and the second pixel and timing of inputting an electric signal into an input section is made to be simultaneous between the first pixel and the second pixel.SELECTED DRAWING: Figure 1

Description

  The present invention relates to an imaging apparatus and an imaging system in which a pixel includes a conversion unit that generates a signal based on incident electromagnetic waves, and an analog-to-digital conversion unit that converts a signal generated by the conversion unit into a digital signal.

  A pixel including a conversion unit that generates a signal based on an incident electromagnetic wave and an analog-to-digital conversion unit (hereinafter referred to as an AD conversion unit) that converts the signal generated by the conversion unit into a digital signal, as in Patent Document 1. There is known an imaging apparatus having

JP 2006-203736 A

  In the imaging apparatus described in Patent Document 1, the potential of the conversion unit is reset before the conversion unit generates a signal based on incident light. When the signal of the conversion unit is reset, a current flows from the conversion unit to the power supply line that supplies the power supply voltage VDD. Further, before AD conversion, the potential of the input node of the AD conversion unit to which the signal of the conversion unit is given is reset. Even when the input node of the AD conversion unit is reset, a current flows from the input node of the AD conversion unit to the power supply line that supplies the power supply voltage VDD. When a current flows through the power supply line that supplies the power supply voltage VDD, a voltage drop occurs, and the potential of the power supply voltage VDD changes. This fluctuation in the potential of the power supply voltage VDD is particularly noticeable when a reset operation is performed simultaneously on a plurality of pixels. The reset potential of the conversion unit or the reset potential of the input node of the AD conversion unit varies due to the fluctuation of the power supply voltage VDD. When the reset potential of the conversion unit varies, the accuracy of the signal generated by the conversion unit based on incident light is reduced. Further, the AD conversion accuracy is lowered due to the change in the reset potential of the input node of the AD conversion unit. Further, when the AD conversion unit includes a comparison unit that compares the ramp signal and the signal output from the conversion unit, the power supply voltage VDD is supplied from the node to which the ramp signal is applied when the node to which the ramp signal of the comparison unit is applied is reset. Current flows through the power line. As a result, a voltage drop occurs in the power supply line that supplies the power supply voltage VDD, and the potential of the power supply voltage VDD varies. When the potential of the power supply voltage VDD fluctuates, the reset potential of the node to which the ramp signal is applied fluctuates, resulting in a decrease in AD conversion accuracy.

  In the imaging apparatus described in Patent Document 1, no study has been made to reduce fluctuations in the reset potential caused by the pixel reset operation.

  The present invention has been made in view of the above problems, and one aspect is a conversion unit that generates an electrical signal based on an incident electromagnetic wave, an input unit that receives the electrical signal from the conversion unit, and A reference signal input unit to which a reference signal is input, and an AD conversion unit that converts the electric signal into a digital signal based on the result of comparing the potential of the input unit and the potential of the reference signal input unit, respectively. A driving method of an imaging apparatus having a plurality of pixels, wherein the plurality of pixels include at least a first pixel and a second pixel different from the first pixel, and the potential of the conversion unit And the reset period for resetting at least one of the potential of the input unit and the potential of the reference signal input unit is different between the first pixel and the second pixel, and the electrical The signal from the converter The timing of inputting the force unit is a driving method of an image pickup apparatus characterized by the simultaneous with the first pixel and the second pixel.

  Another aspect includes a conversion unit that generates an electrical signal based on an incident electromagnetic wave, an input unit that receives the electrical signal from the conversion unit, a reference signal input unit that receives a reference signal, and the input A plurality of pixels each having an AD conversion unit that converts the electrical signal into a digital signal based on a result of comparing the potential of the unit and the potential of the reference signal input unit, and is common to the plurality of pixels A driving method of an imaging apparatus including a potential supply unit that supplies a reset potential of the plurality of pixels, wherein the plurality of pixels are different from the first pixel and the first pixel, and more than the first pixel. At least a second pixel having a long electrical path to which the reset potential is supplied from the potential supply unit, and the potential of the conversion unit, the potential of the input unit, and the potential of the reference signal input unit At least one A reset period for bets, towards the second pixel, a driving method of an image pickup apparatus characterized by initiating earlier than the first pixel.

  Another aspect includes a conversion unit that generates an electrical signal based on an incident electromagnetic wave, an input unit that receives the electrical signal from the conversion unit, a reference signal input unit that receives a reference signal, and the input A plurality of pixels each having an AD conversion unit that converts the electrical signal into a digital signal based on a result of comparing the potential of the unit and the potential of the reference signal input unit. A driving method of an imaging apparatus having a potential supply unit for supplying a common reset potential, wherein the plurality of pixels are different from the first pixel and the first pixel, Includes at least a second pixel having a large resistance in an electrical path to which the reset potential from the potential supply unit is supplied, the potential of the conversion unit, the potential of the input unit, and the reference signal input unit At least with potential The reset period for resetting the One, towards the second pixel, a driving method of an image pickup apparatus characterized by initiating earlier than the first pixel.

  Another aspect includes a conversion unit that generates an electrical signal based on an incident electromagnetic wave, an input unit that receives the electrical signal from the conversion unit, a reference signal input unit that receives a reference signal, and the input An imaging device having a plurality of pixels each having an AD conversion unit that converts the electrical signal into a digital signal based on a result of comparing the potential of the unit and the potential of the reference signal input unit. The pixel includes at least a first pixel and a second pixel different from the first pixel, and the imaging apparatus further includes the potential of the conversion unit, the potential of the input unit, and the reference The start of a reset period for resetting at least one of the potential of the signal input unit is different between the first pixel and the second pixel, and the electric signal is input from the conversion unit to the input unit. When to An imaging apparatus characterized by comprising a control unit to simultaneously between the second pixel and the first pixel.

  Another aspect includes a conversion unit that generates an electrical signal based on an incident electromagnetic wave, an input unit that receives the electrical signal from the conversion unit, a reference signal input unit that receives a reference signal, and the input A plurality of pixels each having an AD conversion unit that converts the electrical signal into a digital signal based on a result of comparing the potential of the unit and the potential of the reference signal input unit, and is common to the plurality of pixels An image pickup apparatus having a potential supply unit that supplies a reset potential of the first pixel, wherein the plurality of pixels are different from the first pixel and the first pixel, and the potential supply is performed more than the first pixel. At least a second pixel that has a long electrical path to which the reset potential is supplied from the unit, and the reset potential is applied to at least one of the conversion unit, the input unit, and the reference signal input unit. Lise to supply The door period, an imaging apparatus characterized by having the signal supply section to start the second pixel earlier than the first pixel.

  In another aspect, a conversion unit that generates an electric signal based on an incident electromagnetic wave, an input unit to which the electric signal is input, an input unit to which the electric signal is input from the conversion unit, and a reference signal A plurality of reference signal input sections each having an input reference signal input section and an AD conversion section that converts the electrical signal into a digital signal based on a result of comparing the potential of the input section with the potential of the reference signal input section And a potential supply unit that supplies a common reset potential to the plurality of pixels. The plurality of pixels include the first pixel and the first pixel. And at least a second pixel having a larger resistance in an electrical path to which the reset potential from the potential supply unit is supplied than the first pixel, and the imaging device further includes the conversion unit , The input unit, and the reference signal An input unit, a reset period and supplies the reset potential to at least one of an imaging apparatus characterized by having the signal supply section to start the second pixel earlier than the first pixel.

  According to the present invention, variation in reset potential that occurs when a pixel is reset can be reduced.

Schematic diagram showing an example of the configuration of the imaging device, and a schematic diagram showing an example of the configuration of the signal supply unit and the pixel Schematic diagram showing an example of the configuration of the counter and a timing diagram showing an example of the operation of the imaging device Timing diagram showing an example of pixel reset operation, schematic diagram showing an example of the configuration of the imaging device, and schematic diagram showing parasitic capacitance and parasitic resistance of the power supply line Diagram showing power line potential and current for pixel reset operation Sectional drawing which showed an example of a structure of an imaging device Schematic diagram showing an example of a signal supply unit and pixels Schematic diagram showing an example of a signal supply unit and pixels Schematic diagram showing an example of a signal supply unit and pixels Timing diagram showing an example of operation of imaging device Schematic diagram showing an example of an imaging system

Example 1
The imaging apparatus of the present embodiment will be described with reference to the drawings.

  FIG. 1A is a block diagram illustrating an example of an imaging apparatus according to the present embodiment. The pixel array 1000 is provided with a plurality of pixels 100 arranged in a matrix. The pixels 100 included in the block 1 and the block 2 have branches 100-1 to 100-4 in order from the first column to the fourth column as viewed from the vertical scanning circuit 2 in the first row as viewed from the signal supply unit 3. Numbers are attached and numbers are attached. Hereinafter, when the pixel 100 is simply described as the M-th row (M is an integer equal to or greater than 1), the pixel 100 is regarded as counted from the signal supply unit 3. Further, when the pixel 100 is simply described as the Nth column (N is an integer of 1 or more), it is treated as counted from the vertical scanning circuit 2. Similarly to the pixel 100 in the first row, the pixels 100 in the second row included in the block 1 are labeled as pixels 100-5 to 100-8 from the first column to the fourth column in order. The vertical scanning circuit 2 selects the pixels 100 for each row. The signal supply unit 3 supplies the pixel 100 with a clock signal CLK, a ramp signal RAMP, a signal PRES, and a signal RRES.

  The digital signal output from the pixel 100 is given to the horizontal scanning circuit 4. The horizontal scanning circuit 4 sequentially outputs the digital signals output from the pixels 100 in each column to the external output unit 5.

  Pixels 100-1, 100-2, 100-5, and 100-6 belong to block 1. The signal supply unit 3 outputs a common signal PRES_1 to each of the pixels 100 belonging to the block 1. The signal supply unit 3 outputs a common signal RRES_1 to each of the pixels 100 belonging to the block 1. The pixels 100-3, 100-4, 100-7, and 100-8 belong to the block 2. The signal supply unit 3 outputs a common signal PRES_2 to each of the pixels 100 belonging to the block 2. The signal supply unit 3 outputs a common signal RRES_2 to each of the pixels 100 belonging to the block 2.

  Block 1 and block 2 in this embodiment correspond to the first block and the second block described in the claims, respectively. Further, the pixels 100-1 and 100-2 of the block 1 are electrically connected to the signal supply unit 3 through signal lines different from each other. However, in this embodiment, the signal supply unit 3 includes the pixels 100-1 and 100-. 2 are supplied with common signals PRES_1 and RRES_1.

  FIG. 1B is a schematic diagram illustrating an example of the pixel 100 of the present embodiment. The analog signal output unit 6 includes a photoelectric conversion unit 9, a transistor 10, and a transistor 11. A signal PTX is supplied from the vertical scanning circuit 2 to the control node of the transistor 10. When the vertical scanning circuit 2 sets the signal PTX to a high level (hereinafter, the high level is expressed as an H level. Similarly, the low level is expressed as an L level), the transistor 10 generates an electric signal generated by the photoelectric conversion unit 9. Is transferred to the input node of transistor 12. The input node of the transistor 12 is the input unit of the AD conversion unit described in the claims. When the signal supply unit 3 sets the signal PRES to the H level, the potential of the input node of the transistor 12 is reset based on the power supply voltage VDD.

  The AD conversion unit 200 includes a comparison unit 7 and a memory unit 8. The comparison unit 7 includes a transistor 12, a transistor 13, and a transistor 14. A signal RRES is given from the signal supply unit 3 to the control node of the transistor 13. When the signal supply unit 3 sets the signal RRES to the H level, the transistor 13 becomes conductive, and the potentials of the input node of the transistor 15 and one node of the capacitor 16 are reset based on the power supply voltage VDD. A ramp signal RAMP is supplied from the signal supply unit 3 to one main node of the transistor 14. A signal RAMP_ST is supplied from the signal supply unit 3 to the control node of the transistor 14. When the signal supply unit 3 sets the signal RAMP_ST to the H level, the ramp signal RAMP is supplied to the input node of the transistor 15. The reference signal shown in the claims is the ramp signal RAMP in this embodiment. Further, the reference signal input section shown in the claims is an input node of the transistor 15 in this embodiment.

  A power supply line for supplying the power supply voltage VDD is commonly connected to the transistors 11, 13, 17, 18, 19, and 20. The power supply voltage VSS is commonly connected to the transistors 21, 22 and 23. The respective power supply lines for supplying the power supply voltages VDD and VSS are commonly connected to the pixels 100 of a plurality of blocks.

  The memory unit 8 includes a counter 24. The signal supply unit 3 supplies the clock signal CLK to the counter 24. Further, the signal supply unit 3 supplies a signal ST to the counter 24. When the signal supply unit 3 sets the signal ST to the H level, the counter 24 starts counting the clock signal CLK. A signal obtained by the counter 24 counting the clock signal CLK is referred to as a count signal CNT. Further, the counter 24 holds a count signal when the signal value of the comparison result signal CMP output from the comparison unit 7 changes.

  FIG. 2A is a diagram showing the configuration of the counter 24. The counter 24 has a plurality of T-type flip-flop circuits. A signal ST is supplied from the signal supply unit 3 to the reset terminal of each flip-flop circuit. When the signal ST is at L level, each flip-flop circuit is reset. The switch 25 becomes conductive when the signal value of the comparison result signal CMP is L level, and the clock signal CLK is input to the flip-flop circuit. The switch 25 becomes non-conductive when the signal value of the comparison result signal CMP is at the H level, and the clock signal CLK is not input to the flip-flop circuit. Each flip-flop circuit holds the signal value at the timing when the switch 25 is switched from the conductive state to the non-conductive state when the AD start signal ST is at the H level. That is, the counter 24 holds a count signal when the signal value of the comparison result signal CMP output from the comparison unit 7 changes.

  Next, the operation of the pixels 100 belonging to the block 1 and the block 2 in the imaging device shown in FIG. 1A will be described with reference to FIG.

  At time t <b> 1 </ b> _ <b> 1, the signal supply unit 3 resets the potential of the input node of the transistor 12 by setting the signal PRES_1 output to the pixel 100 of the block 1 to the H level. Further, the signal supply unit 3 sets the signal RRES_1 to the H level at the same time as setting the signal PRES_1 to the H level, and initializes the potential of the capacitor 16. Thereafter, the signal supply unit 3 sets the signal PRES_1 and the signal RRES_1 to the L level. Time t1_1 is the start time of the reset period of the pixels 100 belonging to the block 1.

  At time t <b> 1 </ b> _ <b> 2, the signal supply unit 3 resets the potential of the input node of the transistor 12 by setting the signal PRES_2 output to the pixel 100 of the block 2 to the H level. Further, the signal supply unit 3 initializes the potential of the capacitor 16 by setting the signal RRES_2 to the H level at the same time as setting the signal PRES_2 to the H level. Thereafter, the signal supply unit 3 sets the signal PRES_2 and the signal RRES_2 to the L level. Time t1_2 is the start time of the reset period of the pixels 100 belonging to the block 2.

  At time t2, the vertical scanning circuit 2 sets the signal PTX output to the pixels 100 of the block 1 and block 2 to H level and then to L level. As a result, the electrical signal generated by the photoelectric conversion unit 9 is simultaneously transferred to the control node of the transistor 12 in each of the plurality of pixels 100.

  At time t3, the signal supply unit 3 sets the signal RAMP_ST output to the pixels 100 of the block 1 and block 2 to the H level, thereby changing the potential depending on the time of the ramp signal RAMP supplied to the pixel 100 of the block 1. Start. At time t3, the signal supply unit 3 sets the signal ST output to the pixels 100 of the block 1 and block 2 to the H level.

  For example, it is assumed that the magnitude relationship between the potential of the input node of the transistor 12 and the potential of the input node of the transistor 15 is reversed at time t4. Then, the signal value of the comparison result signal CMP1 output from the comparison unit 7 changes from L level to H level. The memory unit 8 holds the count signal CNT at time t4. Each pixel 100 belonging to the block 1 and the block 2 holds the signal value of the count signal when the signal value of the comparison result signal CMP changes from the L level to the H level.

  Here, at time t <b> 5, the signal supply unit 3 stops changing the potential depending on the time of the ramp signal RAMP supplied to the pixels 100 of the block 1 and block 2. The AD conversion period of block 1 and block 2 is the period from time t3 to time t5.

  After time t5, the horizontal scanning circuit 4 sequentially outputs the count signal CNT held in the memory unit 8 of each pixel 100 from the memory unit 8 of each pixel 100 and sequentially transfers it to the external output unit 5.

  Next, the reset timing of each of the blocks 1 to 3 shown in FIG. 1A will be described with reference to FIG.

  PRES_1 and RRES_1 shown in FIG. 3A are signals output from the signal supply unit 3 to the pixels 100 belonging to the block 1 described with reference to FIG. Similarly, PRES_2 and RRES_2 are signals output from the signal supply unit 3 to the pixels 100 belonging to the block 2. FIG. 3A further shows signals PRES_3 and RRES_3 output from the signal supply unit 3 to the pixels 100 belonging to the block 3. The block 3 is provided in an area farther from the vertical scanning circuit 2 than the block 2 in the imaging apparatus shown in FIG. Block 2 is sandwiched between blocks 1 and 3. The signal supply unit 3 simultaneously sets the signals PRES_1 and RRES_1 output to the block 1 to the H level. Thereafter, the signals PRES_2 and RRES_2 output to the block 2 are set to the H level. Thereafter, the signals PRES_3 and RRES_3 output to the block 3 are set to the H level. That is, the imaging apparatus of the present embodiment varies the timing for resetting the input node of the AD conversion unit 200 and the timing for resetting the input node of the ramp signal RAMP of the comparison unit 7 for each block. On the other hand, when the signal supply unit 3 simultaneously sets the signal PRES output to the pixel 100 of each block to the H level, a current flows from the input node of the AD conversion unit 200 of each pixel 100 to the power supply line that supplies the power supply voltage VDD. . As a result, the potential of the power supply voltage VDD varies, and the reset potential of the input node of the AD conversion unit 200 varies. Further, even when the signal supply unit 3 simultaneously sets the signal RRES output to the pixels 100 of each block to the H level, the power supply voltage VDD from the input node of the ramp signal RAMP of the comparison unit 7 of each pixel 100 and the capacitive element 16. Current flows through the power supply line that supplies the power. As a result, the potential of the power supply voltage VDD varies, and the reset node of the capacitor element 16 and the input node of the ramp signal RAMP of the comparison unit 7 of each pixel 100 vary. This causes a decrease in AD conversion accuracy.

  In the imaging apparatus according to the present embodiment, the timing for resetting the input node of the AD conversion unit 200 is different for each block. As a result, it is possible to reduce the current that simultaneously flows into the power supply line that supplies the power supply voltage VDD, as compared with the case where all the blocks simultaneously reset the input nodes of the AD conversion unit 200. Therefore, fluctuations in the potential of the power supply voltage VDD can be reduced. Therefore, fluctuations in the reset potential of the input node of the AD conversion unit 200 can be reduced. Further, the timing for resetting the input node of the ramp signal RAMP of the comparison unit 7 and the capacitor 16 is different for each block. As a result, it is possible to reduce the current that simultaneously flows into the power supply line that supplies the power supply voltage VDD, as compared with the case where all the blocks simultaneously reset the input node of the ramp signal RAMP of the comparison unit 7 and the capacitor 16. Thereby, fluctuations in the input potential of the ramp signal RAMP of the comparison unit 7 and the reset potential of the capacitive element 16 can be reduced, and a decrease in AD conversion accuracy can be reduced.

  Further, the image pickup apparatus according to the present embodiment can obtain further effects by setting the signals PRES and RRES to the H level from a block apart from the potential supply unit 300 that supplies the power supply voltage VDD. Until now, as described with reference to FIG. 3A, the signal supply unit 3 sequentially sets the signals PRES and RRES to the H level in the order of blocks 1, 2, and 3. Hereinafter, a mode in which the signal supply unit 3 sequentially sets the signals PRES and RRES to the H level in the order of the blocks 3, 2, 1 will be described.

  FIG. 3B is a diagram showing the potential supply unit 300 that supplies the power supply voltage VDD and the block of the pixel 100 together. The potential supply unit 300 outputs a common power supply voltage VDD for each row of the pixels 100. Further, each block of the pixel 100 is arranged so as to be away from the potential supply unit 300 in the order of blocks 1, 2, and 3.

  FIG. 3C is a diagram illustrating parasitic resistance and parasitic capacitance in the imaging device illustrated in FIG.

  Concerning the parasitic capacitance, when attention is paid to the reset of the input node of the AD conversion unit 200, the parasitic capacitance is present at the input node of the AD conversion unit 200 and the node of the transistor 10 electrically connected to the input node of the AD conversion unit 200. is there. When attention is paid to resetting of the potential of the input node of the comparison unit 7, there is a parasitic capacitance of the input node of the comparison unit 7. Including the parasitic capacitance of these pixels 100, FIG. 3C shows one capacitance element. When the signal supply unit 3 sets the signal PRES to the H level, a current flows from the parasitic capacitance of the pixel 100 to the power supply line that supplies the power supply voltage VDD. Further, the power supply line itself that supplies the power supply voltage VDD has a parasitic resistance. In the configuration shown in FIG. 3C, the parasitic resistance of the power supply line that supplies the power supply voltage VDD increases as the distance from the potential supply unit 300 increases.

  For simplification, FIG. 4A shows the parasitic capacitances CP1 and CP2 of the two pixels 100 and the parasitic resistances R1 and R2 of the power supply line that supplies the power supply voltage VDD, as shown in FIG. It is a figure. Each of the switches SW1 and SW2 is a simplified illustration of the reset operation of the pixel 100. That is, when the switches SW1 and SW2 are turned on, the input node of the AD conversion unit 200, the input node of the ramp signal RAMP of the comparison unit 7, and the potential of the capacitor 16 are reset. Here, it is assumed that the current i1 + i2 flows through the parasitic resistance R1. In addition, the potential of the node of the parasitic capacitance CP1 that is electrically connected to the switch SW1 is set to the potential V1. Further, the potential of the node of the parasitic capacitance CP2 electrically connected to the switch SW1 is set to the potential V2.

  FIG. 4B shows changes in the potentials V1 and V2 when the switches SW1 and SW2 are simultaneously turned on at the time t10 shown in FIG. 4B, and the current flowing through the power supply line that supplies the power supply voltage VDD. FIG. In FIG. 4B, it is assumed that the potentials V1 and V2 are equal before time t10. When the switch SW1 is turned on, a current i1 flows between the parasitic capacitor CP1 and the power supply line as shown in FIG. When the switch SW2 is turned on, a current i2 flows between the parasitic capacitance CP2 and the power supply line as shown in FIG. The current i2 is smaller than the current i1 by the amount affected by the parasitic resistance R2. That is, the parasitic capacitance CP2 has a larger time constant than the parasitic capacitance CP1.

  As a result, as shown in FIG. 4B, the amount of change in potential per unit time is smaller in the potential V2 than in the potential V1. That is, the values of the potential V1 and the potential V2 are different during the period from the time t10 to the time t11.

  The potential difference V1-V2 becomes 0 if a sufficient time has elapsed from the start of resetting, such as after time t11. However, when the time from time t10 to time t11 cannot be taken, the potential difference V1-V2 remains. Further, if a period from time t10 to time t11 is to be provided, speeding up of the imaging device may be hindered.

  As described above, the pixel 100 farther from the potential supply unit 300 takes time to reset the parasitic capacitance CP. That is, it is assumed that the reset is completed for the pixels 100 connected to one power supply line at the same time after the reset is started at the same time before the reset potentials of the respective pixels 100 are aligned. In this case, as the pixel 100 is farther from the potential supply unit 300, the amount of change in the potential of the parasitic capacitance CP from the start to the end of the reset becomes smaller. Thereafter, when an image is generated using the electric signal generated by the photoelectric conversion unit 9, shading based on the distribution of potentials of the parasitic capacitance CP may occur in the image.

  FIG. 4C shows the changes in the potentials V1 and V2 and the current flowing through the power supply line that supplies the power supply voltage VDD when the switch SW1 is turned on after the switch SW2 is turned on. It is. At time t20, the switch SW20 is turned on. As a result, the reset of the parasitic capacitance CP2 having a time constant larger than the parasitic capacitance CP1 is started before the parasitic capacitance CP1. A current i2 flows through the parasitic resistance R1. At the timing described with reference to FIG. 4B, the current i1 + i2 flows through the parasitic resistance R1. Therefore, the amount of current flowing through the power supply line is smaller than when the switches SW1 and SW2 are simultaneously turned on. Therefore, the voltage drop of the power supply voltage VDD is reduced. Therefore, since the parasitic capacitance CP2 is reset at a higher voltage than when the switches SW1 and SW2 are simultaneously turned on, the period required for resetting can be shortened.

  Thereafter, the switch SW1 is turned on to start resetting the parasitic capacitance CP1. The parasitic capacitance CP1 has a smaller time constant than the parasitic capacitance CP2. Therefore, when the switches SW1 and SW2 are both in a conductive state, the potential V1 has a larger change in potential per unit time than the potential V2. Accordingly, the difference between the potential V2 and the potential V1 decreases with the passage of time. At time t21, the difference between the potential V2 and the potential V1 becomes almost zero. Even before the potentials of the parasitic capacitances CP1 and CP2 are settled, if the difference between the potentials V1 and V2 is almost zero, variations in the reset potential for each pixel 100 can be reduced. Therefore, shading is unlikely to occur in an image generated based on the electrical signal generated by the photoelectric conversion unit 9.

  Compared to the period from time t10 to time t11 shown in FIG. 4B, the period from time t20 to time t21 shown in FIG. 4C is shorter. Therefore, even if a reset period until the respective potentials of the parasitic capacitances CP1 and CP2 are settled cannot be provided, shading is unlikely to occur in the image.

  In the present embodiment, the mode in which the vertical scanning circuit 2 sets the signal PTX to the L level while the signal supply unit 3 sets the signal PRES to the H level has been described. As another form, the vertical scanning circuit 2 may set the signal PTX to the H level and reset the photoelectric conversion unit 9 while the signal supply unit 3 sets the signals PRES and RRES to the H level. In the case of this embodiment, the timing for resetting the potential of the photoelectric conversion unit 9 can be made different among the plurality of pixels 100. Thereby, compared with the form which resets the electric potential of the photoelectric conversion unit 9 simultaneously in the plurality of pixels 100, the fluctuation of the electric potential of the power supply voltage VDD can be reduced.

  Further, in the imaging apparatus of the present embodiment, the signal PTX that the vertical scanning circuit 2 outputs to all the pixels 100 at the same time is set to H level, and the electric signal generated by the photoelectric conversion unit 9 is simultaneously transferred to the input node of the AD conversion unit 200. It is good also as a form. Thereby, a global electronic shutter operation can be performed. The control unit that causes the imaging apparatus to perform a global electronic shutter includes a vertical scanning circuit 2 and a signal supply unit 3 in this embodiment.

  Further, the block 1 and the block 2 described with reference to FIG. 1A of the present embodiment may be in a form in which each has at least one pixel 100. That is, in the imaging apparatus of the present embodiment, the electrical signal generated by the photoelectric conversion unit 9 is simultaneously transferred to the control node of the transistor 12 by the first pixel 100 of the block 1 and the second pixel 100 of the block 2. . The timing for starting resetting of the control node of the transistor 12 may be different between the first pixel 100 and the second pixel 200.

  In the present embodiment, the AD conversion using the ramp signal RAMP has been described as an example. The present embodiment is not limited to this form. Other AD conversion modes having a comparator include, for example, a successive approximation type and a pipeline type AD conversion. Even in these forms, the timing for starting the reset may be different for each block.

  As a form of the imaging device in which the pixel 100 includes the comparison unit 7 and the memory unit 8, there is a so-called back-illuminated imaging device. A cross-sectional view of a pixel 100 as an example of a back-illuminated imaging device is shown in FIG. The light that has entered the microlens 28 enters the photoelectric conversion unit 9 through the color filter 29. The wiring layer 30 is provided on the side opposite to the microlens 28 when viewed from the photoelectric conversion unit 9. The wiring layer 30 includes an AD conversion unit 200. That is, the photoelectric conversion unit 9 is provided between the microlens 28 and the AD conversion unit 200. In this back-illuminated imaging device, the pixel 100 having the comparison unit 7 and the memory unit 8 can be configured while suppressing a decrease in the light receiving area of the photoelectric conversion unit 9.

  Although a mode in which each block has a plurality of pixels 100 has been described, a mode in which one block includes one pixel 100 may be employed.

  In this embodiment, the pixel 100 has the AD conversion unit 200, and the signal supply unit 3 supplies the signals PRES and RRES to the plurality of pixels 100. The present embodiment is not limited to this form, and the AD conversion unit 200 may be provided outside the pixel array in which the matrix-like pixels 100 are arranged. For example, the present invention can be implemented even if the AD conversion unit 200 includes a column-parallel AD conversion unit 200 provided corresponding to the column in which the pixels 100 are arranged.

  In the present embodiment, the imaging apparatus having the photoelectric conversion unit 9 has been described as an example of the conversion unit that generates an electric signal based on an incident electromagnetic wave. The conversion unit may be a conversion unit that converts electromagnetic waves such as X-rays, ultraviolet rays, and infrared rays into electric signals.

(Example 2)
The imaging apparatus of the present embodiment will be described focusing on differences from the first embodiment. In the imaging apparatus of the present embodiment, the signal supply unit 3 generates a reset signal based on the logical sum of a plurality of signals having different delay amounts.

  In this embodiment, the timing of resetting the input node of the ramp signal RAMP and the capacitive element 16 is made different between the plurality of comparison units 7 by using the parasitic resistance of the signal line that transmits the signal RRES.

  FIG. 6 is a diagram illustrating the pixel 100 of the present embodiment and signal lines for transmitting the signals Pre-RRES1 and Pre-RRES2. The first signal line 31 is supplied with the signal Pre-RRES1 from one end side of the imaging device, and the second signal line 32 is a signal from the end side opposite to the one end portion of the imaging device. Pre-RRES2 is given. The timings at which the signal values of the signal Pre-RRES1 and the signal Pre-RRES2 change are the same.

  In the first signal line 31 and the second signal line 32, the signals Pre-RRES1 and Pre-RRES2 are delayed due to the parasitic resistance 33 and the parasitic capacitance 34 existing in the respective signal lines. That is, in the first signal line 31, the delay of the signal Pre-RRES1 increases as the electrical path from the supply unit of the signal Pre-RRES1 becomes longer. That is, in the first signal line 31, the delay of the signal Pre-RRES1 increases from the left to the right in FIG. On the other hand, in the second signal line 32, the delay of the signal Pre-RRES2 increases from the right to the left in FIG.

  The delay amount of the signals Pre-RRES1 and Pre-RRES2 can be adjusted by the parasitic resistance 33 of the signal line. The adjustment of the signal parasitic resistance 33 can be, for example, a change in the wiring thickness of the signal line. The signals RRES of the first signal line 31 and the second signal line 32 having different delay increasing directions are output to the AND circuit 50. A signal output from the AND circuit 50 is a signal RRES. The signal PRES is a signal generated based on a logical sum of a plurality of signals having different delay amounts.

  It is assumed that the first signal line 31 and the second signal line 32 have the same resistance value of the parasitic resistor 33 and the capacitance value of the parasitic capacitor 34. In this case, the output of the AND circuit 50 having the smallest difference between the electrical path from the supply unit of the signal Pre-RRES1 and the electrical path from the supply unit of the signal Pre-RRES2 first becomes the H level. For example, the first signal line 31 and the second signal line 32 have exactly the same length. In this case, the output of the AND circuit 50 from which the signals Pre-RRES1 and Pre-RRES2 are output from the center of each of the first signal line 31 and the second signal line 32 is the first among all the AND circuits 50. Becomes H level. In FIG. 6, in the AND circuit 50, the output of the AND circuit 50-2 first becomes H level.

  Thereafter, the output sequentially goes to the AND circuit 50 from the center of each of the first signal line 31 and the second signal line 32 toward one end and the other end. That is, in FIG. 6, after the output of the AND circuit 50-1 first becomes H level, the outputs of the AND circuits 50-1 and 50-3 become H level almost simultaneously.

  As described above, in the imaging apparatus according to the present exemplary embodiment, the timing at which the signal RRES changes from the L level to the H level in the plurality of pixels 100 using the parasitic resistance 33 and the parasitic capacitance 34 of the signal line that transmits the signal RRES. Can be different. As a result, the image pickup apparatus according to the present embodiment can reduce the current that flows simultaneously to the power supply line that supplies the power supply voltage VDD, as compared to a mode in which the signal RRES is changed from the L level to the H level simultaneously for all pixels. Thereby, fluctuations in the input potential of the ramp signal RAMP of the comparison unit 7 and the reset potential of the capacitive element 16 can be reduced, and a decrease in AD conversion accuracy can be reduced.

  In this embodiment, the imaging apparatus having the AND circuit 50 that generates the signal RRES has been described. As another example, the imaging apparatus may include an AND circuit that generates the signal PRES. Also in this case, the signal supply unit 3 may generate the signal PRES based on the logical sum of a plurality of signals having different delay amounts.

(Example 3)
The imaging apparatus of the present embodiment will be described focusing on differences from the second embodiment.

  FIG. 7 shows a pixel array 1000 in which pixels 100 are provided in a matrix, a signal supply unit 3000 that supplies a signal RRES, a signal line 35 that transmits the signal RRES, and power supply units 2000-1 and 2000-2. FIG.

  The power supply units 2000-1 and 2000-2 are respectively provided on one end side of the pixel array and on the end side opposite to the one end.

  In the imaging apparatus of this embodiment, the electric power supplied from the signal supply unit 3000 to the pixel 100 in the column having the longest electrical path among the pixels 100 in all columns is compared with the power supply units 2000-1 and 2000-2. The target route is the shortest.

  The signal line 35 that transmits the signal RRES has a parasitic resistance 36 and a parasitic capacitance 37. Therefore, the delay of the signal RRES increases as the electrical path from the signal supply unit 3000 becomes longer. Thus, when the signal supply unit 3000 sets the signal RRES to the H level, the pixel 100 in the column having the longest electrical path from the power supply units 2000-1 and 2000-2 is the first among the pixels 100 in all columns. The signal RRES becomes H level. Thereafter, the signal RRES becomes H level in order from a short column to a long column in the electrical path from the signal supply unit 3000. Also in the pixels 100 in the same column, the signal RRES becomes H level in order from the pixel 100 having the short electrical path from the signal supply unit 3000 to the pixel 100 having the long electrical path. The power supply unit 2000 supplies the power supply voltage VDD for each row. In one row to which the common power supply voltage VDD is supplied, the signal RRES becomes H level in order from the pixel 100 having the long electrical path from the power supply unit 2000 to the pixel 100 having the shortest electrical path. Thereby, the imaging apparatus of a present Example can acquire the effect similar to the imaging apparatus of Example 2. FIG.

Example 4
The imaging apparatus of the present embodiment will be described focusing on differences from the first embodiment.

  FIG. 8 is a diagram illustrating the configuration of the imaging apparatus according to the present embodiment.

  In this embodiment, the pixel 100 performs correlated double sampling (hereinafter, referred to as CDS, CDS is an abbreviation for Correlated Double Sampling).

  The arrangement of a plurality of blocks having the pixels 100 can be the same as that in FIG.

  FIG. 8 shows an example of the configuration of the pixel 100 of this embodiment. 8, members having the same functions as those of the pixel 100 in FIG. 1B described in the first embodiment are denoted by the same reference numerals as those in FIG.

  The pixel 100 illustrated in FIG. 8 includes a transistor 38, a current source 39 that supplies current to the transistor 38, and a capacitor provided between the transistor 38 and the transistor 12 with respect to the pixel 100 illustrated in FIG. It differs in having 40. Further, the pixel 100 illustrated in FIG. 8 is different from the pixel 100 illustrated in FIG. 1B in that it includes a switch 41 that resets the potential of the node on the transistor 12 side of the capacitor 40. The switch 41 is controlled by a reset signal CRES supplied by the vertical scanning circuit 2. Further, the pixel 100 illustrated in FIG. 8 is different from the pixel 100 illustrated in FIG. 1B in that the memory unit 8 includes an N memory 42 that holds a count signal based on a noise signal. Other configurations can be the same as those of the pixel 100 illustrated in FIG. The transistor 38 is an amplification unit that amplifies the electric signal generated by the conversion unit and outputs the amplified signal to the input unit of the AD conversion unit 200. The signal holding unit shown in the claims is an input node of the transistor 38 in this embodiment.

  Next, FIG. 9 shows a timing chart of the operation of the imaging apparatus having the pixel 100 illustrated in FIG.

  During the period from time t21_1 to time t22_1, the signal supply unit 3 sets the reset signal PRES_1 supplied to the pixels 100 belonging to the block 1 to the H level. As a result, the potential of the input node of the transistor 38 of the pixel 100 belonging to the block 1 is reset. Therefore, the output voltage PDOUT_1 of the transistor 38 of the pixel 100 belonging to the block 1 is reset.

  In addition, during the period from time t21_1 to time t22_1, the signal supply unit 3 sets the signal RRES_1 to the H level. As a result, the potential of the control node of the transistor 15 and the capacitor 16 of the pixel 100 belonging to the block 1 is reset. As a result, the potential of the ramp signal RAMP of the pixels 100 belonging to the block 1 is reset.

  At time t21_1, the signal supply unit 3 sets the signal CRES to the H level. As a result, the switches 41 of the pixels 100 belonging to the block 1 and the block 2 are turned on, so that the potential of the input node of the transistor 12 is reset.

  Thereafter, the signal CRES is set to the L level at time t22_1, so that the switch 41 is turned off. Therefore, the capacitor 40 of the pixel 100 belonging to the block 1 and the block 2 holds the signal output from the transistor 38 when the signal RRES changes from the H level to the L level.

  During a period from time t21_2 to time t22_2, the signal supply unit 3 sets the reset signal PRES_2 supplied to the pixels 100 belonging to the block 2 to the H level. As a result, the potential of the input node of the transistor 38 of the pixel 100 belonging to the block 2 is reset. Therefore, the output voltage PDOUT_2 of the transistor 38 of the pixel 100 belonging to the block 2 is reset.

  Further, the signal RRES_2 is set to the H level during the period from the time t21_2 to the time t22_2. As a result, the potential of the control node of the transistor 15 and the capacitor 16 of the pixel 100 belonging to the block 2 is reset. As a result, the potential of the ramp signal RAMP of the pixels 100 belonging to the block 2 is reset.

  The signal supply unit 3 sets the signal CRES (not shown) output to the pixels 100 belonging to the block 2 to the H level at time t21_2 and to the L level at time t22_2. Accordingly, the capacitor 40 of the pixel 100 belonging to the block 2 holds the signal output from the transistor 38 at time t22_2.

  At time t23, the signal supply unit 3 sets the signal PRMP to the H level, thereby starting a change in potential depending on the time of the ramp signal RAMP. At time t23, the signal supply unit 3 sets the signal ST to the H level, so that the counter 24 starts counting the clock signal CLK.

  At time t24, the magnitude relationship between the potential of the control node of the transistor 12 and the potential of the control node of the transistor 15 is reversed. As a result, the signal value of the comparison result signal CMP changes. The counter 24 holds the count signal at this time.

  At time t25, the signal supply unit 3 sets the signal PRMP to the L level, thereby stopping the change in potential depending on the time of the ramp signal RAMP. The counter 24 outputs the held count signal to the memory 42. Hereinafter, the signal held in the memory 42 is referred to as a digital N signal. This digital N signal is a digital signal based on the potential of the input node of the reset transistor 38.

  The operation from the time t23 to the time t25 has been described for the pixels 100 belonging to the block 1. About the operation | movement regarding the time t25 from the time t23, it can be made the same with the timing of each operation | movement of the pixel 100 which belongs to the block 1 also about the pixel 100 which belongs to the block 2.

  Next, the pixel 100 generates a digital signal based on the electrical signal generated by the photoelectric conversion unit 9 based on the incident light.

  At time t26_1, the signal supply unit 3 sets the signal ST to the L level, so that the count signal is reset.

  During the period from time t26_1 to time t27_1, the signal supply unit 3 sets the signal RRES_1 to the H level, so that the control node of the transistor 15 of the pixel 100 belonging to the block 1 and the potential of the capacitor 16 are reset. As a result, the potential of the ramp signal RAMP of the pixels 100 belonging to the block 1 is reset.

  During the period from time t26_2 to time t27_2, the signal supply unit 3 sets the signal RRES_2 to the H level, so that the control node of the transistor 15 of the pixel 100 belonging to the block 2 and the potential of the capacitor 16 are reset. As a result, the potential of the ramp signal RAMP of the pixels 100 belonging to the block 2 is reset.

  The operations described below are operations common to the pixels 100 belonging to the block 1 and the block 2.

  Next, during a period from time t28 to time t29, the signal supply unit 3 sets the signal PTX to the H level. As a result, the electrical signal generated by the photoelectric conversion unit 9 is transferred to the input node of the transistor 38. The transistor 38 outputs a signal based on the potential of the input node. This signal is referred to as a photoelectric conversion signal.

  At time t30, the signal supply unit 3 sets the control signal PRMP of the transistor 14 to the H level, thereby starting a change in potential depending on the time of the ramp signal RAMP. At time t29, the signal supply unit 3 sets the signal ST to the H level, so that the counter 24 starts counting the clock signal CLK.

  At time t31, the magnitude relationship between the potential of the control node of the transistor 12 and the potential of the control node of the transistor 15 is reversed. The counter 24 holds the count signal at this time. The count signal held by the counter 24 is expressed as a digital S signal.

  At time t32, the signal supply unit 3 sets the signal PRMP to the L level, thereby stopping the change in potential depending on the time of the ramp signal RAMP.

  The vertical scanning circuit 2 causes the horizontal scanning circuit 4 to output the digital N signal held in the memory 42 and the digital S signal held in the counter 24 from the pixels 100 in each row. The horizontal scanning circuit 4 sequentially outputs a digital S signal and a digital N signal to the external output unit 5. The external output unit 5 outputs a difference signal between the digital S signal and the digital N signal to the outside of the imaging apparatus.

  The image pickup apparatus according to the present embodiment outputs a signal obtained by subtracting the digital N signal that is a noise component from the digital S signal to the outside, and thus can output a digital signal with a reduced noise component.

  Further, in the imaging apparatus according to the present embodiment, the timings at which the signals PRES and RRES are changed from the L level to the H level are different for each block. Thereby, the same effect as Example 1 can be acquired.

  In the image pickup apparatus according to the present embodiment, the external output unit 5 generates a difference signal between the digital S signal and the digital N signal. As another example, the pixel 100 or the horizontal scanning circuit 4 may generate a difference signal between the digital S signal and the digital N signal.

  In the imaging apparatus according to the present embodiment, the configuration in which each pixel 100 includes the memory 42 has been described. As another example, the memory 42 may be provided in each pixel column of the pixel array 1000. In this case, the memory 42 in each column holds digital N signals that are sequentially output from the pixels 100 in the corresponding column. Then, the horizontal scanning circuit 4 scans the memory 42 of each column, so that the memory 42 of each column sequentially outputs the digital N signal to the external output unit 5.

  In this embodiment, the signal CRES is a common signal in the block 1 and the block 2. However, in the image pickup apparatus of the present embodiment, the timing of changing the signal CRES from the L level to the H level may be different for each block as in the signals PRES and RRES. In addition, the imaging apparatus according to the present embodiment may change the timing of changing from the L level to the H level for each of the signals PRES, RRES, and CRES in the same block.

(Example 5)
An embodiment in which the imaging apparatus described in the first to fourth embodiments is applied to an imaging system will be described. Examples of the imaging system include a digital still camera, a digital camcorder, and a surveillance camera. FIG. 10 shows a block diagram when an imaging apparatus is applied to a digital still camera as an example of the imaging system.

  In FIG. 10, the imaging system includes a lens 102 that forms an optical image of a subject on the imaging device 104, a barrier 101 for protecting the lens 102, and a diaphragm 103 for changing the amount of light passing through the lens 102. In addition, the imaging system includes a signal processing unit 105 that processes an output signal output from the imaging device 104.

  The signal processing unit 105 includes a digital signal processing unit, and performs an operation of outputting a signal after performing various corrections and compressions on the signal output from the imaging device 104 as necessary.

  In addition, the imaging system includes a buffer memory unit 106 for temporarily storing image data, and a storage medium control unit 110 for recording on or reading from a recording medium. Further, the imaging system includes a removable recording medium 111 such as a semiconductor memory for recording or reading imaging data. The imaging system further includes an external interface unit 107 for communicating with an external computer, an overall control / arithmetic unit 109 for controlling various calculations and the entire digital still camera, and an imaging device 104. The imaging system further includes a timing generation unit 108 that outputs various timing signals to the signal processing unit 105. Here, the timing signal or the like may be input from the outside, and the imaging system only needs to include at least the imaging device 104 and the signal processing unit 105 that processes the output signal output from the imaging device 104.

2 Vertical scanning circuit 3 Signal supply unit 4 Horizontal scanning circuit 100 pixels

Claims (16)

A converter that generates an electrical signal based on an incident electromagnetic wave;
An input unit through which the electrical signal is input from the conversion unit;
A reference signal input unit to which a reference signal is input;
A driving method of an imaging apparatus having a plurality of pixels, each having an AD conversion unit that converts the electric signal into a digital signal based on a result of comparing the potential of the input unit and the potential of the reference signal input unit. There,
The plurality of pixels include at least a first pixel and a second pixel different from the first pixel,
The reset period for resetting at least one of the potential of the conversion unit, the potential of the input unit, and the potential of the reference signal input unit is different between the first pixel and the second pixel. And driving the electrical signal from the conversion unit to the input unit at the same time for the first pixel and the second pixel. A converter that generates an electrical signal based on an incident electromagnetic wave;
An input unit through which the electrical signal is input from the conversion unit;
A reference signal input unit to which a reference signal is input;
Based on the result of comparing the potential of the input unit and the potential of the reference signal input unit, each having a plurality of pixels each having an AD conversion unit that converts the electrical signal into a digital signal,
A driving method of an imaging apparatus having a potential supply unit that supplies a common reset potential to the plurality of pixels,
The plurality of pixels are different from the first pixel and the first pixel, and a second electric path to which the reset potential from the potential supply unit is supplied is longer than the first pixel. And at least a pixel of
In the second pixel, the reset period for resetting at least one of the potential of the conversion unit, the potential of the input unit, and the potential of the reference signal input unit is earlier than that of the first pixel. A driving method of an imaging apparatus, characterized by starting. A converter that generates an electrical signal based on an incident electromagnetic wave;
An input unit through which the electrical signal is input from the conversion unit;
A reference signal input unit to which a reference signal is input;
An AD converter that converts the electrical signal into a digital signal based on a result of comparing the potential of the input unit and the potential of the reference signal input unit;
Each having a plurality of pixels,
A driving method of an imaging apparatus having a potential supply unit that supplies a common reset potential to the plurality of pixels,
The plurality of pixels are different from the first pixel and the first pixel, and the resistance of an electrical path through which the reset potential from the potential supply unit is supplied is larger than that of the first pixel. And at least a second pixel,
In the second pixel, the reset period for resetting at least one of the potential of the conversion unit, the potential of the input unit, and the potential of the reference signal input unit is earlier than that of the first pixel. A driving method of an imaging apparatus, characterized by starting. The imaging device has a plurality of blocks each having a plurality of the pixels,
The method for driving an imaging apparatus according to claim 1, wherein the start of the reset period is made different between the plurality of blocks.   5. The driving method of the imaging apparatus according to claim 1, wherein the AD conversion unit further generates a digital signal based on the reset potential of the input unit.   6. The method of driving an imaging apparatus according to claim 1, wherein the electrical signal input to the input unit is a signal obtained by amplifying the electrical signal generated by the conversion unit. Each of the plurality of pixels further includes a signal holding unit,
The signal holding unit holds the electrical signal generated by the conversion unit,
The electric signal input to the input unit is a signal obtained by amplifying the electric signal held by the signal holding unit,
The reset period is a period in which at least one of the potential of the conversion unit, the potential of the input unit, the potential of the reference signal input unit, and the potential of the signal holding unit is reset. A method for driving the imaging apparatus according to claim 6. A converter that generates an electrical signal based on an incident electromagnetic wave;
An input unit through which the electrical signal is input from the conversion unit;
A reference signal input unit to which a reference signal is input;
An imaging device having a plurality of pixels each having an AD conversion unit that converts the electrical signal into a digital signal based on a result of comparing the potential of the input unit and the potential of the reference signal input unit,
The plurality of pixels include at least a first pixel and a second pixel different from the first pixel,
The imaging device further includes
The reset period for resetting at least one of the potential of the conversion unit, the potential of the input unit, and the potential of the reference signal input unit is different between the first pixel and the second pixel. And an image pickup apparatus comprising: a control unit configured to simultaneously input the electric signal from the conversion unit to the input unit between the first pixel and the second pixel. The control unit further includes a signal supply unit that supplies a reset signal for starting the reset period to the plurality of pixels.
The imaging apparatus according to claim 7, wherein the signal supply unit starts the reset period of each of the plurality of pixels based on a logical sum of a plurality of signals having different delay amounts. A converter that generates an electrical signal based on an incident electromagnetic wave;
An input unit through which the electrical signal is input from the conversion unit;
A reference signal input unit to which a reference signal is input;
Based on the result of comparing the potential of the input unit and the potential of the reference signal input unit, each having a plurality of pixels each having an AD conversion unit that converts the electrical signal into a digital signal,
An imaging device having a potential supply unit that supplies a common reset potential to the plurality of pixels,
The plurality of pixels are different from the first pixel and the first pixel, and a second electric path to which the reset potential from the potential supply unit is supplied is longer than the first pixel. And at least a pixel of
Signal supply for causing the second pixel to start a reset period for supplying the reset potential to at least one of the conversion unit, the input unit, and the reference signal input unit earlier than the first pixel. An imaging device comprising a portion. The signal supply unit supplies a reset signal for starting the reset period to the plurality of pixels;
Among the plurality of pixels, a pixel having a longer electrical path for the reset potential from the potential supply unit is more suitable than a pixel having a shorter electrical path for the reset potential from the potential supply unit. The imaging apparatus according to claim 10, wherein an electrical path of the reset signal from the camera is short. A converter that generates an electrical signal based on an incident electromagnetic wave;
An input unit to which the electrical signal is input;
An input unit through which the electrical signal is input from the conversion unit;
A reference signal input unit to which a reference signal is input;
An AD converter that converts the electrical signal into a digital signal based on a result of comparing the potential of the input unit and the potential of the reference signal input unit;
Each having a plurality of pixels,
A potential supply section for supplying a common reset potential to the plurality of pixels;
An imaging device having
The plurality of pixels are different from the first pixel and the first pixel, and the resistance of an electrical path through which the reset potential from the potential supply unit is supplied is larger than that of the first pixel. And at least a second pixel,
The imaging device further includes
Signal supply for causing the second pixel to start a reset period for supplying the reset potential to at least one of the conversion unit, the input unit, and the reference signal input unit earlier than the first pixel. An imaging device comprising a portion.   13. The signal supply unit according to claim 9, wherein the signal supply unit starts the reset period of each of the plurality of pixels based on a logical sum of a plurality of signals having different delay amounts. Imaging device. Each of the plurality of pixels further includes an amplification unit,
The imaging apparatus according to claim 8, wherein the electrical signal input to the input unit is a signal obtained by the amplification unit amplifying the electrical signal generated by the conversion unit. Each of the plurality of pixels further includes a signal holding unit,
The signal holding unit holds the electrical signal generated by the conversion unit,
The electric signal input to the input unit is a signal obtained by amplifying the electric signal held by the signal holding unit by the amplification unit,
15. The imaging apparatus according to claim 14, wherein the reset period is a period during which the reset potential is supplied to at least one of the conversion unit, the input unit, and the reference signal input unit. An imaging device according to any one of claims 8 to 15,
A signal processing unit configured to generate an image using the digital signal output from the imaging device.

Images