JP6410882B2 - Imaging device, imaging system, and driving method of imaging device - Google Patents

Description

  The present invention relates to an imaging apparatus, an imaging system, and a driving method for an imaging apparatus that convert incident rays into electric charges.

  An imaging device that photoelectrically converts incident light is known. As an example of such an imaging apparatus, Patent Document 1 discloses an imaging having a pixel having a photoelectric conversion unit that photoelectrically converts incident light and an AD conversion unit that converts a signal output from the photoelectric conversion unit into a digital signal. There is a device.

JP 2006-203736 A

  In some cases, a converter that generates charges based on incident lines and a bias line that applies a potential to the AD converter are electrically connected in common to the converters and AD converters that generate charges based on incident lines. In this case, there has been a problem that the fluctuation of the potential of the bias line caused by the operation of the conversion unit that generates charges based on the incident line reduces the AD conversion accuracy of the AD conversion unit.

  The present invention has been made in view of the above problems, and one aspect is to convert a charge based on an incident line and a signal based on the charge generated by the conversion section into a digital signal. An AD conversion unit, a first bias line electrically connected to the conversion unit, and a capacitive element that holds a voltage based on a potential of the first bias line, the AD conversion The image pickup apparatus is characterized in that the unit is driven based on the voltage held by the capacitor.

  Another aspect of the present invention is a pixel having a conversion unit that generates charges based on incident rays, and an AD conversion unit that converts a signal based on the charges generated by the conversion unit into a digital signal, and the conversion unit And a first bias line that supplies a common potential to the AD converter and a capacitive element, and a voltage based on the potential of the first bias line is applied to the capacitive element. In the driving method of the imaging apparatus, the AD converter is driven based on the voltage held and held in the capacitor.

  According to the present invention, it is possible to provide an imaging apparatus in which fluctuations in the potential of the bias line caused by the operation of the conversion unit that generates charges based on incident lines do not easily affect the operation of the AD conversion unit.

The figure which showed an example of the structure of an imaging device and a pixel An example of pixel configuration and an example of pixel operation The figure which showed another example of the structure of a pixel The figure which showed another example of a structure of an imaging device and a pixel Illustration of an example of an imaging system

  Embodiments will be described below with reference to the drawings.

Example 1
FIG. 1A is a schematic diagram illustrating the configuration of the imaging apparatus of the present embodiment.

  A pixel array 100 in FIG. 1A includes pixels 101 arranged in M rows and N columns. The bias circuit group 200 includes a bias circuit 201 that drives each pixel 101. In this embodiment, the bias circuit 201 is provided for each row. The bias circuit 201 in each row supplies a bias voltage to each pixel 101 in the row corresponding to the bias circuit 201. Each pixel 101 outputs a digital signal to the signal holding unit 500 via the output line 400. The signal holding unit 500 sequentially outputs digital signals to the output unit 600 by a horizontal scanning circuit (not shown). The output unit 600 outputs a digital signal to an output node 700 that is electrically connected to the outside of the imaging apparatus.

  FIG. 1B is a diagram illustrating a configuration of the pixel 101 illustrated in FIG. The pixel 101 includes a power supply voltage supply line 102, a GND potential supply line 103, a photodiode 104, a switch 105, a switch 106, an AD conversion unit 107, a switch 108, a capacitor element 109, and an output line 400. A ground voltage is applied to the GND potential supply line 103. Switch 105 becomes conductive when signal φRES is set to a high level (hereinafter, H level). Switch 106 becomes conductive when signal φTX is set to H level. Switch 108 becomes conductive when signal φS1 is set to H level. Signals φRES, φTX, and φS1 are signals given from a timing generator (not shown). The count signal line 111 and the control signal line 114 are electrically connected to the AD conversion unit 107. The photodiode 104 is a conversion unit that generates charges based on the incident line of this embodiment. The photodiode 104 of this embodiment is also a photoelectric conversion unit that generates charges generated by photoelectric conversion of incident light.

  FIG. 2A is a diagram illustrating an example of the configuration of the bias circuit 201 and the AD conversion unit 107 according to the present embodiment. The bias voltage generated by the bias circuit 201 is applied to the bias line 202. The AD conversion unit 107 includes capacitive elements C0, C1, and C2. The AD conversion unit 107 includes a comparator 140 having MOS transistors M2, M3, M4, M5, and M6. The MOS transistor M3 is a first input transistor to which a signal output from the photodiode 104 is given. The MOS transistor M4 is a second input transistor to which a ramp signal VRAMP that is a reference signal is applied. The comparator 140 outputs a comparison result signal, which is a comparison between the signal output from the photodiode 104 and the ramp signal VRAMP supplied from the vertical control circuit 300 via the ramp signal line 110 and the capacitive element C2, to the latch unit 112. To do. The AD conversion unit 107 includes a latch unit 112 that outputs a signal LATCH to the memory unit 113 based on the comparison result signal output from the comparator 140. In addition, the vertical control circuit 300 provides a count signal obtained by counting clock pulses to the memory unit 113 via the count signal line 111. Further, the vertical control circuit 300 outputs a signal φMEM to the memory unit 113 via the control signal line 114. The MOS transistor M2 is a current supply transistor that operates as a current source that drives the comparator 140. One node of the capacitive element 109 is electrically connected to the control node of the MOS transistor M2. Further, one main node of the MOS transistor M 2 is electrically connected to the GND potential supply line 103. The other main node of the MOS transistor M2 is electrically connected to the MOS transistors M3 and M4. The GND potential supply line 103 is the first bias line in this embodiment. The bias line 202 is the second bias line of this embodiment. The ramp signal VRAMP is a reference signal in this embodiment.

  Next, the operation of the pixel shown in FIG. 2A will be described with reference to FIG.

  Prior to the reset period, the signal φS1 is changed from H level to L level. Accordingly, the capacitor 109 holds a voltage based on the potential difference between the bias line 202 and the GND potential supply line 103 when the signal φS1 is set to the L level. The AD conversion unit 107 illustrated in FIG. 2A is driven based on the voltage held by the capacitor 109 and the potential of the GND potential supply line 103. More specifically, the current source of the comparator 140 of the AD conversion unit 107 is driven by the voltage held by the capacitor 109 and the potential of the GND potential supply line 103.

  Next, in the reset period, the signal φRES is set to the H level, and φTX is set to the H level. As a result, the charge of the photodiode 104 and the charge of one node of each of the capacitive elements C0 and C1 are reset.

  Signal φTX is set to L level, and φRES is set to L level. When the signal φRES is set to L level, the photodiode 104 accumulates charges generated by photoelectrically converting incident light. The period for accumulating this charge is the accumulation period.

  After the accumulation period, the signal φTX is set to H level and then to L level. As a result, the charges accumulated in the photodiode 104 are transferred to the capacitive elements C0 and C1, and a signal based on the transferred charges is applied to the control node of the MOS transistor M3.

  When the signal φTX is set to the L level, the vertical control circuit 300 starts a change depending on the time of the potential of the ramp signal line 110 as the AD conversion period. In addition, the vertical control circuit 300 outputs a count signal to the AD conversion unit 107 via the count signal line 111.

  Latch section 112 sets the signal value of signal φLATCH to H level when the signal output from comparator 140 changes. Receiving this H level signal φLATCH, memory unit 113 holds the count signal value when signal φLATCH becomes H level. The held count signal value is a digital signal based on the charge accumulated in the photodiode 104.

  The vertical control circuit 300 ends the change in potential depending on the time of the ramp signal VRAMP, whereby the AD conversion period ends.

  The vertical control circuit 300 sets the signal φMEM to the H level. The memory unit 113 outputs the digital signal held in the signal holding unit 500 via the output line 400.

  Then, the vertical control circuit 300 sets the signal φS1 to the H level.

  The potential of the GND potential supply line 103 varies as the photodiode 104 is reset and accumulated. On the other hand, the potential of the bias line 202 is constant. Therefore, when the control node of the MOS transistor M2 is directly connected to the bias line 202, when the potential of the GND potential supply line 103 changes, the gate source voltage of the MOS transistor M2 changes, and the drain current, that is, the comparator 140. The drive current changes. Since the operating point of the comparator 140 changes as the drive current of the comparator 140 changes, the accuracy of the comparison operation decreases. The reduction in accuracy of the comparison operation results in a reduction in AD conversion accuracy of the AD conversion unit 107, and thus the linearity of the analog-digital conversion characteristics of the AD conversion unit 107 is reduced. Further, due to the difference in the transient response due to the impedance of the GND potential supply line 103, the amount of fluctuation in the potential of the GND potential supply line 103 differs for each pixel 101. Thereby, since the AD conversion accuracy of the AD conversion unit 107 is different for each pixel, the image quality of the image generated by the imaging apparatus is lowered. In addition, between the pixels 101 that share the GND potential supply line 103, the variation in the GND potential caused by the operation of a certain pixel 101 reduces the AD conversion accuracy of the other pixels 101.

  On the other hand, providing a standby period until the potential of the GND potential supply line 103 is stabilized becomes a factor that hinders speeding up of the imaging device.

  In this embodiment, the capacitor 109 holds a voltage based on the potential difference between the bias line 202 and the GND potential supply line 103. As a result, the potential of the control node of the MOS transistor M2 also varies in accordance with the variation of the potential of the GND potential supply line 103. Accordingly, since the gate source voltage of the MOS transistor M2 does not easily vary, the drain current flowing through the comparator 140 is unlikely to vary. Accordingly, the AD conversion unit 107 can be made less susceptible to fluctuations in the potential of the GND potential supply line 103 without providing a standby time until the potential of the GND potential supply line 103 is stabilized.

  In addition, as shown in FIG. 2C, when the operation in the frame is performed in parallel in a plurality of frames in order to increase the frame rate, the operation of the photodiode 104 and the operation of the AD conversion unit 107 are performed in parallel. The influence of the fluctuation of the GND potential supply line 103 becomes large. Also in this case, by holding a signal based on the potential difference between the bias line 202 and the GND potential supply line 103 in a blank period such as a reading period, the AD conversion unit 107 is less likely to be subject to fluctuations in the GND potential supply line 103. Can do.

  The waveform of the signal φS1 in this embodiment is not limited to the waveform shown in FIG. If the timing at which the signal φS1 is changed from the H level to the L level is before the start of the AD conversion period, the AD conversion unit 107 detects the potential fluctuation of the GND potential supply line 103 due to the accumulation operation of the photodiode 104 in the AD conversion period. It can be made difficult to receive.

  Furthermore, in this embodiment, as an example of the AD conversion unit, a description has been given based on a mode in which a signal output from a conversion unit that generates charges based on incident rays is compared with a ramp signal. As another form, for example, an AD conversion unit such as a successive approximation type or a flash type may be used. Even with these forms of AD converters, the same effects as those of the imaging apparatus of the present embodiment can be obtained by driving the AD converters with the voltage held by the capacitor 109.

  In the present specification, the change of the potential depending on the time of the reference signal is described as being performed in a slope shape, but the reference signal may be changed in a staircase shape. A reference signal whose potential changes stepwise is also an example of a reference signal whose potential changes depending on time.

  In the present embodiment, the configuration in which one node of the capacitive element 109 is electrically connected to the control node of the MOS transistor M2 of the comparator 140 is shown. This embodiment is not limited to this form, and any form may be used as long as the AD conversion unit 107 is driven based on the voltage held by the capacitor 109. For example, the capacitor 109 holds a voltage based on the potential of the GND potential supply line 103 while the charge of the photodiode 104 is reset. The AD conversion unit 107 performs an AD conversion operation based on the voltage held by the capacitor 109 instead of the potential of the GND potential supply line 103. Accordingly, the AD conversion unit 107 can be configured to be less susceptible to fluctuations in the potential of the GND potential supply line 103. In other words, any configuration is possible as long as the capacitor 109 holds a voltage based on the potential of the GND potential supply line 103 and the AD converter 107 operates based on the voltage held by the capacitor 109. The timing at which the capacitor 109 holds the voltage based on the potential of the GND potential supply line 103 is not necessarily in a state where the charge of the photodiode 104 is reset. After the reset period shown in FIG. 2B, the AD conversion unit 107 performs AD conversion. A signal generated by this AD conversion is referred to as a digital N signal. During this AD conversion or before AD conversion, the capacitor 109 holds a voltage based on the potential of the GND potential supply line 103. After that, the AD conversion unit 107 performs AD conversion on a signal based on the charge generated by photoelectric conversion by the photodiode 104 based on the voltage held by the capacitor 109. A signal generated by this AD conversion is expressed as a digital S signal. The memory unit 113 holds the digital N signal and the digital S signal, respectively, and outputs them to the signal holding unit 500. For example, the output unit 600 outputs a signal obtained by subtracting the digital N signal from the digital S signal to the outside of the imaging apparatus. Thereby, the influence of the characteristic variation for each comparator 140 on the signal output to the outside of the imaging device can be reduced. When the AD conversion unit 107 is driven by the potential of the GND potential supply line 103, the potential of the GND potential supply line 103 may fluctuate due to AD conversion of each of the digital N signal and the digital S signal. In this case, even if the digital N signal is subtracted from the digital S signal, the influence of fluctuations in the potential of the GND potential supply line 103 remains, so that the AD conversion accuracy decreases. On the other hand, the voltage based on the potential of the GND potential supply line 103 is held at the time of AD conversion when the capacitor 109 generates a digital N signal or before AD conversion. AD conversion of the digital S signal is performed with the voltage held by the capacitor 109. Thereby, in the AD conversion of the digital S signal and the digital N signal, the AD conversion unit 107 is driven with a common voltage, so that the digital N signal can be suitably subtracted from the digital S signal.

  In this embodiment, a mode in which the capacitor holds a voltage based on the potential of the bias line is described. The voltage based on the potential of the bias line means that when a resistive element or other capacitive element is included in the electrical path between the bias line and the capacitive element, the resistive element or other capacitive element is removed from the bias line. Including the voltage applied via

  In this embodiment, the bias circuit 201 is provided for each row of the pixels 101. The present embodiment is not limited to this mode, and may be configured to include the bias circuit 201 for each column of the pixels 101.

  The photodiode 104 is an example of a conversion unit that generates charges based on incident rays. In addition, the conversion unit that generates charges based on incident rays may be configured to generate charges based on incident rays such as X-rays and infrared rays.

(Example 2)
With reference to the drawings, the imaging apparatus of the present embodiment will be described focusing on differences from the first embodiment.

  FIG. 3A is a diagram showing an example of the configuration of the pixel 101 of this embodiment. In FIG. 3 (a), the same reference numerals as those in FIG. 1 (b) are given in FIG. 3 (a) for configurations having the same functions as those of the image pickup apparatus described in FIG. 1 (b). The pixel 101 shown in FIG. 3A has a buffer circuit having MOS transistors M1 and M2. The buffer circuit of this embodiment is an example of an amplifier circuit. The electric charge output from the photodiode 104 via the switch 106 is given to the control node of the MOS transistor M2. The power supply voltage supply line 102 is electrically connected to one main node of the MOS transistor M2, and the MOS transistor M1 is electrically connected to the other main node. A signal is output to the AD converter 107 from a node provided in the electrical path between the MOS transistor M2 and the MOS transistor M1. The signal output to the AD conversion unit 107 is a signal based on the charge generated by the photodiode 104. One node of the capacitive element 122 and one node of the switch 121 are electrically connected to the control node of the MOS transistor M1. The GND potential supply line 103 is electrically connected to the other node of the capacitor 122. The third bias line 203 is electrically connected to the other node of the switch 121. Switch 121 becomes conductive when signal φS2 output from a timing generator (not shown) is set to H level, and becomes non-conductive when set to L level. The configuration of the AD conversion unit 107 can be the same as that shown in FIG. The capacitive element 122 is the second capacitive element of this embodiment. The switch 121 is the second switch of this embodiment.

  The operation of the imaging apparatus illustrated in FIG. 3A can be the same as that in FIG. Further, the signal φS2 can be operated in the same manner as the signal φS1.

  In this embodiment, by providing a buffer circuit in the electrical path between the photodiode 104 and the AD converter 107, the driving force of the buffer can be adjusted according to the input load of the AD converter 107. Further, separating the photodiode 104 and the AD conversion unit 107 makes it difficult for noise generated by the operation of the AD conversion unit 107 to be input to the photodiode 104.

  In this embodiment, a buffer circuit is further electrically connected to the GND potential supply line 103 to which the photodiode 104 and the AD conversion unit 107 are electrically connected in common. In the imaging device of this embodiment, the capacitive element 122 holds a voltage based on the potential difference between the third bias line 203 and the GND potential supply line 103. The buffer circuit is driven by the voltage held by the capacitor 122 and the potential of the GND potential supply line 103. As a result, the potential of the control node of the MOS transistor M1 also varies according to the variation of the potential of the GND potential supply line 103. Therefore, the gate-source voltage of the MOS transistor M1 hardly changes. As a result, the buffer circuit is less susceptible to fluctuations in the potential of the GND potential supply line 103.

  In this embodiment, the signals φS1 and φS2 are described as having the same waveform, but the signal φS2 may be a signal having a waveform different from that of the signal φS1. If the timing at which the signal φS2 is changed from the H level to the L level is before the start of the AD conversion period, the buffer circuit is unlikely to receive the potential fluctuation of the GND potential supply line 103 due to the accumulation operation of the photodiode 104 in the AD conversion period. can do.

  In this embodiment, a buffer circuit having MOS transistors M1 and M2 is shown as an example of an amplifier circuit. As another form of the amplifier circuit, for example, a differential amplifier in which the signal of the photodiode 104 is given to the inverting node and the reference potential is given to the non-inverting node may be used. Any structure may be used as long as this reference potential is supplied by the voltage held by the capacitor 122 and the potential of the GND potential supply line 103. In other words, the imaging device of this embodiment may be configured so that the amplifier circuit is driven by the voltage held by the capacitor 122 and the potential of the GND potential supply line 103.

  In the present embodiment, the mode in which the bias line 202 and the third bias line 203, which are the second bias lines, are separately provided has been described, but a mode in which a common bias line is used may be employed. In addition, a common potential may be supplied to the bias line 202 and the third bias line 203.

(Example 3)
With reference to the drawings, the imaging apparatus of the present embodiment will be described focusing on differences from the first embodiment. The imaging apparatus of the present embodiment is different from the first embodiment in the configuration of the AD conversion unit 107.

  FIG. 3B is a schematic diagram illustrating an example of the configuration of the AD conversion unit 107 included in the pixel 101 of this embodiment.

  The comparator 140 of the AD conversion unit 107 of the present embodiment includes MOS transistors M7 and M8 that are gain adjustment transistors for adjusting the gain of the comparator 140.

  A GND potential supply line 103 is electrically connected to the back gates of the MOS transistors M7 and M8 of this embodiment. The control nodes of the MOS transistors M7 and M8 are electrically connected to one node of the switch 123 and one node of the capacitive element 124, respectively.

  The other node of the switch 123 is electrically connected to the fourth bias line 204. The other node of the capacitor 124 is electrically connected to the GND potential supply line 103. The switch 123 becomes conductive when a signal φS3 output from a timing generator (not shown) is set to H level, and becomes non-conductive when set to L level. The capacitive element 124 is the third capacitive element of this embodiment. The switch 123 is the third switch of this embodiment.

  The operation of the imaging apparatus illustrated in FIG. 3B can be the same as that in FIG. The signal φS3 can be operated in the same manner as the signal φS1.

  When the control nodes of the MOS transistors M7 and M8 are always connected to the fourth bias line 204 and the potential of the GND potential supply line 103 changes and the potentials of the back gates of the MOS transistors M7 and M8 change, the following problem occurs. . If the potentials of the control nodes of the MOS transistors M7 and M8 are constant, the potential difference between the control node and the back gate of each of the MOS transistors M7 and M8 varies due to the variation of the back gate potential of the MOS transistors M7 and M8. End up. As a result, the operating points of the MOS transistors M7 and M8 change. Therefore, the accuracy of the comparison operation of the comparator 140 is reduced.

  In the present embodiment, the control nodes of the MOS transistors M7 and M8 are further electrically connected to the GND potential supply line 103 electrically connected to the photodiode 104 and the MOS transistor M2 via the capacitive element 124. . The MOS transistors M7 and M8 are driven by the voltage held by the capacitor 124 and the potential of the GND potential supply line 103. The back gates of the MOS transistors M7 and M8 are electrically connected to the GND potential supply line 103. The potentials of the control nodes of the MOS transistors M7 and M8 also vary according to the potential variation of the back gates of the MOS transistors M7 and M8 caused by the potential variation of the GND potential supply line 103. Therefore, even if the potential of the GND potential supply line 103 varies, the potential difference between the control nodes of the MOS transistors M7 and M8 and the back gate is unlikely to vary. Therefore, the operating points of the MOS transistors M7 and M8 are unlikely to change. Therefore, the accuracy of the comparison operation of the comparator 140 is not easily lowered.

  In this embodiment, the MOS transistors M7 and M8 are described as NMOS transistors. When the MOS transistors M7 and M8 are PMOS transistors, the node that is electrically connected to the GND potential supply line 103 of the capacitor 124 in FIG. 3B is electrically connected to the power supply voltage supply line 102. You just have to do it.

  Further, if the signals φS1 and φS2 are kept at the H level during the AD conversion period, the capacitive elements 109 and 124 can be operated as filters for reducing noise of the bias line 202 and the GND potential supply line 103. Therefore, for example, in the case of a frame rate that can provide a standby time until the fluctuation of the potential of the GND potential supply line 103 converges, the signals φS1 and φS2 remain at the H level and the capacitors 109 and 124 are filtered. To act as. On the other hand, in the case of a frame rate in which it is difficult to provide a standby time until the fluctuation of the potential of the GND potential supply line 103 converges, as described in this embodiment, the bias lines 202 are connected to the capacitor elements 109 and 124. And a voltage based on a potential difference between the GND potential supply line 103 and the GND potential supply line 103 may be held. That is, after the switch 123 is switched from conduction to non-conduction, the comparator 140 compares the signal output from the photodiode 104 with the reference signal, and the switch 123 is kept conductive, and the comparator 140 has the photodiode 104 connected to the comparator 140. The imaging apparatus may be operated by selecting a mode from a mode group including a mode for comparing a signal to be output and a reference signal.

Example 4
The imaging apparatus of the present embodiment will be described focusing on differences from the first embodiment.

  FIG. 4A shows an example of the configuration of the imaging apparatus of the present embodiment. In this embodiment, pixel cells 130 having a plurality of pixels 101 are provided in a plurality of rows and columns. The vertical control circuit 300 scans for each row of the pixel cells 130. The bias circuit 201 is provided corresponding to the row of the pixel cells 130. The output line 400 shown in FIG. 4A is the product of the bit number N of the signal output from the pixel cell 130 and the column number M of the pixel 101 in the pixel cell 130 for one column of pixel cells 130. N × M are provided.

  FIG. 4B shows one of the pixel cells 130 shown in FIG. A plurality of columns 131 and a plurality of rows of pixels 131 are provided in the pixel cell 130. The plurality of pixels 131 are electrically connected to a common fifth bias line 134. In the fifth bias line 134, one node of the capacitive element 133 is electrically connected to the fifth bias line 134 and one node of the switch 132. The other node of the switch 132 is electrically connected to the bias line 202. Switch 132 becomes conductive when signal φS4 output from a timing generator (not shown) is set to H level, and becomes non-conductive when set to L level. The other node of the capacitor 133 is electrically connected to the GND potential supply line 103.

  FIG. 4C shows the configuration of the pixel 131 of this embodiment. 4C, the components having the same functions as those of the image pickup apparatus described in FIG. 1B are denoted by the same reference numerals as those in FIG. The fifth bias line 134 is electrically connected to the AD conversion unit 107. The signals φRES and φTX shown in FIG. 4C can be the same as the operation shown in FIG. The AD conversion unit 107 of each pixel 131 in the pixel cell 130 of this embodiment is driven by the voltage held by the capacitor 133 and the potential of the GND potential supply line 103.

  The signal φS4 is preferably changed from H level to L level before the signal φRES in the pixel cell 130 becomes H level. This is because the capacitance element 133 holds a voltage based on the potential difference between the bias line 202 and the GND potential supply line 103 in a state where the potential variation of the GND potential supply line 103 is small when the signal φS4 changes from the H level to the L level. Because it can. The image pickup apparatus of this embodiment includes a capacitive element 133 that holds a voltage based on a potential difference between the bias line 202 and the GND potential supply line 103. As a result, the potential of the fifth bias line 134 varies according to the variation in the potential of the GND potential supply line 103 caused by the operation of the photodiode 104. Therefore, the potential difference between the fifth bias line 134 and the GND potential supply line 103 does not easily change. Therefore, the same effects as those of the first embodiment can be obtained with the imaging apparatus of the present embodiment.

  In the imaging apparatus of this embodiment, a single capacitive element that holds a voltage based on the potential difference between the bias line and the GND potential supply line is provided for a plurality of pixels 131. As a result, the number of capacitative elements that hold a voltage based on the potential difference between the bias line and the GND potential supply line and the number of switches that control the signal holding operation of the capacitative element can be reduced as compared with the imaging apparatus of the first embodiment. Therefore, the circuit scale can be reduced.

  Further, the pixel 131 of this embodiment may have the buffer circuit and the capacitor 122 described in Embodiment 2. Further, when the AD conversion unit 107 according to the present embodiment includes the comparator 140 as described in the third embodiment and includes the MOS transistors M7 and M8 that adjust the gain, the capacitance element 124 may be provided. good.

(Example 5)
FIG. 5 illustrates an imaging system including the imaging apparatuses according to the first to fourth embodiments.

  In FIG. 5, the imaging system includes a barrier 151 for protecting the lens, a lens 152 that forms an optical image of a subject on the imaging device 154, and a diaphragm 153 for changing the amount of light passing through the lens 152. Further, the imaging system includes an output signal processing unit 155 that processes a signal output from the imaging device 154. A signal output from the imaging device 154 is an imaging signal for generating an image of a subject. The output signal processing unit 155 generates an image by performing various corrections and compressions on the imaging signal output from the imaging device 154 as necessary. A lens 152 and a diaphragm 153 are optical systems that collect light on the imaging device 154.

  The imaging system illustrated in FIG. 5 further includes a buffer memory unit 156 for temporarily storing image data, and an external interface unit 157 for communicating with an external computer or the like. The imaging system further includes a removable recording medium 159 such as a semiconductor memory for recording or reading imaging data, and a recording medium control interface unit 158 for recording or reading to the recording medium 159. Further, the imaging system includes an overall control / arithmetic unit 1510 that controls various calculations and the entire digital still camera.

  The imaging device 154 included in the imaging system illustrated in FIG. 5 can have the form described in the first to fourth embodiments. Thereby, also in the imaging device 154 of the imaging system of FIG. 5, the effects described in the first to fourth embodiments can be obtained.

101 pixel 102 power supply voltage supply line 103 GND potential supply line 104 photodiode 107 AD converter

Claims (11)

A pixel having a conversion unit that generates charges based on incident rays, and an AD conversion unit that converts a signal based on the charges generated by the conversion unit into a digital signal;
A first bias line electrically connected to the conversion unit;
A second bias line to which a potential different from the first bias line is applied;
A capacitive element including one node electrically connected to the AD converter and the other node electrically connected to the first bias line;
A switch that switches between conduction and non-conduction between the one node and the second bias line ,
The AD conversion unit includes a comparator and a current supply transistor that operates as a current source that drives the comparator,
The image pickup apparatus , wherein the one node of the capacitor is electrically connected to a gate of the current supply transistor . The imaging device has a plurality of the pixels,
The imaging apparatus according to claim 1 , wherein the one node of the capacitive element is electrically connected to the AD conversion unit of each of the plurality of pixels. The comparator includes a first input transistor to which a signal output from the conversion unit is provided, and a second input transistor to which a reference signal is provided.
The imaging apparatus according to claim 1, wherein the current supply transistor supplies current to the first input transistor and the second input transistor. The comparator outputs a comparison result signal indicating a result of comparing a potential applied to the first input transistor and a potential applied to the second input transistor;
One main node of the current supply transistor is electrically connected to the first bias line;
The imaging apparatus according to claim 3 , wherein the other main node of the current supply transistor is electrically connected to the first input transistor and the second input transistor. The comparator has a gain adjustment transistor for adjusting the gain of the comparator;
The imaging device includes a third capacitor element, a fourth bias line, a third switch,
Have
One node of the third capacitive element is electrically connected to the gain adjustment transistor,
The other node of the third capacitive element is electrically connected to the first bias line;
The imaging apparatus according to claim 4, wherein the third switch is a switch that switches between conduction and non-conduction between the one node of the third capacitor and the fourth bias line. The imaging device
An amplifier circuit provided in an electrical path between the conversion unit and the AD conversion unit, a second capacitance element, a third bias line, and a second switch;
One node of the second capacitive element is electrically connected to the amplifier circuit;
The other node of the second capacitive element is electrically connected to the first bias line;
6. The switch according to claim 1, wherein the second switch is a switch that switches between conduction and non-conduction between the one node of the second capacitive element and the third bias line. 7. Imaging device.   The imaging apparatus according to claim 6, wherein a common potential is applied to the second bias line and the third bias line.   The imaging apparatus according to claim 1, wherein a ground voltage is applied to the first bias line. An imaging device according to any one of claims 1 to 8,
A signal processing unit for processing a signal output from the imaging device;
An imaging system. A plurality of converters for generating charges based on incident rays;
A plurality of AD converters for converting signals based on the charges generated by the plurality of converters into digital signals;
A first bias line electrically connected to each converter of the plurality of converters;
A second bias line to which a potential different from the first bias line is applied;
A capacitive element including one node electrically connected to each AD converter of the plurality of AD converters, and the other node electrically connected to the first bias line;
A switch that switches between conduction and non-conduction between the one node and the second bias line,
Each of the AD conversion units includes a comparator and a current supply transistor that operates as a current source that drives the comparator,
The image pickup apparatus, wherein the one node of the capacitor is electrically connected to a gate of the current supply transistor. The imaging apparatus according to claim 10, wherein the plurality of AD conversion units are arranged in a matrix.

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