JP7213661B2 - IMAGING DEVICE AND CONTROL METHOD THEREOF, PROGRAM, STORAGE MEDIUM - Google Patents

Description

The present invention relates to an imaging device and its control method.

As disclosed in Japanese Unexamined Patent Application Publication No. 2002-100000, an imaging apparatus using a pixel-parallel AD conversion method in which an AD conversion unit is provided for each pixel has been proposed.

WO2016/136448

When AD-converting a signal read out from one pixel continuously two or more times by a pixel parallel AD conversion method as described in Patent Document 1, the timing of AD-converting the signal read out from the photoelectric conversion unit for the first time. As a result, the time difference (hereinafter referred to as AD conversion interval) between the AD conversion timings of the signals read from the second time onwards becomes longer. In particular, in a configuration in which one memory is provided for one pixel, it is necessary to read AD conversion results from all rows through data transfer lines and empty the memories of all rows. determined by the signal readout time in minutes.

The present invention has been made in view of the above problems, and its object is to perform AD conversion of a signal read out from one pixel continuously two or more times by a pixel parallel AD conversion method. An object of the present invention is to provide an imaging device capable of shortening the interval between AD conversions.

An imaging device according to the present invention is an imaging device comprising a plurality of unit units arranged two-dimensionally, wherein each of the plurality of unit units includes a pixel having at least one photoelectric conversion unit, and one of the above-mentioned an AD conversion unit provided corresponding to each pixel to AD-convert a signal of the pixel; and a first memory provided corresponding to each pixel and storing output data from the AD conversion unit. , at least one second memory that does not correspond to each of the pixels , and output data from the AD converter in the unit cell including the AD converter and a selection unit that switches between a state of outputting to the first memory and a state of outputting to the second memory .

According to the present invention, when AD conversion is performed on a signal read out from one pixel two or more times in succession in the pixel-parallel AD method, it is possible to shorten the interval between AD conversions performed a plurality of times in succession. Become.

1 is a block diagram showing the configuration of an imaging device according to a first embodiment of the present invention; FIG. FIG. 2 is a block diagram showing the configuration of an imaging device according to the first embodiment; FIG. FIG. 2 is a block diagram showing the configuration of a unit of an imaging element; FIG. 2 is a block diagram showing the configuration of a unit of an imaging element; FIG. 4 is a diagram showing a correspondence relationship between a pupil region of a photographing lens and a photoelectric conversion unit; FIG. 2 is a circuit diagram of pixels of the image pickup device according to the first embodiment; 4 is a timing chart showing the operation of the image sensor in the first embodiment; FIG. 3 is a diagram showing the configuration of a unit cell of an image sensor and an AD conversion section according to the first embodiment; FIG. 10 is a block diagram showing the configuration of a unit of an imaging device according to the second embodiment; 9 is a timing chart showing the operation of the image pickup device according to the second embodiment; FIG. 5 is a diagram showing the configuration of a unit cell and an AD conversion section of an imaging device according to a second embodiment; FIG. 11 is a block diagram showing a configuration for switching between a reference signal and a reference signal based on luminance determination according to the third embodiment; FIG. 11 is a diagram showing the configuration of a unit cell of an image sensor and an AD conversion section according to a third embodiment; FIG. 11 is a diagram showing the configuration of a unit cell of an image sensor and an AD conversion section according to a third embodiment; FIG. 11 is a diagram showing the correspondence relationship between the pupil region and aperture of the photographing lens according to the fourth embodiment; FIG. 11 is a circuit diagram of pixels of an image sensor according to a fourth embodiment; 14 is a timing chart showing the operation of the imaging element in the fourth embodiment; FIG. 11 is a timing chart showing the operation of the image sensor in the fifth embodiment; FIG. The figure which shows the structure of the unit cell of an image sensor in 5th Embodiment, and an AD-conversion part. FIG. 12 is a top view of pixels of an image pickup device according to the sixth embodiment; FIG. 11 is a diagram showing the arrangement of pixels of an image pickup device according to the sixth embodiment; FIG. 11 is a circuit diagram of pixels of an image sensor according to a sixth embodiment; FIG. 12 is a block diagram showing the configuration of a unit of an imaging device according to the sixth embodiment; FIG. 11 is a diagram showing the configuration of a unit cell of an image sensor and an AD conversion section according to a sixth embodiment; FIG. 10 is a timing chart showing the operation of the image sensor in the sixth embodiment; FIG. FIG. 10 is a timing chart showing the operation of the image sensor in the sixth embodiment; FIG.

BEST MODE FOR CARRYING OUT THE INVENTION Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings.

<First Embodiment>
FIG. 1 is a block diagram showing the configuration of an imaging apparatus according to the first embodiment of the invention.

FIG. 1 is a diagram showing the configuration of a digital camera 1000 that is the first embodiment of the imaging apparatus of the present invention. In FIG. 1, light from a subject passes through an imaging optical system 1120 and forms an image of the subject on the imaging device 100 . The imaging optical system 1120 includes, in order from the subject side, a fixed first lens group 1101, a zoom lens 1102 that moves in the optical axis direction to change magnification, a diaphragm 1103 that adjusts the amount of light, and a fixed second lens group. A group lens 1104 is arranged.

A focus lens 1105 having both a function of correcting image plane fluctuations accompanying zooming and a focus function is also arranged. Although each lens group is shown to be composed of one lens in FIG. 1, it may actually be composed of one lens, or may be composed of a plurality of lenses. may have been

The imaging element 100 is a photoelectric conversion element configured by a CMOS sensor, and converts an analog signal obtained by photoelectrically converting an object image into a digital signal and outputs the digital signal. A camera signal processing circuit 1108 performs various image processing on the output signal from the image sensor 100 to generate an image signal.

An AF (autofocus) signal processing circuit 1081 is provided in the camera signal processing circuit 1108 . The AF signal processing circuit 1081 uses the focus detection signal output from the image sensor 100 to generate a focus signal representing the focus state of the imaging optical system 1120 .

A display device 1109 displays the image signal from the camera signal processing circuit 1108, and a recording device 1110 records the image signal from the camera signal processing circuit 1108 on a recording medium such as a magnetic tape, an optical disk, or a semiconductor memory.

A camera microcomputer (hereinafter referred to as a camera microcomputer) 1111 controls a focus lens driving section 1113 (to be described later) based on a focus signal output from a camera signal processing circuit 1108 to move a focus lens 1105 in the optical axis direction. This operation is mainly performed by the AF control section 1121 provided in the camera microcomputer 1111 .

Also, the AF control unit 1121 actually performs focus control according to the determined target position of the focus lens 1105 . Furthermore, during zooming, zoom tracking control is performed to move the focus lens 1105 based on zoom tracking data stored in advance. This prevents image plane fluctuation (bokeh) due to zooming. Note that the camera microcomputer 1111 also controls the operation of the imaging device 100 .

A zoom lens driving unit 1112 moves the zoom lens 1102 to perform a zooming operation, and a focus lens driving unit 1113 moves the focus lens 1105 to perform focus adjustment. The zoom lens driving section 1112 and the focus lens driving section 1113 are provided with drive sources such as stepping motors, DC motors, vibration motors, and voice coil motors.

FIG. 2 is a diagram showing the configuration of the imaging element 100 used in the imaging apparatus of this embodiment. In FIG. 2, unit units 102 each having at least one pixel are arranged two-dimensionally on the imaging surface of the imaging element 100 . FIG. 2 shows a state in which the unit units 102 are arranged in three units vertically and three units horizontally for ease of explanation. Tens of millions of unit units 102 are arranged.

A reference signal generation circuit 114 is connected to each unit 102 via a reference signal line 116 . The reference signal generation circuit 114 uses a reference signal line 116 to supply each unit 102 with a reference signal used when performing AD conversion within the unit 102 .

Furthermore, a counter 118 is connected to each unit 102 via a counter signal line 120 . The counter 118 uses the counter signal line 120 to supply each unit 102 with a counter signal used when performing AD conversion within the unit 102 .

Each unit 102 is driven by a pixel driving circuit 110 . The pixel drive circuit 110 sends control signals for controlling the unit units 102 (to be described later) to the respective unit units 102 via the pixel drive signal lines 108 .

A digital signal (output data) AD-converted by the unit 102 is sent to the signal processing circuit 106 via the data transfer line 104 . The signal processing circuit 106 transfers the digital signal to the output unit 112 after rearranging the digital signal obtained from each unit 102 and performing addition/subtraction.

A timing generator (TG) 122 controls the operation timing of each unit. Through unillustrated wiring, the timing generator 122 connects the reference signal generation circuit 114, the counter 118, the pixel drive circuit 110, the signal processing circuit 106, the comparators 21a, 21b, 21c included in the unit 102, and the selector 22, which will be described later. Control.

FIG. 3 is a diagram showing the configuration of unit 102 shown in FIG. In FIG. 3, the unit 102 has three pixels 20a, 20b, 20c. A pixel outputs an analog signal according to incident light to the pixel, as will be described later. The unit 102 includes comparators 21a, 21b, and 21c corresponding to the pixels 20a, 20b, and 20c, respectively.

Further, the unitary unit 102 includes first memories 23a, 23b, 23c and 23d respectively corresponding to the comparators 21a, 21b and 21c. A combination of the pixel 20a, the comparator 21a, and the first memory 23a is called a unit cell. In FIG. 3, the dashed-dotted lines indicate the elements that make up the unit cell.

Although the counter 118 is provided in common for all pixels in FIG. 2, it may be provided for each pixel. When the counter 118 is provided for each pixel, a combination of the pixel 20a, the comparator 21a, the first memory 23a, and the counter provided for each pixel is called a unit cell.

In this embodiment, since AD conversion is performed by a method described later, a memory is essential for AD conversion. Therefore, the combination of the comparator 21a and the first memory 23a is called an AD converter. In FIG. 3, dashed lines indicate the elements constituting the AD converter. Similarly, a combination of the pixel 20b, the comparator 21b, and the first memory 23b is called a unit cell, and the comparator 21b and the first memory 23b constitute an AD converter. Similarly, a combination of the pixel 20c, the comparator 21c, and the first memory 23c is called a unit cell, and the comparator 21c and the first memory 23c constitute an AD converter.

The unit 102 also includes a second memory 23d in addition to the first memory provided for each unit cell (within the unit cell). In FIG. 3, one second memory 23d is arranged for three unit cells. The selection unit 22 is provided to perform switching so as to hold the result of AD conversion performed by a method described later in one of the memories.

In the configuration of FIG. 3, the selector 22 switches between the first memory and the second memory connected to each comparator. As a result, AD conversion is performed using the memory after switching, and the AD conversion result is held by the memory after switching.

Further, as will be described later, in the configuration of FIG. 3, switching the first memory or the second memory connected to the comparator by the selector 22 corresponds to switching the elements constituting the AD converter. . At this time, the elements constituting the unit cell are not switched.

Next, AD conversion in the unit 102 shown in FIG. 3 will be described. Here, a unit cell composed of a pixel 20a, a comparator 21a, and a first memory 23a will be used for explanation. The comparator 21 a compares the analog signal from the pixel 20 a with the reference signal supplied from the reference signal line 116 . A ramp signal is used as the reference signal, and the magnitude relationship determined by the comparator 21a is inverted at a certain timing.

A counter signal is supplied from the counter signal line 120 to the memory 23a, and the counter signal at the timing when the magnitude relationship determined by the comparator 21a is inverted is recorded in the memory 23a. Thereby, the analog signal output from the pixel 20a is converted into a digital value.

Although one counter signal line 120 is shown in FIG. 3, 14 counter signal lines 120 are connected to each memory, for example, when AD conversion is to be performed with 14 bits. The digital value recorded in the memory is transferred to the signal processing circuit 106 using the data transfer line 104 and output from the output section 112 .

The arrangement of the selection unit 22 and the second memory 23d is not limited to the arrangement shown in FIG. Any arrangement may be used as long as the signal continuously obtained from one or more pixels can be held in the unit. As an example, FIG. 4 shows an arrangement of the selection unit 22 and the second memory 23d that is different from that shown in FIG.

In the arrangement shown in FIG. 3, a selector 22 is provided between the comparator and the first and second memories. Therefore, switching the connection between the comparator, the first memory, and the second memory by the selection unit 22 corresponds to switching the elements (memories) constituting the AD conversion unit.

On the other hand, in the arrangement shown in FIG. 4, the selector 22 is provided between the first memory and the second memory. In the arrangement of FIG. 4, even if the selection unit 22 switches the connection, the second memory 23d does not become an element (memory) constituting the AD conversion unit. The second memory 23d is used to temporarily hold the result of AD conversion using the first memory.

Thus, the arrangement of the selection unit 22 and the second memory is different between FIG. 3 and FIG. 4, but either arrangement can hold a signal continuously obtained from one or more pixels. Although the following description is based on the arrangement shown in FIG. 3, the arrangement shown in FIG. 4 may also be used.

In the arrangement shown in FIG. 4, the time for transferring data so that the result of AD conversion using the first memory is held in the second memory can be performed simultaneously for all unit units. It is sufficiently short compared to the time required to use and transfer to the signal processing circuit 106 . In addition, since AD conversion is performed using the same memory, there is also the advantage that the influence of variations in the characteristics of the memory and the characteristics of the counter signal line 120 that supplies the counter signal to the memory can be eliminated.

Next, the configuration of the pixels 20a, 20b, and 20c included in the unit shown in FIG. 3 and the driving method thereof will be described. In the present embodiment, when each pixel has two photoelectric conversion units, a method of obtaining imaging signals from the pixels 20a, 20b, and 20c and obtaining focus detection signals only from the pixel 20a (part of the pixels) is described. explain.

In the present embodiment, by storing the signal from one photoelectric conversion unit of the pixel 20a in the second memory 23d, the timing of AD conversion of the focus detection signal of the pixel 20a and the timing of AD conversion of the imaging signal of the pixel 20a are adjusted. shorten the interval between As a result, focus detection can be performed with sufficient accuracy even for a moving object.

Also, the pixels that acquire the focus detection signal can be switched between the pixels 20b and 20c. As a result, in the case of a red subject, optimum focus detection processing can be performed according to the subject, such as performing focus detection using the R pixels that detect red light.

Furthermore, in order to select and switch between several tens of rows as the focus detection area, the three pixels shown in FIG. 3 may be increased to several tens of pixels. In that case, the second memory 23d may be provided for the number of rows selected as the focus detection area for several tens of pixels.

A configuration of a pixel having two photoelectric conversion units in this embodiment will be described. Although three pixels are shown in FIG. 3, the configuration of each pixel is the same.

FIG. 5 shows the correspondence relationship between the pupil area of the photographing lens and the photoelectric conversion unit. FIG. 5 shows two photoelectric conversion units 201a and 201b, pupil regions 253a and 253b, a microlens 251, and a color filter 252 provided in one pixel. Light that has passed through the pupil region 253a is incident on the photoelectric conversion unit 201a. Light passing through the pupil region 253b is incident on the photoelectric conversion unit 201b.

Accordingly, focus detection can be performed from the signals obtained from the photoelectric conversion units 201a and 201b. Further, by mixing signals obtained from the photoelectric conversion units 201a and 201b, an imaging signal can be generated.

FIG. 6 is a diagram showing the circuit configuration of a pixel. The photoelectric conversion units 201a and 201b generate charges based on incident light. The transfer transistor 202 a is provided in an electrical path between the photoelectric conversion section 201 a and the floating diffusion section (hereinafter referred to as the FD section) 203 , and the transfer transistor 202 b is provided in an electrical path between the photoelectric conversion section 201 b and the FD section 203 .

The transfer transistors 202 a and 202 b control on/off of charge transfer from the photoelectric conversion units 201 a and 201 b to the FD unit 203 . The reset transistor 204 has a source terminal electrically connected to the FD section 203 and a drain terminal supplied with a power supply voltage VDD. The reset transistor 204 controls on/off of resetting of the potential of the FD section 203 .

The amplification transistor 205 has a gate terminal electrically connected to the FD section 203, a drain terminal supplied with a power supply voltage VDD, and a source terminal electrically connected to a drain terminal of the selection transistor 206. FIG. The amplification transistor 205 performs source follower operation with the current supplied from the current supply unit 207 and the power supply voltage VDD. The amplification transistor 205 outputs an analog signal based on the potential of the FD section 203 .

The source terminal of the selection transistor 206 is electrically connected to the current supply section 207 and the comparator. The selection transistor 206 switches conduction/non-conduction between the amplification transistor 205 and the comparator. A pixel driving signal is sent from the pixel driving circuit 110 to the gate terminals of the transfer transistors 202a and 202b, the reset transistor 204, and the selection transistor 206 via the pixel driving signal line 108, and controlled.

Next, a method for driving the imaging device 100 configured as described above will be described. FIG. 7 is a timing chart showing driving timings of the imaging element.

Of the two photoelectric conversion units, the signal for focus detection obtained from the photoelectric conversion unit 201a is signal A, the signal for focus detection obtained from photoelectric conversion unit 201b is signal B, and the signals A and B are mixed. The imaging signal generated by the above is expressed as an A+B signal. In this embodiment, the imaging signal is obtained from the three pixels 21a, 21b, and 21c, and the focus detection signal is obtained only from the pixel 21a.

Here, AD conversion and reading are performed in different periods such that AD conversion is performed in periods 301 and 302 and reading from the memory is performed in periods 303 to 306 . However, the AD conversion period and the readout period from the memory may overlap.

For example, after the AD conversion of the A signal of the pixel 20a in the period 301, that is, in the period 302, the reading of the A signal from the second memory 23d shown to be performed in the period 303 may be started. At this time, in period 302, AD conversion is performed in the first memories 23a, 23b, and 23c, and reading from the memory is simultaneously performed in the second memory 23d.

In the period 301 shown in FIG. 7, AD conversion of the A signal from the photoelectric conversion unit 201a of the pixel 20a is performed. At this time, the transfer transistor 202a is turned on, the charge accumulated in the photoelectric conversion unit 201a is transferred to the FD unit 203, and the A signal (analog signal) is output from the amplification transistor 205 to the comparator 21a. The output destination of the comparator 21a is set by the selector 22 to the second memory 23d. Thereby, the A signal (digital signal) of the pixel 20a is held in the second memory 23d.

FIG. 8 shows the connection relationship between the unit cells and the AD converters in period 301 . In FIG. 8, the dashed-dotted lines indicate the elements forming the unit cell, and the dashed lines indicate the elements forming the AD converter. As shown in FIG. 8, in a period 301, the selector 22 sets the comparator 21a and the second memory 23d to be connected, and the comparator 21a and the second memory 23d constitute an AD converter.

In a period 302 shown in FIG. 7, A+B signals of three pixels 20a, 20b, and 20c are AD-converted. In the pixel 20 a , the transfer transistor 202 a is turned on in the period 301 , and the transfer transistor 202 b is also turned on in the period 302 . As a result, charges generated by the photoelectric conversion units 201a and 201b are transferred to the FD unit 203, and an A+B signal (analog signal) is output from the amplification transistor 205 to the comparator 21a.

The output destination of the comparator 21a is set by the selector 22 to the first memory 23a. At this time, the connection relationship between the respective AD converters is the configuration surrounded by the dashed lines in FIG. Thereby, the A+B signal (digital signal) of the pixel 20a is held in the first memory 23a.

Thus, by holding the results of the A signal and the A+B signal obtained from the pixel 20a in the second memory 23d and the first memory 23a, AD conversion can be continuously performed in the pixel 20a. If the A signal and the A+B signal are AD-converted using the same memory, the signal A held in the memory using the signal processing circuit 106 is converted between the AD conversion of the A signal and the AD conversion of the A+B signal. It takes time to read the signal. This time difference leads to deterioration of the focus detection signal.

7, in the pixels 20b and 20c, the transfer transistors 202a and 202b are turned on to transfer charges generated by the photoelectric conversion units 201a and 201b to the FD unit 203. FIG. As a result, A+B signals (analog signals) of pixels 20b and 20c are output to comparators 21b and 21c, respectively.

The output destinations of the comparators 21b and 21c are set by the selector 22 to the first memories 23b and 23c, respectively. As a result, the A+B signals (digital signals) obtained from the pixels 20b and 20c are held in the first memories 23b and 23c, respectively.

In the period 303 shown in FIG. 7, the signal processing circuit 106 reads the A signal of the pixel 20a from the second memory 23d. In FIG. 7, readout of the focus detection signal is preferentially performed in order to start the focus detection calculation first. That is, the A signal of the pixel 20a shown in the period 303 and the A+B signal of the pixel 20a shown in the period 304 are read with priority. Although one data transfer line 104 is shown in FIG. 3, a plurality of lines may be provided in parallel in order to increase the data read speed.

In periods 304, 305 and 306 shown in FIG. 7, the signal processing circuit 106 reads A+B signals of the pixels 20a, 20b and 20c from the first memories 23a, 23b and 23c, respectively.

By the above operation, the time difference between the AD conversion timing of the A signal and the timing of AD conversion of the A+B signal can be shortened, deterioration of the focus detection signal can be prevented, and appropriate focus detection can be performed even for a moving object. can be done.

In this embodiment, the focus detection signal is obtained from the pixel 20a, but the focus detection signal may be obtained from the pixel 20b and the pixel 20c and stored in the second memory 23d. When acquiring the focus detection signal from the pixel 20b, the selector 22 sets the comparator 21b to be connected to the second memory 23d in the period 301 shown in FIG. Thereby, the A signal (digital signal) of the pixel 20b is held in the second memory 23d.

Similarly, when acquiring the focus detection signal from the pixel 20c, the selector 22 sets the comparator 21c to be connected to the second memory 23d in the period 301 shown in FIG. Thereby, the A signal (digital signal) of the pixel 20c is held in the second memory 23d.

Further, in the present embodiment, the case where the imaging signals are obtained from the pixels 20a, 20b, and 20c and the focus detection signal is obtained from the pixel 20a has been described. Live view display and focus detection can also be implemented. For example, among the pixels 20a, 20b, and 20c shown in FIG. 3, only the pixel 20a is selected, and control is performed so that both the imaging signal and the focus detection signal are not read out from the pixels 20b and 20c.

As a result, it is possible to reduce not only the amount of focus detection signals but also the amount of readout of imaging signals, enabling high-speed operation. At this time, the signal reading and AD conversion of the pixels 20b and 20c shown in period 302 in FIG. 7 need not be performed. Also, the data transfer shown in periods 305 and 306 in FIG. 7 need not be performed.

Note that when giving priority to low-delay live view display over high-speed focus detection, the readout of the A+B signal shown in period 304 in FIG. Control to go first.

<Second embodiment>
A driving method according to the second embodiment of the present invention will be described below. The pixel configuration shown in FIGS. 5 and 6 is also used in the second embodiment. In this embodiment, when there is a first mode in which focus detection signals and imaging signals are acquired in 12 bits and a second mode in which only imaging signals are acquired in 16 bits, AD conversion result A drive method for switching the memory holding the will be described.

FIG. 9 is a diagram showing the configuration of the unit 102 in the second embodiment. For convenience of explanation, FIG. 9 shows the first memory 23a shown in FIG. 3 divided into three blocks of a first memory 23a1, a first memory 23a2, and a first memory 23a3.

In FIG. 9, each of the first memories 23a1, 23a2, and 23a3 holds a 4-bit digital value. This corresponds to holding a 12-bit digital value in the first memory 23a in FIG.

Similarly, the first memories 23b, 23c and the second memory 23d shown in FIG. 3 can also hold 12 bits. Also, in FIG. 9, the dashed-dotted lines indicate the elements forming the unit cell, and the dashed lines indicate the elements forming the AD converter.

First, the driving method of the first mode for acquiring the focus detection signal and the imaging signal with 12 bits will be described. A driving method in the first mode is the same as the driving method described in the first embodiment. That is, as shown in FIG. 7, the A signal of the pixel 20a is AD-converted using the comparator 21a, and the result is held in the second memory 23d.

In FIG. 9, a 12-bit A signal is held by holding 4 bits in each of the second memories 23d1, 23d2, and 23d3. After performing AD conversion of the A signal of the pixel 20a, AD conversion of the A+B signals of the pixels 20a, 20b, and 20c is performed, and the respective results are held in the first memories 23a, 23b, and 23c. In FIG. 9, a 12-bit A+B signal is held in each first memory divided into three blocks of 4 bits each.

Next, a description will be given of a driving method in the second mode in which only a 16-bit imaging signal is acquired. The second mode is a mode in which 16-bit imaging signals, that is, A+B signals are obtained from each of the pixels 20a, 20b, and 20c. FIG. 10 is a timing chart showing operation timings in the second mode.

In the second mode, AD conversion of pixels 20a, 20b, and 20c is performed in period 401 of FIG. At this time, in order to hold the AD conversion result of the 16-bit A+B signal, the selector 22 sets the first memories 23a1, 23a2, 23a3 and the second memory 23d1 to be connected to the comparator 21a. . As a result, the number of bits that can be held in the AD conversion section composed of the comparator 21a and the first memories 23a1, 23a2, and 23a3 is limited to 12 bits, but by adding the second memory 23d1, it can hold up to 16 bits. can do.

FIG. 11 shows a connection relationship between a unit cell including the pixel 20a and an AD converter used for AD conversion of the pixel 20a in the period 401. FIG. In FIG. 11 , the dashed-dotted lines indicate the elements forming the unit cell, and the dashed lines indicate the elements forming the AD converter.

As shown in FIG. 11, in a period 401, the selector 22 sets the first memories 23a1, 23a2, 23a3 and the second memory 23d1 to be connected to the comparator 21a. It is configured. A unit cell including the pixel 20a is composed of the pixel 20a, the comparator 21a, and the first memories 23a1, 23a2 and 23a3.
Similarly, the selector 22 connects the first memories 23b1, 23b2, 23b3, and the second memory 23d2 to the comparator 21b, and connects the first memories 23c1, 23c2, 23c3, and 23c3 to the comparator 21c. It is set to connect the second memory 23d3. As a result, the pixels 20b and 20c can also hold the 16-bit A+B signal at the same time as the pixel 20a.

In periods 402, 403, and 404 shown in FIG. 10, the signal processing circuit 106 reads A+B signals (digital values) from the first memory and the second memory for each pixel.

Incidentally, if 12 parallel data transfer lines are provided according to the number of bits that can be held in the first memory and the second memory, 16-bit parallel reading cannot be performed. Therefore, 12-bit parallel reading may be performed for each memory. In that case, the data is rearranged at the output destination of the signal processing circuit 106 or the output unit 112 to generate a 16-bit A+B signal obtained from each pixel.

In addition, 12 parallel data transfer lines are provided in the first memory and the second memory, and another 4 parallel data transfer lines are provided in the second memory to obtain data for each pixel when driving in the second mode. 16-bit parallel reading may be performed collectively on the A+B signals obtained.

<Third Embodiment>
A driving method according to the third embodiment of the present invention will be described below. In the third embodiment, a case will be described where the luminance of an output value from a pixel is determined and AD conversion is performed by changing the slope of a ramp signal given as a reference signal.

First, the method of determining the luminance and switching the slope of the ramp signal will be described. FIG. 12 is a diagram showing a reference signal used in the third embodiment and a configuration for switching the reference signal based on luminance determination.

FIG. 12(a) shows the first reference signal when the slope of the ramp signal is not switched. FIG. 12(b) shows a second reference signal H including a pulse signal used for luminance determination and a ramp signal with a slope different from that of FIG. 12(a). FIG. 12(c) shows a second reference signal L including a ramp signal having the same slope as that of FIG. 12(a) but having a low peak and a short AD conversion time. FIG. 12D shows a configuration for switching reference signals based on luminance determination.

As shown in FIG. 12D, two signal lines 116H and 116L are provided as the reference signal line 116 in addition to the pixel 20a and the comparator 21a shown in FIG. A luminance determination unit 25 is provided. Pixels 20b and 20c shown in FIG. 3 also have the same configuration.

This embodiment has a third mode in which AD conversion is performed without luminance determination, and a fourth mode in which luminance determination is performed and the reference signal is switched.

A method of setting the fourth mode for luminance determination as the normal mode and switching to the third mode when discrete gradation is conspicuous in pixels determined to have high luminance will be described below. Here, whether or not to switch from the fourth mode to the third mode, that is, whether or not the discretization of the gradation is conspicuous, is whether or not the number of high-brightness pixels in a certain area in the previous frame is equal to or greater than a threshold. or not. Also, a switching switch or the like may be provided so that the user can arbitrarily switch.

A driving method in the third embodiment will be described below with reference to FIGS. 12(d), 13 and 14. FIG.

13 and 14 show the connection relationship between the unit cells and the AD converters in the third embodiment. In FIGS. 13 and 14, the dashed-dotted lines indicate the elements forming the unit cell, and the dashed lines indicate the elements forming the AD converter.

In the present embodiment, since luminance is determined for each pixel, the reference signal switching unit 24 and the luminance determination unit 25 are provided for the reference signal lines 116H and 116L and each comparator as shown in FIG. 12(d). Although provided, it is omitted in FIGS.

13 and 14, for convenience of explanation, the second memory 23d shown in FIG. 3 is divided into three blocks of a second memory 23d1, a second memory 23d2, and a second memory 23d3. In switching between the third mode and the fourth mode, a 14-bit memory is required in the fourth mode and a 16-bit memory is required in the third mode in order to hold the AD conversion result. do.

Therefore, 14-bit memories are prepared for the first memories 23a, 23b, and 23c, and 3 blocks of 2-bit each are prepared for the second memories 23d1, 23d2, and 23d3, for a total of 6-bit memories. Note that a memory with a number of bits greater than 6 bits may be prepared as the second memory 23d so that the first embodiment and the second embodiment can be implemented using the same configuration.

Focusing on the unit cell including the pixel 20a, detailed driving will be described below using FIG.

First, in the third mode, the input of the reference signal switching section 24 is set to the reference signal line 116H. The first reference signal generated by the reference signal generation circuit 114 is supplied to the reference signal switching section 24 using the reference signal line 116H. Although the reference signal line 116H is used here, the first reference signal may be supplied using the reference signal line 116L. Further, the state of the luminance determination unit 25 is fixed to Hi when the reference signal line 116H is used, and is fixed to Low when the reference signal line 116L is used.

The reference signal switching unit 24 inputs the first reference signal to the comparator 21a, and the comparator 21a compares the analog signal (input signal) from the pixel 20a with the first reference signal to convert a 16-bit signal. AD conversion is performed. At this time, since the AD conversion result is 16 bits while the first memory is 14 bits, the selector 22 sets the comparator 21a to be connected to the first memory 23a and the second memory 23d1. That is, the unit cell including the pixel 20a and the AD converter used for AD conversion of the pixel 20a have the configuration shown in FIG.

A counter signal is supplied from the counter signal line 120 to the first memory 23a and the second memory 23d1. Then, the counter signal at the timing when the magnitude relationship between the analog signal from the pixel 20a and the first reference signal is inverted in the comparator 21a is recorded in the first memory 23a and the second memory 23d1. As a result, the analog signal output from the pixel 20a is converted into a 16-bit digital value.

Similarly, by setting the selector 22 to connect the comparator 21b to the first memory 23b and the second memory 23d2, 16-bit AD conversion is performed in the pixel 20b. Further, by setting the selector 22 to connect the comparator 21c to the first memory 23c and the second memory 23d3, 16-bit AD conversion is performed in the pixel 20c.

On the other hand, in the fourth mode, luminance determination is performed in the period from time t1 to time t2 shown in FIG. That is, the input of the reference signal switching unit 24 is set to the reference signal line 116H, and the reference signal generation circuit 114 supplies the reference signal switching unit 24 with a pulse signal whose intensity is ¼ of the peak of the first reference signal. do. The comparator 21a determines whether the pixel output signal has high luminance or low luminance by determining the magnitude relationship between the analog signal and the pulse signal output from the pixel 20a. Then, the brightness determination unit 25 holds the result of brightness determination performed using the comparator 21a in a Hi state or a Low state.

The reference signal switching unit 24 refers to the brightness determination result held in the brightness determination unit 25 and switches the reference signal to be used after time t2 in FIG. That is, when the luminance is high, the input of the reference signal switching unit 24 is set to the reference signal line 116H, and the reference signal generation circuit 114 selects the second reference signal H having a large slope of the ramp signal. 24.

When the luminance is low, the input of the reference signal switching unit 24 is set to the reference signal line 116L, and the reference signal generation circuit 114 selects the second reference signal L having a small slope of the ramp signal. 24. Note that when AD conversion is performed using the second reference signal H, the time required for AD conversion is reduced to 1/4 compared to when an analog signal of the same level is AD converted using the second reference signal L.

Here, a counter signal is supplied from the counter signal line 120 to the first memory 23a. Then, a counter signal is recorded in the first memory 23a at the timing when the analog signal from the pixel 20a and the second reference signal H or the second reference signal L are inverted in magnitude by the comparator 21a. As a result, the analog signal output from the pixel 20a is converted into a 14-bit digital value. For the pixels 20b and 20c as well, brightness determination is performed in the same manner, and then AD conversion is performed. Also, the unit cell and the AD converter have the configuration shown in FIG.

On the low luminance side, the AD conversion accuracy is the same as in the third mode, and the AD conversion results are the same as in the third mode. 4. Therefore, a digital value can be held in a 14-bit memory. The signal processing circuit 106 reads out the AD conversion result from the first memory 23a and outputs it to the output unit 112 as 16 bits by adding 00 to the upper two bits.

Also, on the high luminance side, the AD conversion accuracy is 1/4 that of the third mode, and since a 14-bit digital value shifted two bits lower is output, the digital value on the high luminance side is also 14-bit. Can be held in memory. The signal processing circuit 106 reads out the AD conversion result from the first memory 23a, shifts it by 2 bits to the higher order, and outputs it to the output unit 112 as 16 bits. In either case, the 14-bit to 16-bit conversion may occur prior to output 112 .

It should be noted that, when performing luminance determination, it has been explained that a pulse signal having an intensity of 1/4 of the peak of the ramp signal shown in the first reference signal is used, but the intensity of the pulse signal is limited to this value. not something. In that case, the final output value may be calculated by applying an arbitrary gain in the signal processing circuit 106 without using the bit shift.

<Fourth Embodiment>
A driving method according to the fourth embodiment of the present invention will be described below. In the fourth embodiment, a driving method of performing AD conversion twice in a focus detection pixel among a plurality of pixels included in a unit will be described. In this embodiment, by holding the second AD conversion result obtained from the focus detection pixels in the second memory, the interval between the timing of the first AD conversion in the focus detection pixels and the timing of the second AD conversion is to shorten

As will be described later, the apertures of the focus detection pixels used in the fourth embodiment limit the amount of light that enters the pixels, so the amount of light that the pixels can acquire is smaller than that of the imaging pixels. Therefore, in a low-brightness subject, the focus detection pixels are susceptible to noise. In the fourth embodiment, when focus detection is performed on a low-brightness object, AD conversion is performed twice in the focus detection pixels and an average value is calculated, thereby reducing noise in the focus detection signal. Improve detection accuracy.

In this embodiment, among the pixels shown in FIG. 3, only the pixel 20a is provided with a focus detection pixel, and the pixels 20b and 20c are provided with imaging pixels. FIG. 15 is a diagram showing the correspondence relationship between the pupil region of the photographing lens used in the fourth embodiment and the apertures of the focus detection pixels. Unlike FIG. 5, the aperture 254 determines the shape of the pupil region 253 . For the focus detection pixels, a color filter 252 having a wider transmission band width than the imaging pixels is used in order to improve sensitivity.

Also, in order to detect only the light that has passed through the pupil region 253, a pair of pixels, that is, a pixel that detects light from the right pupil region (not shown in FIG. 15) is separately provided to obtain a focus detection signal. For example, a pair of pixels may be provided in another unit unit adjacent to the unit unit including the pixels having the configuration shown in FIG.

FIG. 16 shows the circuit configuration of a focus detection pixel. The circuit configuration of the focus detection pixels shown in FIG. 16 is the same as that of the imaging pixels. The difference from FIG. 6 is that only one photoelectric conversion unit 201 and only one transfer transistor 202 are provided in FIG. Also, the circuit configuration of the paired pixels is the same as in FIG.

Next, a method for driving the imaging device 100 in this embodiment will be described. FIG. 17 is a timing chart showing drive timings in this embodiment.

In a period 501 shown in FIG. 17, the selector 22 sets the comparator 21a to the first memory 23a, the comparator 21b to the first memory 23b, and the comparator 21c to the first memory 23c, AD conversion is performed respectively. As a result, the first memory 23a holds the focus detection signal obtained from the pixel 20a, and the first memories 23b and 23c hold the imaging signals obtained from the pixels 20b and 20c. At this time, the configuration of each AD converter is the configuration surrounded by the dashed line in FIG.

In a period 502 illustrated in FIG. 17, the selection unit 22 connects the comparator 21a to the second memory 23d, and performs the second AD conversion in the pixel 20a. Thereby, the focus detection signal obtained from the pixel 20a is held in the second memory 23d. At this time, the configuration of each AD converter is the configuration surrounded by the dashed line in FIG.

During periods 503 to 506 shown in FIG. 17, the focus detection signal is preferentially read out sequentially from the memory by the signal processing circuit 106 . A signal processing circuit (not shown) connected to the tip of the signal processing circuit 106 or the output unit 112 calculates an average value of the AD conversion results of the focus detection signals twice, and noise is reduced. Note that the focus detection pixels are not limited to the pixel 20a, and may be provided in the pixels 20b and 20c.

In the above description, noise reduction of the focus detection signal is performed for a low-brightness object, but noise reduction of the imaging signal can also be performed. For example, in a pixel array consisting of R pixels that detect red light, G pixels that detect green light, and B pixels that detect blue light, when a red subject is photographed, the number of B pixels is higher than that of R pixels. signal output drops significantly. By providing unitary units for R, G, and B pixels, noise can be reduced by performing AD conversion and averaging twice for B pixels when a red subject is photographed.

Here, the color of the object is determined based on the image signal of the previous frame by the signal processing circuit 106 or a signal processing circuit (not shown) connected to the output unit 112, and the result is fed back to the selection unit 22. . Similarly, when an object of blue color is photographed, the signal output of the R pixel is small, so noise can be reduced by performing AD conversion and averaging twice on the R pixel.

In this way, among the plurality of pixels included in the unit unit, AD conversion is performed twice on pixels with weak signal outputs, and the average value is calculated, thereby reducing noise and improving focus detection accuracy. Variations in the RGB ratio due to noise can be suppressed.

<Fifth Embodiment>
A driving method according to the fifth embodiment of the present invention will be described below. In the fifth embodiment, a drive method will be described in which one pixel is selected by thinning out of the three pixels included in the unit shown in FIG. 3 and AD conversion is performed twice. Here, not only the imaging signal is AD-converted twice, but also the reset level after the reset operation performed by turning on the reset transistor 204 is AD-converted twice.

Noise reduction is achieved by calculating the average value of the results of the two AD conversions. In the present embodiment, the first memory and the second memory hold the second AD conversion result of the reset level obtained from the thinned pixels and the two AD conversion results of the imaging signal. This shortens the interval between the timing of AD conversion of the reset level and the timing of AD conversion of the imaging signal.

The number of pixels included in the unit unit and the number of thinned pixels are not particularly limited, and one or more pixels may be selected by thinning out a plurality of pixels included in the unit unit. Further, AD conversion may be performed two or more times, and an average value may be calculated to reduce noise. In this embodiment, a case is considered in which an imaging signal is obtained only from the pixel 20a among the pixels shown in FIG. In this case, no signal is acquired from the pixels 20b and 20c.

FIG. 18 is a timing chart showing drive timings in this embodiment. In FIG. 18, the reset level signal is denoted as N signal, and the imaging signal is denoted as S signal. Also, FIG. 19 shows the connection relationship between the unit cell and the AD converter at a certain timing. In FIG. 19, the dashed-dotted lines indicate the elements forming the unit cell, and the dashed lines indicate the elements forming the AD converter.

In a period 601 shown in FIG. 18, the selection unit 22 sets the comparator 21a to be connected to the first memory 23a, thereby transferring the first AD conversion result of the N signal of the pixel 20a to the first memory 23a. Hold. FIG. 19A shows the connection relationship between the unit cells and the AD converters in this case.

In the period 602 shown in FIG. 18, the selection unit 22 sets the comparator 21a to be connected to the first memory 23b, so that the second AD conversion result of the N signal of the pixel 20a is transferred to the first memory 23b. Hold. FIG. 19(b) shows the connection relationship between the unit cell and the AD converter at this time.

In a period 603 illustrated in FIG. 18 , the transfer transistor 202 of the pixel 20 a is turned on, and the charge accumulated in the photoelectric conversion portion 201 is transferred to the FD portion 203 . After the charge transfer, the transfer transistor 202 is turned off and the selection transistor 206 is turned on, thereby making it possible to AD-convert the imaging signal.

By setting the selector 22 to connect the comparator 21a to the first memory 23c, the first AD conversion result of the S signal of the pixel 20a is held in the first memory 23c. FIG. 19(c) shows the connection relationship between the unit cells and the AD converters in this case.

In the period 604 shown in FIG. 18, the selection unit 22 sets the comparator 21a to be connected to the second memory 23d, thereby transferring the second AD conversion result of the S signal of the pixel 20a to the second memory 23d. Hold. FIG. 19(d) shows the connection relationship between the unit cell and the AD converter at this time.

After AD conversion of the reset level and the imaging signal is completed, the signal processing circuit 106 reads out the reset level and the imaging signal from the first memory and the second memory in periods 605 to 608 in FIG. The reset level and the imaging signal thus obtained are averaged by a signal processing circuit (not shown) connected to the end of the signal processing circuit 106 or the output unit 112, respectively. , the noise is reduced.

<Sixth embodiment>
A driving method according to the sixth embodiment of the present invention will be described below. In the sixth embodiment, one pixel has four photoelectric conversion units. Vertical pupil division and horizontal pupil division (pupil division direction) are realized by using pixels with four photoelectric conversion units, and focus detection is possible regardless of whether the subject has vertical lines or horizontal lines. It can be carried out.

Further, in the present embodiment, by forming a unitary unit 102 including a total of 9 pixels arranged 3 pixels in the vertical direction and 3 pixels in the horizontal direction, and switching the connection of the second memory according to the direction of pupil division, Pupil splitting in any direction can be implemented. In this embodiment, by storing the signal from one photoelectric conversion unit of the selected pixel in the second memory, the interval between the timing of AD conversion of the focus detection signal of the selected pixel and the timing of AD conversion of the imaging signal is reduced. to shorten As a result, focus detection can be performed with sufficient accuracy even for a moving object.

FIG. 20 is a top view of one pixel in this embodiment. Although pixel 20e is shown in FIG. 20, pixels 20f to 20m shown in FIG. 21 have the same configuration. In FIG. 20, one pixel has two photoelectric conversion units arranged in the vertical direction and two in the horizontal direction, for a total of four photoelectric conversion units. Here, the four photoelectric conversion units are photoelectric conversion units 201c, 201d, 201e, and 201f.

By mixing the photoelectric conversion units 201c and 201e and mixing the photoelectric conversion units 201d and 201f, a phase difference detection signal can be obtained when the pupil is divided in the horizontal direction. Further, by mixing the photoelectric conversion units 201c and 201d and mixing the photoelectric conversion units 201e and 201f, it is possible to obtain a phase difference detection signal when pupil division is performed in the vertical direction.

FIG. 22 is a diagram showing the circuit configuration of a pixel in this embodiment. The difference from FIG. 6 is that in FIG. 22, four photoelectric conversion units and four transfer transistors are provided, and signals can be read out independently from each photoelectric conversion unit.

FIG. 21 is a diagram showing a pixel array of 9 pixels included in the unit 102. As shown in FIG. Nine pixels shown in FIG. 21 each include four photoelectric conversion units shown in FIG. FIG. 23 is a diagram showing the configuration of the unit 102 in this embodiment. In FIG. 23, the dashed-dotted lines indicate the elements forming the unit cell, and the dashed lines indicate the elements forming the AD converter.

The unit 102 includes nine pixels shown in FIG. 21, each pixel is provided with a comparator, and constitutes a unit cell. A first memory is provided for each unit cell. Also, the unit 102 is provided with three second memories 23n, 23o, and 23p. Also, FIG. 24 shows the connection relationship between the unit cell and the AD converter at a certain timing. In FIG. 24, the dashed-dotted lines indicate the elements forming the unit cell, and the dashed lines indicate the elements forming the AD converter.

Next, a method for driving the imaging element 100 in this embodiment will be described. In the present embodiment, a fifth mode in which a focus detection signal is obtained by horizontally dividing the pupil from one of the three rows, and a focus detection signal by vertically dividing the pupil from one of the three columns. It has a sixth mode of acquiring the detection signal. FIG. 25 is a timing chart of the fifth mode. Also, FIG. 26 is a timing chart of the sixth mode.

In the fifth mode, focus detection signals are obtained from pixels 20e, 20f, and 20g. First, exposure is performed before the period 701 shown in FIG. 25 to accumulate charges in the photoelectric conversion units 201c, 201d, 201e, and 201f.

In a period 701 shown in FIG. 25, in the pixels 20e, 20f, and 20g, the transfer transistors 202c and 202e shown in FIG. transfer to unit 203; After the charge is transferred to the FD section 203, the transfer transistors 202c and 202e are turned off. After that, the selection transistor 206 is turned on to perform AD conversion.

At this time, the selector 22 connects the comparator 21e to the second memory 23n, the comparator 21f to the second memory 23o, and the comparator 21g to the second memory 23p, and outputs the respective AD conversion results to the second memory. Hold. As a result, focus detection signals obtained by performing pupil division in the horizontal direction can be obtained from three pixels in the first row in the pixel array shown in FIG. 21 . FIG. 24(a) shows the connection relationship between the unit cells and the AD converters in this case.

In a period 702 shown in FIG. 25, the transfer transistors 202c, 202d, 202e, and 202f are turned on in nine pixels from pixels 20e to 20m, and charges accumulated in all the photoelectric conversion units included in the pixels are transferred to the FD unit 203. Forward. After the charge is transferred to the FD section 203, the transfer transistors 202c, 202d, 202e, and 202f are turned off.

After that, the selection transistor 206 is turned on to perform AD conversion. At this time, the selector 22 has a configuration of a unit cell indicated by a dashed line in FIG. 23 and an AD converter indicated by a broken line. A comparator is connected to the first memory for each unit cell, and the imaging signal is held in the first memory provided for each unit cell.

During periods 703 to 705 shown in FIG. 25, the signal processing circuit 106 reads the focus detection signal held in the second memory.

In periods 706 to 714 shown in FIG. 25, the imaging signal held in the first memory is read out by the signal processing circuit 106 . At this time, the imaging signals of the pixels 20e, 20f, and 20g that have acquired the focus detection signals are prioritized in order to generate the focus detection signals paired with the focus detection signals held in the second memory using the imaging signals. read out. This makes it possible to achieve high-speed focus detection.

In the sixth mode, focus detection signals are obtained from pixels 20e, 20h, and 20k. First, exposure is performed before the period 801 shown in FIG. 26 to accumulate charges in the photoelectric conversion units 201c, 201d, 201e, and 201f.

In a period 801 shown in FIG. 26, in the pixels 20e, 20h, and 20k, the transfer transistors 202c and 202d shown in FIG. Transfer to the FD unit 203 . After the charge is transferred to the FD section 203, the transfer transistors 202c and 202d are turned off. After that, the selection transistor 206 is turned on to perform AD conversion.

At this time, the selector 22 connects the comparator 21e to the second memory 23n, the comparator 21h to the second memory 23o, and the comparator 21k to the second memory 23p, and outputs the respective AD conversion results to the second memory. Hold. As a result, focus detection signals obtained by vertical pupil division can be obtained from three pixels in the first column in the pixel array shown in FIG. 21 . FIG. 24(b) shows the connection relationship between the unit cells and the AD converters in this case.

In a period 802 shown in FIG. 26, the transfer transistors 202c, 202d, 202e, and 202f are turned on in nine pixels from pixels 20e to 20m, and charges accumulated in all the photoelectric conversion units included in the pixels are transferred to the FD unit 203. Forward. After the charge is transferred to the FD section 203, the transfer transistors 202c, 202d, 202e, and 202f are turned off. After that, the selection transistor 206 is turned on to perform AD conversion.

At this time, the selector 22 has a configuration of a unit cell indicated by a dashed line in FIG. 23 and an AD converter indicated by a broken line. A comparator is connected to the first memory for each unit cell, and the imaging signal is held in the first memory provided for each unit cell.

During periods 803 to 805 shown in FIG. 26, the signal processing circuit 106 reads the focus detection signal held in the second memory.

In periods 806 to 814 shown in FIG. 26, the imaging signal held in the first memory is read out by the signal processing circuit 106 .

In the fifth mode, the focus detection signal is obtained from the first row, and in the sixth mode, the focus detection signal is obtained from the first column. A focus detection signal can be acquired. Further, by providing a unit unit for an area including pixels of several tens of rows and several tens of columns, it is possible to switch the pixels for acquiring the focus detection signal according to the subject.

In particular, by selecting arbitrary pixels from an area containing pixels of several tens of rows and several tens of columns, the size of the focus detection area, the position of the focus detection area, the pixel thinning rate, and any of R, G, and B pixels can be determined. can be used, or parameters such as can be adjusted to the optimum according to the subject. The parameters are set by recognizing the subject by the signal processing circuit 106 or a signal processing circuit (not shown) connected to the end of the output unit 112 based on the imaging signal of the previous frame, determining the parameters, and sending the result to the selection unit 22. Implement by giving feedback.

Furthermore, not only when one pixel has four photoelectric conversion units, but when it has a larger number of photoelectric conversion units, the combination of photoelectric conversion units for simultaneously reading electric charges is changed according to the image height. Optimum focus detection can be achieved by changing the direction and shape of the pupil division accordingly.

Thus, by providing a unit unit for a pixel area having a plurality of photoelectric conversion units, it is possible to achieve high-speed focus detection with a high degree of freedom using a small amount of memory.

(Other embodiments)
In addition, the present invention supplies a program that implements one or more functions of the above-described embodiments to a system or apparatus via a network or a storage medium, and one or more processors in the computer of the system or apparatus reads the program. It can also be realized by executing processing. It can also be implemented by a circuit (eg, ASIC) that implements one or more functions.

100: image sensor, 102: unit unit, 104: data transfer line, 106: signal processing circuit, 108: pixel driving signal line, 110: pixel driving circuit, 112: output unit, 114: reference signal generation circuit, 116: reference signal line, 118: counter, 120: counter signal line, 122: timing generator (TG)

Claims (18)

An imaging device comprising a plurality of unit units arranged two-dimensionally,
Each of the plurality of unit units is
a pixel having at least one photoelectric conversion unit; an AD conversion unit provided corresponding to each pixel for AD conversion of a signal of the pixel; and an AD conversion unit provided corresponding to each pixel; a plurality of unit cells each including a first memory for storing output data from the conversion unit;
at least one second memory not corresponding to each of said pixels ;
a selection unit that switches between a state in which output data from the AD conversion unit is output to the first memory in the unit cell including the AD conversion unit, and a state in which the output data is output to the second memory;
having
An imaging device characterized by: The unit unit further includes a selection unit that switches an output destination of data stored in the first memory included in the unit unit to the second memory included in the unit unit. The imaging device according to claim 1 . The selection unit outputs data obtained by AD-converting the first signal obtained from the pixel included in the unit cell to the second memory, and continuously obtains the first signal from the pixel. 3. The imaging apparatus according to claim 1 , wherein the second signal is switched to output AD-converted data to the first memory included in the unit cell. The first signal is obtained from one or more pixels selected from pixels included in the unit unit, and the second signal is obtained from all pixels included in the unit unit. 4. The imaging device according to claim 3 . The first signal is a signal independently read out from one or more photoelectric conversion units, and the second signal is a mixture of outputs from all photoelectric conversion units included in one pixel. 5. The imaging device according to claim 4 , wherein the image is a signal. The first signal and the second signal obtained from the pixels that have obtained the first signal are read from the unit before the second signal obtained from the pixels that have not obtained the first signal. 5. The image pickup apparatus according to claim 4 , wherein the image pickup apparatus The selection unit selects signals continuously acquired from pixels included in one unit cell, and includes a first memory included in the one unit cell and a unit cell different from the one unit cell. 2. The imaging apparatus according to claim 1 , wherein connection is switched so as to output to the first memory and the second memory. 8. The imaging apparatus according to claim 7 , wherein said continuously acquired signals are acquired only from some pixels included in said unit unit. At the same time that data is read from at least one of the first memory or the second memory included in the unit unit, data is not read from the first memory or the second memory. 9. The image pickup apparatus according to claim 3 , wherein data is written from said AD converter in a first memory or a second memory. 9. The imaging apparatus according to claim 8 , wherein the continuously acquired signals are signals acquired from pixels provided for focus detection. 9. The imaging apparatus according to claim 8 , wherein the continuously obtained signals are obtained from pixels selected based on the output value of the signal among the pixels in the unit unit. The selection unit outputs data of some bits among data based on signals from pixels included in the unit cell to the first memory provided in the unit cell, and outputs data of the remaining bits. 3. The imaging apparatus according to claim 1 , wherein connection is switched so as to output to said second memory. 3. The imaging apparatus according to claim 1 , wherein the selection unit switches connection according to a shooting mode. The AD conversion unit switches a reference signal for AD conversion according to the intensity of the input signal from the pixel to perform AD conversion, and selects one reference signal regardless of the intensity of the input signal. 14. The imaging apparatus according to claim 13 , further comprising a mode in which AD conversion is performed using an AD converter, and wherein the selection unit switches connection of the memory according to the mode of the AD conversion unit. The pixels included in the unit unit include a plurality of photoelectric conversion units arranged in at least two directions of a first direction and a second direction. a mode in which signals from one or more photoelectric conversion units are mixed and read so that the signals from one or more photoelectric conversion units are read out in the first direction; 14. The imaging apparatus according to claim 13 , further comprising a mode for mixing and reading out signals of , wherein the selection unit switches connection of the memory according to the imaging mode. An imaging device comprising a plurality of unit units arranged two-dimensionally, wherein each of the plurality of unit units is provided corresponding to each pixel having at least one photoelectric conversion unit. , a plurality of unit cells each including an AD converter for AD-converting a signal of the pixel, and a first memory provided corresponding to each pixel and storing output data from the AD converter; , at least one second memory that does not correspond to each of the pixels, and outputs output data from the AD converter to the first memory in the unit cell including the AD converter. A method for controlling an imaging device having a selection unit for switching between a state and a state for outputting to the second memory ,
switching between a state in which the selection unit outputs the output data from the AD conversion unit to the first memory in the unit cell including the AD conversion unit, and a state in which the output data is output to the second memory; A control method for an imaging device, comprising: A program for causing a computer to execute the control method according to claim 16 . A computer-readable storage medium storing a program for causing a computer to execute the control method according to claim 16 .

Images