JP6393087B2 - Imaging device and imaging apparatus - Google Patents

Imaging device and imaging apparatus Download PDF

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JP6393087B2
JP6393087B2 JP2014123816A JP2014123816A JP6393087B2 JP 6393087 B2 JP6393087 B2 JP 6393087B2 JP 2014123816 A JP2014123816 A JP 2014123816A JP 2014123816 A JP2014123816 A JP 2014123816A JP 6393087 B2 JP6393087 B2 JP 6393087B2
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JP2016005104A (en
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隆史 岸
隆史 岸
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キヤノン株式会社
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Description

  The present invention relates to a technique for reducing the number of pixels in an image sensor.
  In recent digital cameras, while the number of pixels of an image sensor such as a CMOS sensor has been increased, there is a need for high frame rate shooting such as outputting 1920 × 1080 pixels at 30 fps or 60 fps as in a Full-HD video, for example. Is also growing.
  In response to this need, a thinning-out method is known as a method for realizing high frame rate shooting by reducing the number of pixels of a high-pixel imaging device in the case of moving image shooting. In the thinning-out method, pixels are skipped at a specific cycle, and the data rate is lowered to increase the frame rate by reducing the number of pixels. In this method, pixels are skipped at a specific cycle. Therefore, as a characteristic of a captured image, there is a problem that moire, which is a kind of aliasing noise, is conspicuous while it is advantageous for edge detection of a subject. Therefore, as a technique for reducing moiré, a technique has been proposed in which pixels skipped in the thinning-out technique are mixed with adjacent readout pixels to reduce the number of pixels for output.
  In the pixel mixing method proposed in Patent Document 1, a plurality of rows of pixel signals are mixed and output by simultaneously selecting and outputting a plurality of rows by a row selection circuit. The above-described method has an effect of reducing moire and converging random noise by obtaining a mixed output of a plurality of pixels. From the above effects, in general, a pixel mixing method in which mixing is performed in a CMOS image sensor to reduce the number of pixels is superior to a simple thinning method in terms of image quality.
JP 2010-259027 A
  However, the pixel mixing method is disadvantageous for the detection of the edge of the subject and has a problem that the image has a low resolution.
  The present invention has been made in view of the above-described problems, and an object of the present invention is to provide a technique for reducing the number of pixels that can acquire an image with a high resolution feeling while reducing moire compared to the thinning technique. .
The imaging device according to the present invention each includes a photodiode and a MOS amplifier that reads the signal of the photodiode, and includes a plurality of pixels arranged in a matrix and a column from which the signals of the plurality of pixels are output. A signal line and a selection unit capable of simultaneously outputting a signal of a predetermined number of pixels to the column signal line via the MOS amplifier of each pixel, and the selection unit simultaneously outputs the signal to the column signal line. among the predetermined number of pixels but outputted, the MOS amplifiers of the at least one pixel, oxide film thickness, the gate length, either the gate width Unlike other pixels, the plurality of pixels by the selection means Are separately output to the column signal line, the pixel having a different oxide film thickness, gate length, or gate width of the MOS amplifier, the oxide film thickness of the MOS amplifier, and the gate , The gate width and the same pixel, and correcting the signal of a pixel using different correction values.
  According to the present invention, it is possible to provide a technique for reducing the number of pixels that can acquire an image with a high resolution feeling while reducing moire compared to the thinning technique.
1 is a diagram schematically illustrating an overall configuration of an image sensor according to a first embodiment of the present invention. 2A and 2B are diagrams illustrating a pixel configuration and a circuit configuration for reading a signal from the pixel. 3 is a timing chart illustrating a method for driving the image sensor according to the first embodiment. The figure which shows typically pixel arrangement | positioning of the image pick-up element of 1st Embodiment. The figure which illustrates typically the drive method when not mixing a pixel. FIG. 3 is a diagram illustrating a configuration of a pixel and a configuration of a circuit that reads a signal from the pixel. 9 is a timing chart illustrating a method for driving an image sensor according to the second embodiment. The timing chart which shows the drive method when not mixing a pixel. FIG. 3 is a diagram illustrating a configuration of a pixel and a configuration of a circuit that reads a signal from the pixel. The figure which shows typically pixel arrangement | positioning of the image pick-up element of 3rd Embodiment. 9 is a timing chart illustrating a method for driving an image sensor according to a fourth embodiment. The figure which shows typically pixel arrangement | positioning of the image pick-up element of 5th Embodiment. The figure which shows typically the pixel arrangement | positioning of the modification of 5th Embodiment. The figure which shows typically the pixel arrangement | positioning of the further modification of 5th Embodiment. The block diagram of the digital camera to which the image sensor of the embodiment is applied.
  Embodiments of the present invention will be described below in detail with reference to the accompanying drawings.
(First embodiment)
FIG. 1 is a diagram showing an outline of an image sensor according to the first embodiment of the present invention. In FIG. 1, the imaging device 100 includes a pixel array 101, a vertical selection circuit 102 that selects a row in the pixel array 101, and a horizontal selection circuit 104 that selects a column in the pixel array 101. Further, it further includes a readout circuit 103 that reads a signal of a pixel selected by the vertical selection circuit 102 among the pixels in the pixel array 101, and a serial interface 105 for determining an operation mode of each circuit from the outside. The reading circuit 103 includes a memory for storing signals, a gain amplifier, an AD converter, and the like for each column. In addition to the illustrated components, the image sensor 100 includes a timing generator or a control circuit that provides timing to the vertical selection circuit 102, the horizontal selection circuit 104, the readout circuit 103, and the like, for example.
  In the present embodiment, the vertical selection circuit 102 sequentially selects a plurality of rows of the pixel array 101 and reads them to the reading circuit 103. The horizontal selection circuit 104 sequentially selects a plurality (predetermined number) of pixel signals read by the reading circuit 103 for each column and outputs them to the outside.
  FIG. 2 is a diagram illustrating a configuration of a pixel in the image sensor of the present embodiment and a configuration of a circuit that reads a signal from the pixel. A pixel array that provides a two-dimensional image is configured by arranging a plurality of pixels in a matrix.
  Each pixel 201 includes a photodiode (hereinafter also referred to as PD) 202, a transfer switch 203, a floating diffusion portion (hereinafter also referred to as FD) 204, a reset switch 207, a MOS amplifier 205, and a selection switch 206. Consists of including.
  A pulse for driving the switch is supplied from the vertical selection circuit 102. These pulse signals are sent simultaneously to the pixels in the same row. Pulses φTXn, φSELn, and φRESn for driving the pixels in the n-th row are simultaneously supplied to the respective pixels in the n-th row.
  The PD 202 functions as a photoelectric conversion unit that photoelectrically converts light incident through the optical system. The anode of the PD 202 is connected to the ground line, and the cathode is connected to the source of the transfer switch 203. The transfer switch 203 is driven by a transfer pulse φTXn input to its gate terminal, and transfers charges generated in the PD 202 to the FD 204. The FD 204 functions as a charge-voltage conversion unit that temporarily accumulates charges and converts the accumulated charges into a voltage signal.
  The MOS amplifier 205 functions as a source follower, and a signal that has been subjected to charge-voltage conversion by the FD 204 is input to its gate. The MOS amplifier 205 has a drain connected to the power supply line VDD and a source connected to the selection switch 206. The selection switch 206 is driven by a selection pulse φSELn input to its gate, its drain is connected to the amplification MOS amplifier 205, and its source is connected to the column signal line 208. When the selection pulse φSELn becomes active level (high level), the selection switch 206 of the pixel belonging to the corresponding n-th row of the pixel array is turned on, and the source of the MOS amplifier 205 is connected to the column signal line 208.
  The reset switch 207 has its drain connected to VDD, its source connected to the FD 204, and is driven by a reset pulse φRESn input to its gate to remove charges accumulated in the FD 204. The FD 204, the MOS amplifier 205, and the constant current source 209 that supplies a constant current to the column signal line 208 constitute a floating diffusion amplifier. In each pixel constituting the row selected by the selection switch 206, the charge transferred to the FD 204 is converted into a voltage signal by the FD 204 and output to the corresponding readout circuit 103 through the floating diffusion amplifier. The signals read to the reading circuit 103 are sequentially selected by the horizontal selection circuit 104 and transmitted to the outside of the image sensor.
  Next, driving for performing mixed output of pixel signals of a plurality of rows by simultaneously selecting and outputting a plurality of rows by a row selection circuit with respect to the circuit configuration diagram described in FIG. 2 will be described with reference to the drawings.
  FIG. 3 is a timing chart showing the drive timing of the image sensor 100 of the present embodiment. Here, a description will be given for selecting and reading out pixel signals for three rows of pixels in the n-2th row and the n + 2th row with the pixel in the nth row as the center, but the number of pixels to be simultaneously selected is It is not limited to three.
  The reset switch φRESn-2, φRESn, φRESn + 2 is set to a low level and a selection pulse φSELn-2, φSELn, φSELn + 2 is set to a high level at a time t301 after a lapse of a predetermined time after the photographing signal is accumulated in the PD 202, thereby resetting the reset switch φRESn-2, φRESn, φRESn + 2 207 is turned off. At the same time, the selection switches 206 are turned on simultaneously for three rows, and the pixels 201 are connected to the column signal lines 208. When the above operation is completed, the column signal line 208 is mixed with and output the potentials obtained by resetting the FDs 204 in the (n−2, n, n + 2) th rows. The mixed output of the reset potential of the FD 204 is held in the reading circuit 103.
  Next, after the transfer pulses φTxn−2, φTxn, and φTxn + 2 are changed to the high level in the period T302, the signals of the PDs 202 of the pixels for three rows are transferred to the respective FDs 204. When the above operation is completed, the signal potential of the FD 204 after the signal is transferred from the PD 202 of each of the pixels in the n−2, n, and n + 2 rows to the FD 204 is mixed and output to the column signal line 208. Retained. CDS of mixed output of signal potential and mixed output of reset potential is performed. As a result, a signal obtained by subtracting the reset component from the signal can be acquired, and the difference signal is output to the outside by the horizontal selection circuit 104. By performing the driving described above, it is possible to mix signals from a plurality of pixels.
  Here, a signal voltage appearing on the column signal line 208 will be described. The voltage Vout appearing on the column signal line 208 is expressed by the following equation depending on the parameter k of the MOS amplifier 205 and the current I flowing through the constant current source 209.
I = k / 2x (Vfd−Vth−Vout) 2 (Formula 1)
Vth is the threshold voltage of the MOS amplifier 205, and Vfd is the voltage of the FD 204. K is
k = μxCox W / L (Formula 2)
This is a parameter of the MOS amplifier 205 expressed by μ is the electron mobility, Co is the gate oxide film thickness, W is the gate width, and L is the gate length.
Since the current flowing through the column signal line 208 is defined by the constant current source 209, when connecting the signals of three pixels to the column signal line at the same time,
I = k (n−2) / 2x (Vfd (n−2) −Vth−Vout) 2 + k (n) / 2x (Vfd (n) −Vth−Vout) 2 + k (n + 2) / 2x (Vfd (n + 2) ) -Vth-Vout) 2 (Formula 3)
It becomes. k (n−2), k (n), and k (n + 2) indicate parameters of the MOS amplifier 205 of the pixels in the n−2th row, the nth row, and the n + 2th row, respectively. Vfd (n−2), Vfd (n), and Vfd (n + 2) indicate the voltages of the FDs 204 of the pixels in the n−2th row, the nth row, and the n + 2th row, respectively.
  As shown in Equation 3, the current defined by the constant current source 209 is shared by the amplification MOS 205 of the pixels connected to the column signal line at the same time, and as a result, an average output is obtained.
  Here, the parameter k (n) of the MOS amplifier 205 of the pixel in the n-th row is set to the parameters k (n−2) and k (n + 2) of the MOS amplifier 205 of the pixel in the n−2 and n + 2 rows. By increasing the ratio, the ratio of the current flowing through the MOS amplifier 205 of the pixel in the nth row is increased. By doing so, the influence of the signal in the n-th row can be further increased, and the output signal ratio can be changed with respect to the ratio of the signals obtained in the pixels.
  For example, if the parameter k of the MOS amplifier 205 is k (n−2): k (n): k (n + 2) = 1: 2: 1, the pixels of the n−2th row, the nth row, and the n + 2th row The signal is output at a ratio of 1: 2: 1. That is, when simultaneously connecting a plurality of pixels to a vertical line, by changing the parameter k of the MOS amplifier 205 of the pixels to be connected at the same time, a filter effect for weighting the signal obtained by the PD 202 of the pixel is obtained. It becomes possible to grant. Specifically, the oxide film thickness of the MOS amplifier 205 of the pixel whose weight is desired to be increased may be reduced, the gate width W may be increased, or the gate length L may be decreased. In this way, by performing weighting, it becomes possible to extract high-frequency components, and an image with high resolution can be obtained, as compared with a simple mixing method.
  Next, with reference to the drawings, a description will be given of which pixel signal is weighted. FIG. 4 is a diagram schematically showing the arrangement of pixels. This is schematically shown as a pixel configuration of 8 rows and 8 columns, but actually there are more pixels. Symbols V0 to V7 indicate rows. Symbols R, Gr, Gb, and B indicate color filters arranged in each pixel, and symbols a and b in parentheses indicate that the parameters of the MOS amplifier 205 are different here. Assume that the MOS parameter of the MOS amplifier 205 of the pixel indicated by (a) is k1, and the MOS parameter of the MOS amplifier 205 of the pixel indicated by (b) is k2. Usually, mixing is performed for pixels having the same color filter. The pixels in the V0, V2, and V4 rows are selected simultaneously. The parameter k of the MOS amplifier 205 in the V0 and V4 rows is k1, and the parameter k of the MOS amplifier 205 in the V2 row is k2. To read the pixel signals in the V0, V2, and V4 rows at the same time, driving may be performed based on the timing chart shown in FIG.
  Here, by setting k1: k2 = 1: 2, the pixel signals in the V0, V2, and V4 rows become signals weighted at a ratio of 1: 2: 1. The V3, V5, and V7 lines are the same as the V0, V2, and V4 lines.
  As described above, the signals of the pixels adjacent in the column direction (vertical direction) having the same color filter are simultaneously connected to the column signal line 208, and the parameters of the MOS amplifier 205 are changed among the simultaneously selected pixels. As a result, it is possible to obtain a weighted mixed signal.
  In the above description, the timing and effect of selecting a plurality of pixels at the same time have been described. However, when reading without mixing pixels in the column direction (vertical direction), such as when shooting a still image, separate driving is required. Become. This will be described with reference to the drawings.
  FIG. 5 shows a timing chart for reading out the pixels in the column direction (vertical direction) of this embodiment without mixing them. In the timing chart shown in FIG. 3, the transfer switch 203, the reset switch 207, and the selection switch 206 of the pixels in the (n−2) th row, the nth row, and the (n + 2) th row are simultaneously driven at the time t301 and the period T302. In the timing chart shown in FIG. 5, the transfer switch 203, the reset switch 207, and the selection switch 206 of the pixels on the (n−2) th row, the nth row, and the n + 2th row are driven at different times.
  In light of FIG. 3, the transitions of the high level and low level of the reset switch 207 and the selection switch 206 performed at time t301 are at times t501 and t503 at the n-2th row, the nth row, and the n + 2th row, respectively. , At another time of t505. Similarly, the transition of the high level and the low level of the transfer switch 203 performed in the period T302 is performed in the other periods of the periods T502, T504, and T506 in the n-2th row, the nth row, and the n + 2th row, respectively. . In this way, pixels in the column direction (vertical direction) can be read independently without selecting a plurality of rows of pixels simultaneously.
  When driving for independently reading out pixels in the column direction (vertical), the parameter k of the MOS amplifier 205 of the pixels in the n-th row is different from that in the pixels in the (n−2) th row and the (n + 2) th row. The operating range at 208 changes. For this reason, the dark characteristics of the pixels in the n-th row change with respect to the pixels in the (n-2) -th row and the n + 2-th row. Therefore, in the driving for independently reading out the pixels in the column direction (vertical direction), correction data (correction value) for correcting the dark characteristics of the pixels in the (n−2) th row, the (n + 2) th row, and the pixels in the nth row. Are separately provided and corrected separately.
  In the V0 to V7 rows shown in FIG. 4, correction is performed by switching the correction data of the pixels in the V0, V1, V3, V4, V6, and V7 rows and the pixels in the V2 and V5 rows. Further, not only dark characteristics but also characteristics such as linearity that change as the operation range of the column signal line 208 is changed are corrected for pixels in the V0, V1, V3, V4, V6, and V7 rows, and in the V2 and V5 rows. The correction data of the pixels may be switched.
  As described above, by changing the parameters of the MOS amplifier 205 depending on the pixel, the mode in which the pixels in the column direction (vertical direction) are read independently without being mixed and the mode in which a plurality of pixels are simultaneously connected to the column signal line and mixed are achieved. However, it is possible to obtain a weighted signal in a mode in which a plurality of pixels are connected simultaneously. By performing weighting, it is possible to extract high-frequency components as compared with a simple mixing method, and an image with high resolution can be obtained.
  The mode in which the pixels in the column direction (vertical direction) shown in FIG. 5 are read out independently without being mixed is suitable for still image shooting that requires high resolution and high resolution, and a plurality of pixels shown in FIG. The mode of connecting to the signal line and mixing is appropriate for moving image shooting that requires a high frame rate.
(Second Embodiment)
Next, a configuration that performs weighting while making the correction described in the first embodiment unnecessary is described.
  FIG. 6 is a diagram illustrating a configuration of a pixel and a configuration of a circuit that reads a signal from the pixel in the image sensor according to the second embodiment of the present invention. The pixel 601 is different from the pixel 201 illustrated in FIG. 2 in that there are two circuits for reading the signal of the FD 204. Specifically, the gates of two MOS amplifiers, MOS amplifiers 602 and 604, are connected to the FD 204, and selection switches 603 and 605 are provided for the respective MOS amplifiers. The selection switch 603 is driven by a selection pulse φSELAn, and the selection switch 605 is driven by a selection pulse φSELBn.
  The MOS parameter of the MOS amplifier 602 connected to the column signal line 208 by the selection switch 603 is set to the same k1 for all pixels. The MOS parameter of the MOS amplifier 604 connected to the column signal line 208 by the selection switch 605 is k2 for the weighted pixel and k3 for the non-weighted pixel. Moreover, k1 and k3 may be the same.
  With respect to the circuit configuration diagram described with reference to FIG. 6, driving for performing mixed output of pixel signals of a plurality of rows by simultaneously selecting and outputting a plurality of rows by a row selection circuit will be described with reference to the drawings. FIG. 7 is a timing chart of driving for performing mixed output according to the present embodiment.
  The operations of the reset pulses φRESn−2, φRESn, and φRESn + 2 at time t701 are the same as at time t301. At time t701, the selection pulses φSELAn-2, φSELAn, and φSELAn + 2 do not transition to a high level, so that the selection switch 603 is not turned on. Further, the selection pulses φSELBn−2, φSELBn, and φSELBn + 2 transit to a high level, and the selection switch 605 is turned on. Here, the MOS parameter of the MOS amplifier 604 of the pixel in the nth row is k2, the MOS parameter of the MOS amplifier 604 of the pixel in the (n−2) th row and the (n + 2) th row is k3, and k2> k3. It becomes possible to weight the signals of the pixels in the row. Specifically, the pixel MOS amplifier 604 indicated by (a) in FIG. 4 may be k3, and the pixel MOS amplifier 604 indicated by (b) may be k2.
  On the other hand, when reading without mixing pixels in the column direction (vertical direction), the selection switch to be used is changed. FIG. 8 shows a timing chart for reading out the pixels in the column direction (vertical direction) of this embodiment without mixing them. The only difference from the timing chart shown in FIG. 5 is that the selection pulses φSELBn−2, φSELBn, and φSELBn + 2 are in the low level state, and the description thereof is omitted. Here, the MOS amplifier 604 having different MOS parameters for each pixel is not connected to the column signal line 208 by the selection switch 605, and the MOS amplifier 602 having the same MOS parameter is connected to the column signal line 208 in all pixels. By driving in this way, when driving to read out pixels in the column direction (vertical direction) individually, the MOS parameters of the MOS amplifiers of all the pixels can be read out in the same state. On the other hand, correction due to different MOS parameters for each row is not necessary.
  In this embodiment, the parameters of the MOS amplifier 602 and the MOS amplifier 604 are changed in the pixel, and the MOS amplifier connected to the column signal line 208 is changed in the drive mode. As a result, it is possible to obtain a weighted signal in a mode in which a plurality of pixels are simultaneously connected while achieving both a mode in which all pixels are read without being mixed and a mode in which a plurality of pixels are simultaneously connected.
(Third embodiment)
Next, a method for performing weighting in the row direction (horizontal direction) will be described. FIG. 9 is a diagram illustrating a configuration of a pixel in an image sensor according to the third embodiment of the present invention and a configuration of a circuit that reads a signal from the pixel. The configuration of one pixel is the same as that of the pixel 601 described in the second embodiment, but a plurality of columns of pixels are connected to one column signal line 208. In the first and second embodiments, the mixing and weighting in the vertical column direction is performed. However, with this configuration, the mixing and weighting in the horizontal row direction is possible, and the weights in both the vertical and horizontal directions are possible. It can also be attached. Although FIG. 9 shows two columns of pixels, three or more columns are more preferable.
  Next, with reference to the drawings, a description will be given of which pixel signal is weighted. FIG. 10 is a diagram schematically showing the arrangement of pixels. Symbols V0 to V7 indicate rows, and symbols H0 to H7 indicate columns. Symbols R, Gr, Gb, and B indicate color filters arranged in each pixel, and symbols a, b, and c in parentheses indicate that the parameters of the MOS amplifier 604 are different here. The MOS parameter of the MOS amplifier 604 of the pixel shown in (a) is k1, the MOS parameter of the MOS amplifier 604 of the pixel shown in (b) is k2, and the MOS parameter of the MOS amplifier 604 of the pixel shown in (c) is k3. And Usually, mixing is performed for pixels having the same color filter. Here, nine pixels belonging to the V0, V2, and V4 rows and belonging to the H0, H2, and H4 columns are simultaneously selected and connected to the column signal line 208. Since the barycentric pixel of the mixed pixel in this case is the pixel in the V2 row and the H2 column, the pixel is weighted most, and then the pixel in the V2 row and the H2 column is positioned on the top, bottom, left, and right of the pixel in the V2 column and the H2 column. The pixels in the first, V2, H4, V0, H2, and V4, H2 columns are weighted next. That is, by setting k3> k2> k1, it is possible to obtain a signal in which the centroid pixel is most weighted.
  In this embodiment, adjacent pixels of the same color in the row direction and the column direction are connected to the column signal line 208, and the parameters of the MOS amplifier 602 and the MOS amplifier 604 are changed in the pixel. The MOS amplifier 604 has a larger MOS parameter than the MOS amplifier 604 of the center-of-gravity pixel in the matrix direction. With this configuration, it is possible to obtain a weighted signal as it approaches the barycentric pixel in both the matrix direction. Further, when reading without mixing pixels, correction due to different MOS parameters as in the second embodiment is also unnecessary.
(Fourth embodiment)
Next, a method for weighting with a simpler pixel configuration will be described. In FIG. 6, the MOS parameters k1 and k2 of the MOS amplifiers 602 and 604 are made the same. In this case, weighting cannot be performed in the timing chart shown in FIG. 7, but weighting can be performed by changing the driving method. This will be described below with reference to the drawings.
  FIG. 11 is a timing chart of driving for performing mixed output according to the fourth embodiment of the present invention. The operations of the reset pulses φRESn−2, φRESn, and φRESn + 2 at time t1101 are the same as at time t301. At time t1101, the selection pulses φSELBn−2, φSELBn, and φSELBn + 2 transit to a high level, and the selection switch 605 is turned on as in the timing chart shown in FIG. The only difference is that at time t1101, only the selection pulse φSELAn of the pixels in the n-th row weighted among the selection pulses φSELAn-2, φSELAn, and φSELAn + 2 transits to a high level, and the selection pulses φSELAn-2 and φSELAn + 2 are at a low level. It is. In this way, the selection switches 603 and 605 are turned on only for the pixels in the nth row to be weighted, and the MOS amplifiers 602 and 604 are connected to the column signal line 208. In the (n−2) th row and the (n + 2) th row, only the MOS amplifier 604 is connected to the column signal line 208. When driven in this way, pixels (partial pixels) in the nth row are driven by two MOS amplifiers, and pixels in the (n−2) and (n + 2) th rows are driven by one MOS amplifier. Only the eye pixels can be weighted at a ratio of 1: 2: 1. The operation of the transfer pulse φTXn in the period T302 is the same as described above. The specific pixel arrangement may be the same as the arrangement shown in FIG. 4, and the driving shown in the nth row is performed on the pixel shown in (b), and the driving shown in the n−2 and n + 2th rows is performed. What is necessary is just to perform with respect to the pixel shown by (a). When weighting is to be performed at a ratio of 1: 2: 1 or more, for example, 1: 3: 1, the number of MOS amplifiers and selection switches for reading out the signal of the FD 204 may be increased, and driving may be performed in the same way.
  With the driving described above, the MOS parameters of the MOS amplifiers 602 and 604 of the pixels can be made the same, so that it is possible to simplify manufacturing and obtain a weighted signal.
(Fifth embodiment)
Next, a method for realizing weighting by further reducing the number of pixel circuits will be described. In the configurations of the second and third embodiments, the MOS amplifier 604 and the selection switch 605 are increased in one pixel, and therefore the area of the pixel is pressed. By mixing the signal of the pixel 201 shown in FIG. 2 and the signal of the pixel 601 shown in FIG. 6, the number of switches can be reduced.
  FIG. 12 is a diagram schematically illustrating the arrangement of pixels. The pixel (a) has the same configuration as the pixel 201 shown in FIG. 2, and the pixels (b) and (c) have the same configuration as the pixel 601 shown in FIG. The V0, V2, V4, and V6 row color filters are R and Gr rows are MOS amplifiers and the selection switch is a single pixel, and the V1, V3, V5, and V7 color filters are Gb and B rows. Both the MOS amplifier and the selection switch are pixels having two configurations. The operation of the pixel selection switch in (a) and (b) is shown in the n-2 and n + 2 rows in FIG. 11, and the operation of the pixel selection switch in (c) is shown in the n row in FIG. When in operation, it is possible to weight.
  Here, weighting is possible only in the rows where the color filters Gb and B exist, and weighting is not possible in the rows where the color filters R and Gr exist. It becomes possible to reduce.
  FIG. 13 is a diagram schematically illustrating the arrangement of pixels according to a modification of the fifth embodiment. The pixel (a) has the same configuration as the pixel 201 shown in FIG. 2, and the pixel (b) has the same configuration as the pixel 601 shown in FIG. The V0, V1, V2, V3, V4, V6, and V7 rows are pixels having one configuration for both the MOS amplifier and the selection switch, and the V5 row is a pixel having two configurations for both the MOS amplifier and the selection switch. When the operation of the pixel selection switch in (a) is the operation shown in the n-2 and n + 2 rows in FIG. 11, and the operation of the pixel selection switch in (b) is the operation shown in the nth row in FIG. It is possible to weight. Similar to the configuration shown in FIG. 12, weighting cannot be performed in a row where the color filters R and Gr exist. In addition, since the pixels that can be weighted are fixed in the row where the color filters Gb and B exist, it is not possible to select averaging of three rows, averaging of five rows, but the number of switches is further reduced. It becomes possible.
  FIG. 14 is a diagram schematically illustrating the arrangement of pixels according to a further modification of the fifth embodiment. The pixel (a) has the same configuration as the pixel 201 shown in FIG. 2, and the pixels (b) and (c) have the same configuration as the pixel 601 shown in FIG. Pixels with R and B color filters are pixels of one configuration for both the MOS amplifier and selection switch, and pixels with color filters Gr and Gb are pixels of two configurations for both the MOS amplifier and selection switch. The operation of the pixel selection switch in (a) and (b) is shown in the n-2 and n + 2 rows in FIG. 11, and the operation of the pixel selection switch in (c) is shown in the n row in FIG. When in operation, it is possible to weight.
  Here, only Gr and Gb pixels of the color filter can be weighted, and weighting cannot be performed on the R and B pixels of the color filter, but the number of switches can be reduced accordingly. It becomes. A configuration may be used in which weighting is performed only on the R and B pixels of the color filter and weighting is not performed on the Gr and Gb pixels. Further, the pixel having the configuration (b) may be the same as the configuration (a).
  With the pixel configuration and driving described above, weighting can be performed while reducing the number of switches in the pixel. Since the weighting rows and color filters are limited, the resolution is lowered with respect to the methods of the third and fourth embodiments, but the number of switches in the pixel can be reduced. This is suitable for an image pickup device having pixels with more gorgeous pitches.
  An example in which the above-described imaging element driving method is applied to a digital camera which is an imaging apparatus will be described.
  In FIG. 15, a lens unit 1501 forms an optical image of a subject on an image sensor 1505, and zoom control, focus control, aperture control, and the like are performed by a lens driving device 1502. The mechanical shutter 1503 is controlled by a shutter driving device 1504. The image sensor 1505 captures the subject image formed by the lens unit 1501 as an image signal. The image signal processing circuit 1506 performs various corrections on the image signal output from the image sensor 1505 and compresses data. A timing generator 1507 is a driving unit that outputs various timing signals to the image sensor 1505 and the image signal processing circuit 1506. A total control / calculation unit 1509 controls various calculations and the entire imaging apparatus. The memory 1508 temporarily stores image data. A recording medium control I / F unit 1510 is an interface for performing recording or reading on a recording medium. A recording medium 1511 is a detachable recording medium such as a semiconductor memory for recording or reading image data. A display unit 1512 displays various information and captured images.
  Next, the operation of the digital camera at the time of shooting in the above configuration will be described. When the main power supply is turned on, the power supply for the control system is turned on, and the power supply for the image pickup system circuit such as the image pickup signal processing circuit 1506 is turned on.
  Thereafter, when a release button (not shown) is pressed, a high-frequency component is extracted based on the signal output from the focus detection device 1514 and the subject focus detection calculation is performed by the overall control / calculation unit 1509. Thereafter, the lens unit is driven by the lens driving device 1502 to determine whether it is in focus. When it is determined that the lens unit is not in focus, the lens unit is driven again to perform focus detection. When focus detection is performed by the image sensor 1505, the shutter 1503 is opened to project a subject image on the image sensor 1505, and an image signal processing circuit 1506 and an overall control / calculation unit 1509 are used using a focus detection signal from the image sensor 1505. The focus detection calculation may be performed with Then, after the in-focus state is confirmed, the photographing operation is started.
  When the photographing operation ends, the image signal output from the image sensor 1505 is subjected to image processing by the photographing signal processing circuit 1506 and written to the memory 1508 by the overall control / arithmetic unit 1509. Thereafter, the data stored in the memory 1508 is recorded on a removable recording medium 1511 such as a semiconductor memory through the recording medium control I / F unit 1510 under the control of the overall control / arithmetic unit 1509. Further, the image may be processed by directly inputting to a computer or the like through an external I / F unit (not shown).
(Other embodiments)
The present invention can also be realized by executing the following processing. That is, software (program) that realizes the functions of the above-described embodiments is supplied to a system or apparatus via a network or various storage media, and a computer (or CPU, MPU, etc.) of the system or apparatus reads the program. It is a process to be executed.
100: imaging device, 101: pixel array, 102: vertical selection circuit, 103: readout circuit, 104: horizontal selection circuit, 202: photodiode

Claims (5)

  1. A plurality of pixels each having a photodiode and a MOS amplifier that reads out a signal of the photodiode, arranged in a matrix,
    Column signal lines from which signals of the plurality of pixels are output;
    Selection means capable of simultaneously outputting a signal of a predetermined number of pixels to the column signal line via the MOS amplifier of each pixel;
    Of the predetermined number of pixels to which signals are simultaneously output to the column signal line by the selection means, any one of the oxide film thickness, gate length, and gate width of the MOS amplifier of at least one pixel is different from that of other pixels. different Ri,
    When the signal of the plurality of pixels is separately output to the column signal line by the selection unit, the pixel having a different oxide film thickness, gate length, or gate width of the MOS amplifier, and the oxide film of the MOS amplifier An image sensor, wherein a pixel signal is corrected using different correction values for pixels having the same thickness, gate length, and gate width .
  2. A plurality of pixels each having a photodiode, a first MOS amplifier for reading out the signal of the photodiode, and a second MOS amplifier for reading out the signal of the photodiode;
    A column signal line from which the pixel signal is output;
    Selection means capable of simultaneously outputting a signal of a predetermined number of pixels to the column signal line via at least one of the first and second MOS amplifiers of each pixel;
    Signals of some of the predetermined number of pixels are output to the column signal line via the first and second MOS amplifiers of the respective pixels, and other signals of the predetermined number of pixels are output. An image sensor, wherein a pixel signal is output to the column signal line via the first or second MOS amplifier of each pixel.
  3. 3. The image pickup device according to claim 2 , wherein pixels that output signals to the column signal lines via the first and second MOS amplifiers are arranged at different positions in the row direction.
  4. 4. The image pickup device according to claim 2, wherein a pixel that outputs a signal to the column signal line via the first and second MOS amplifiers has a different color filter. 5.
  5. Imaging apparatus characterized by comprising an imaging element according to any one of claims 1 to 4.
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