JP2018098444A - Electronic device - Google Patents

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JP2018098444A
JP2018098444A JP2016244350A JP2016244350A JP2018098444A JP 2018098444 A JP2018098444 A JP 2018098444A JP 2016244350 A JP2016244350 A JP 2016244350A JP 2016244350 A JP2016244350 A JP 2016244350A JP 2018098444 A JP2018098444 A JP 2018098444A
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circuit
electronic device
reference circuit
chip
shield
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JP6631494B2 (en
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哲平 川本
Teppei Kawamoto
哲平 川本
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Denso Corp
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Denso Corp
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    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805Shape
    • H01L2224/4809Loop shape
    • H01L2224/48091Arched
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481Disposition
    • H01L2224/48151Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151Die mounting substrate
    • H01L2924/153Connection portion
    • H01L2924/1531Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
    • H01L2924/15311Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181Encapsulation

Abstract

PROBLEM TO BE SOLVED: To provide an electronic device capable of carrying out quality inspection of an object to be inspected such as solder ball while avoiding characteristics fluctuation of the element.SOLUTION: An electronic device 10 includes: a circuit board 16 which has a first face in a first direction and a second face in a second direction opposite to the first direction; an IC chip 12 disposed on the first face of the circuit board; an object to be inspected 24 disposed on the second face of the circuit board; a reference circuit 14 disposed on the IC chip; a circuit 30 other than the reference circuit disposed on the IC chip; and a shield 26 which covers the first direction side of the reference circuit but does not cover the first direction side of the circuit other than the reference circuit, and which can shield X-ray.SELECTED DRAWING: Figure 1

Description

本発明は、電子装置に関する。   The present invention relates to an electronic device.

半導体装置の製造工程や実装工程では、X線などの放射線を照射して半導体装置の透過像を観察することにより、半導体部品のはんだ実装などにおける接着面の観察やコネクタケーブルの接続状態の観察などのように、直接目視などで観察できない部位においての不良検査が行なわれている。半導体装置がX線などの強い放射線を照射された場合には、半導体装置中の素子の特性が変動する場合があることが知られている。そこで、半導体装置のチップを遮蔽するように金属のフィルタを設けることによって放射線のエネルギーを吸収もしくは減衰させ、半導体装置中の素子の特性変動を抑制する手法がある。   In the manufacturing process and mounting process of semiconductor devices, by observing the transmitted image of the semiconductor device by irradiating radiation such as X-rays, etc., observation of the adhesive surface in solder mounting of semiconductor components, etc., and observation of the connection state of the connector cable, etc. As described above, a defect inspection is performed at a site that cannot be observed directly by visual observation or the like. It is known that the characteristics of elements in a semiconductor device may fluctuate when the semiconductor device is irradiated with strong radiation such as X-rays. Therefore, there is a technique for absorbing or attenuating radiation energy by providing a metal filter so as to shield the chip of the semiconductor device, thereby suppressing fluctuations in characteristics of elements in the semiconductor device.

しかし、一方でBGA(Ball Grid Array)やQFN(Quad Flatpack No Lead)等のようにパッケージの裏面に電極が存在するものについては、X線透過画像によるはんだ実装時の接着面の不良チェックの際に、素子を保護するためX線遮蔽フィルタによってX線を遮蔽すると、パッケージ裏面のX線透過画像が得られないため不良チェックを行うことができないという課題があった。   However, on the other hand, when there is an electrode on the back of the package, such as BGA (Ball Grid Array) and QFN (Quad Flatpack No Lead), etc., when checking the defect of the adhesive surface during solder mounting by X-ray transmission image In addition, if X-rays are shielded by an X-ray shielding filter to protect the element, there is a problem that an X-ray transmission image on the back surface of the package cannot be obtained, so that a defect check cannot be performed.

特開2006−202791号公報JP 2006-202791 A 特開2012−134642号公報JP 2012-134642 A

本発明は、上記課題に鑑みてなされたものであり、その目的は、素子の特性変動を回避および補正を行い、はんだボールなどの被検査物のX線透過による出来映え検査を可能とする電子装置を提供することにある。   The present invention has been made in view of the above-described problems, and an object of the present invention is to provide an electronic device that avoids and corrects variations in element characteristics and enables a work-inspection by X-ray transmission of an inspection object such as a solder ball. Is to provide.

請求項1に記載した発明によれば、電子装置(10)は、第1方向に第1面を、前記第1方向に対して反対方向の第2方向に第2面を備える回路基板(16)と、前記回路基板の前記第1面に設けられるICチップ(12)と、前記回路基板の前記第2面に設けられる被検査物(24)と、前記ICチップに配置された基準回路(14)と、前記ICチップに配置された前記基準回路以外の回路(30)と、前記基準回路の第1方向側を覆い、前記基準回路以外の回路の前記第1方向側を覆わない、X線を遮蔽可能な遮蔽物(26)と、を備える。   According to the invention described in claim 1, the electronic device (10) includes a circuit board (16) having a first surface in a first direction and a second surface in a second direction opposite to the first direction. ), An IC chip (12) provided on the first surface of the circuit board, an object to be inspected (24) provided on the second surface of the circuit board, and a reference circuit ( 14), a circuit (30) other than the reference circuit arranged on the IC chip, and a first direction side of the reference circuit, and a first direction side of the circuit other than the reference circuit is not covered, X And a shield (26) capable of shielding the line.

この構成によれば、X線遮蔽物の設置範囲を最小限とすることにより、はんだボールを配置しない領域を最小限とすることができる。また、X線透過画像によるはんだボールの出来映え検査の際に、遮蔽領域にはX線が照射されないため、この領域にはんだボールが存在する場合にはX線透過画像が得られないため検査ができない。しかし、本実施形態では、遮蔽領域には被検査物(はんだボール)が配置されていないため、X線透過画像によりはんだボールの出来映え検査ができないという事態を回避できる。また、基準回路にはX線の照射がされないため、基準回路に配置される回路素子の特性は変動しない。従って基準回路を用いて被調整回路の特性変動を補正することにより、基準回路によって調整信号を正しく発生させることができる。これにより、電子装置全体の正常な回路動作が確保できる。   According to this structure, the area | region which does not arrange | position a solder ball can be minimized by minimizing the installation range of an X-ray shield. In addition, when performing a solder ball performance inspection using an X-ray transmission image, the shielding area is not irradiated with X-rays. Therefore, if there is a solder ball in this area, an X-ray transmission image cannot be obtained and the inspection cannot be performed. . However, in this embodiment, since an object to be inspected (solder ball) is not arranged in the shielding area, it is possible to avoid a situation in which the inspection of the solder ball cannot be performed by the X-ray transmission image. Further, since the reference circuit is not irradiated with X-rays, the characteristics of the circuit elements arranged in the reference circuit do not change. Therefore, the correction signal can be correctly generated by the reference circuit by correcting the characteristic variation of the circuit to be adjusted using the reference circuit. Thereby, normal circuit operation of the whole electronic device can be secured.

第1実施形態に係る電子装置の概略構成を示す上面図1 is a top view illustrating a schematic configuration of an electronic device according to a first embodiment. 第1実施形態に係る電子装置の概略構成を示す縦断面図1 is a longitudinal sectional view showing a schematic configuration of an electronic device according to a first embodiment. 第1実施形態に係る電子装置の概略構成を示す下面図1 is a bottom view showing a schematic configuration of an electronic device according to a first embodiment. シールドの概略構成例を示す図Diagram showing a schematic configuration example of the shield シールドの概略構成例を示す図Diagram showing a schematic configuration example of the shield シールドの概略構成例を示す図Diagram showing a schematic configuration example of the shield シールドの概略構成例を示す図Diagram showing a schematic configuration example of the shield 電子装置の電気的構成を模式的に示す概略平面図Schematic plan view schematically showing the electrical configuration of the electronic device 比較器および差異調整回路の概略構成例Schematic configuration example of comparator and difference adjustment circuit 比較器および差異調整回路の概略構成例Schematic configuration example of comparator and difference adjustment circuit 調整回路の概略構成例Example of schematic configuration of adjustment circuit 調整回路の概略構成例Example of schematic configuration of adjustment circuit 第2実施形態に係る電子装置の概略構成を示す上面図The top view showing the schematic structure of the electronic device concerning a 2nd embodiment. 第2実施形態に係る電子装置の概略構成を示す縦断面図A longitudinal sectional view showing a schematic configuration of an electronic device according to a second embodiment 第2実施形態に係る電子装置の概略構成を示す下面図The bottom view which shows schematic structure of the electronic device which concerns on 2nd Embodiment.

以下、本発明の複数の実施形態について図面を参照して説明する。なお、以下に示す各実施形態において、共通乃至関連する要素又は実質的に同一の要素には同一の符号を付し、説明を省略する。また、以下の説明において、「X線が照射されない」、という場合には、X線が完全に遮蔽される場合だけでなく、X線による影響をうけない程度すなわち素子の特性変動が起こらないレベルまでにX線が減衰されて照射されている場合を含むものとする。   Hereinafter, a plurality of embodiments of the present invention will be described with reference to the drawings. In the following embodiments, common or related elements or substantially the same elements are denoted by the same reference numerals, and description thereof is omitted. Further, in the following description, when “X-rays are not irradiated”, not only when the X-rays are completely shielded but also at a level at which the influence of the X-rays is not affected, that is, the element characteristics do not change. This includes the case where X-rays have been attenuated and irradiated.

(第1の実施形態)
図1から図3は、第1実施形態に係る電子装置10の概略構成を示す図であり、図1は平面図、図2は図1のAA線に沿う部分の縦断面図、図3は裏面図である。図1から図3に示すように、電子装置10は、ICチップ12、回路基板16、封止樹脂18、はんだボール24、及びシールド26を備えている。
(First embodiment)
1 to 3 are diagrams showing a schematic configuration of the electronic device 10 according to the first embodiment. FIG. 1 is a plan view, FIG. 2 is a longitudinal sectional view of a portion along the line AA in FIG. It is a back view. As shown in FIGS. 1 to 3, the electronic device 10 includes an IC chip 12, a circuit board 16, a sealing resin 18, solder balls 24, and a shield 26.

電子装置10は所謂ICパッケージであり、図2に示すように、ICチップ12が、回路基板16のチップ搭載面すなわち図において上面側(第1面)に固定されている。回路基板16のチップ搭載面の裏面側すなわちチップ搭載面側の反対側(第2面)には、図示しない電極が設けられており、この電極に外部接続用の複数のはんだボール24が接続形成されている。回路基板16は、樹脂やセラミックスを主原料とする絶縁基材に、銅などの導電材料からなる配線を配置して構成されている。   The electronic device 10 is a so-called IC package. As shown in FIG. 2, the IC chip 12 is fixed to the chip mounting surface of the circuit board 16, that is, the upper surface side (first surface) in the drawing. An electrode (not shown) is provided on the back side of the chip mounting surface of the circuit board 16, that is, on the opposite side (second surface) of the chip mounting surface, and a plurality of solder balls 24 for external connection are formed on this electrode. Has been. The circuit board 16 is configured by arranging wiring made of a conductive material such as copper on an insulating base material mainly made of resin or ceramics.

ICチップ12は、シリコンなどの半導体基板に、トランジスタ、ダイオード、抵抗、コンデンサなどの素子が集積され、論理回路、記憶回路、A/D変換回路、増幅回路、或いはこれらの混合回路等の回路(大規模集積回路)が構成され、チップ化されたものである。本実施形態では、平面略矩形状のICチップ12が、回路基板16のチップ搭載面に接着固定されている。   The IC chip 12 includes elements such as transistors, diodes, resistors, and capacitors integrated on a semiconductor substrate such as silicon, and a circuit such as a logic circuit, a memory circuit, an A / D conversion circuit, an amplifier circuit, or a mixed circuit thereof ( A large-scale integrated circuit) is configured and formed into a chip. In the present embodiment, the IC chip 12 having a substantially planar shape is bonded and fixed to the chip mounting surface of the circuit board 16.

ICチップ12上には、基準回路14、その他の被調整回路30a、30b、30c、30d(以下まとめて被調整回路30と称する)が形成されている。本実施形態では、基準回路14は、基準回路14以外の被調整回路30の特性変動を調整するために用いられる回路素子を含むもの、及び、X線の照射により回路素子の特性変動が生じた場合に、その特性変動を補正しても期待される機能を回復しない回路素子を含むものである。基準回路14は、X線照射により特性変動が生じると電子装置10の全体の性能に影響する部分、例えばメモリ、基準電源などを意味する。具体的には、後述する比較器32、メモリ34、基準電源回路36、差異調整回路38などが含まれる。   On the IC chip 12, a reference circuit 14 and other adjusted circuits 30a, 30b, 30c, and 30d (hereinafter collectively referred to as the adjusted circuit 30) are formed. In the present embodiment, the reference circuit 14 includes a circuit element used for adjusting the characteristic variation of the circuit 30 to be adjusted other than the reference circuit 14, and the characteristic variation of the circuit element is caused by X-ray irradiation. In some cases, circuit elements that do not recover the expected function even if the characteristic variation is corrected are included. The reference circuit 14 refers to a portion that affects the overall performance of the electronic device 10 when a characteristic variation occurs due to X-ray irradiation, such as a memory or a reference power supply. Specifically, a comparator 32, a memory 34, a reference power supply circuit 36, a difference adjustment circuit 38, and the like, which will be described later, are included.

一方、被調整回路30は、基準回路14による特性変動の調整を受ける回路素子を含むもの、及び、X線の照射により回路素子の特性変動が生じた場合に、その特性変動を補正しなくても期待される回路機能を発揮する回路素子、又はその特性変動を補正すれば期待される回路機能を回復する回路素子を含むものである。被調整回路30は、X線照射により特性変動が生じても電子装置10全体の性能に影響しにくい、あるいは特性変動が調整可能な回路、例えば制御ロジック、ON/OFFドライバ、COMP閾値、FBゲインなどを意味する。   On the other hand, the circuit 30 to be adjusted includes a circuit element that is subjected to adjustment of the characteristic variation by the reference circuit 14 and when the characteristic variation of the circuit element occurs due to the X-ray irradiation, the characteristic variation is not corrected. The circuit element that exhibits the expected circuit function, or the circuit element that recovers the expected circuit function by correcting its characteristic variation. The circuit 30 to be adjusted is a circuit that is unlikely to affect the overall performance of the electronic apparatus 10 even if characteristic variation occurs due to X-ray irradiation, or a circuit that can adjust the characteristic variation, for example, control logic, ON / OFF driver, COMP threshold value, FB gain. Means.

基準回路14の上方には、基準回路14の上面側を覆うようにしてシールド26が形成されている。シールド26は被調整回路30の上面側を覆っていない。シールド26の下方向に投影した領域すなわち遮蔽領域28に基準回路14が含まれる。シールド26は、X線を吸収、反射もしくは減衰することにより遮蔽可能な機能を備えている。シールド26の構成材料としては、例えば、Al、Cu、W、Ag、Ti、Sn、Pb、Ta、Mo、Ge、Bi、Pt又はZn等の金属材料やこれらの金属を含む合金、あるいは、Mo/Siを用いた多層膜、シリコン窒化膜(Si)等を用いることができる。ここで、シールド26の図において垂直下方向に投影した領域を、遮蔽領域28とする。なお、「遮蔽」には、X線を吸収することによって遮蔽する場合だけでなく、X線を反射もしくは散乱させることも含み、また、X線の強度を素子特性の変動を回避可能なレベルまで減衰させることも含む。 A shield 26 is formed above the reference circuit 14 so as to cover the upper surface side of the reference circuit 14. The shield 26 does not cover the upper surface side of the circuit 30 to be adjusted. The reference circuit 14 is included in a region projected downward of the shield 26, that is, a shielding region 28. The shield 26 has a function capable of shielding by absorbing, reflecting, or attenuating X-rays. Examples of the constituent material of the shield 26 include metal materials such as Al, Cu, W, Ag, Ti, Sn, Pb, Ta, Mo, Ge, Bi, Pt, and Zn, alloys containing these metals, or Mo. A multilayer film using / Si, a silicon nitride film (Si 3 N 4 ), or the like can be used. Here, a region projected vertically downward in the drawing of the shield 26 is defined as a shielding region 28. Note that “shielding” includes not only shielding by absorbing X-rays but also reflecting or scattering X-rays, and the X-ray intensity is reduced to a level at which variations in element characteristics can be avoided. Including attenuation.

回路基板16は、樹脂やセラミックスを主原料とする絶縁基材に、銅などの導電材料からなる配線を多層に配置して構成されている。回路基板16のチップ搭載面には図示しない複数のランドが形成されており、これらランドは、ICチップ12上の図示しない電極パッドとボンディングワイヤ22によって電気的に接続されている。   The circuit board 16 is configured by arranging wirings made of a conductive material such as copper in multiple layers on an insulating base material mainly made of resin or ceramics. A plurality of lands (not shown) are formed on the chip mounting surface of the circuit board 16, and these lands are electrically connected to electrode pads (not shown) on the IC chip 12 by bonding wires 22.

回路基板16の裏面には、遮蔽領域28を除き、はんだボール24が格子状すなわちマトリクス状に形成されている。すなわち、はんだボール24は遮蔽領域28には配置されていない。はんだボール24は、回路基板16に形成された図示しない配線を介して、チップ搭載面に形成されたランドと電気的に接続されており、ICチップ12に構成された回路と電気的に接続された、電気的な接続機能を提供する。はんだボール24としては、例えば、Sn−Ag系、Sn−Ag−Cu系、Sn−Zn−Bi系、Sn−Cu系、等の組成のはんだ材を用いることができる。はんだボール24は球状すなわちボール状に形成されている。このように、電子装置10はBGA(Ball Grid Array)型パッケージとなっている。   On the back surface of the circuit board 16, the solder balls 24 are formed in a lattice shape, that is, a matrix shape, except for the shielding region 28. That is, the solder ball 24 is not disposed in the shielding region 28. The solder ball 24 is electrically connected to a land formed on the chip mounting surface via a wiring (not shown) formed on the circuit board 16 and is electrically connected to a circuit formed on the IC chip 12. Provide electrical connection function. As the solder ball 24, for example, a solder material having a composition such as Sn—Ag, Sn—Ag—Cu, Sn—Zn—Bi, or Sn—Cu can be used. The solder ball 24 is formed in a spherical shape, that is, a ball shape. Thus, the electronic device 10 is a BGA (Ball Grid Array) type package.

本実施形態では、基準回路14のみを遮蔽してX線の被爆から保護するようにシールド26を設けることで、X線の遮蔽領域28を最小限としている。さらに遮蔽領域28には、はんだボール24を配置しないようにしている。これによって、はんだボール24を配置可能な領域を増加させるとともに、はんだボール24のX線透過画像による出来映え検査を可能としている。   In the present embodiment, the shield region 28 is provided so as to shield only the reference circuit 14 and protect it from X-ray exposure, thereby minimizing the X-ray shielding region 28. Further, the solder ball 24 is not disposed in the shielding region 28. As a result, the area where the solder balls 24 can be arranged is increased, and a workmanship inspection using an X-ray transmission image of the solder balls 24 is made possible.

ICチップ12の上面はボンディングワイヤ22およびシールド26を含めて封止樹脂18により覆われて封止されている。封止樹脂18の構成材料としては、フェノール系硬化剤やシリコーンゴム及びフィラーが添加されたエポキシ系樹脂等の材料を用いることができる。   The upper surface of the IC chip 12 is covered and sealed with the sealing resin 18 including the bonding wires 22 and the shield 26. As a constituent material of the sealing resin 18, a material such as an epoxy resin to which a phenolic curing agent, silicone rubber, and a filler are added can be used.

次に、シールド26の形成方法について図4から図7を用いて説明する。
図4は、シールド26を、ICチップ12に使用される多層配線のうち、1層目の配線層42aを回路配線として用い、2層目及び3層目の配線層42b、42cを積層させて基準回路14上に配置するようにして構成し、シールド26としたものである。
Next, a method for forming the shield 26 will be described with reference to FIGS.
4 shows that the shield 26 is formed by stacking the second and third wiring layers 42b and 42c using the first wiring layer 42a as the circuit wiring among the multilayer wirings used in the IC chip 12. FIG. The shield 26 is configured to be arranged on the reference circuit 14.

図5に示すものは、さらにシールド26形成用の第4層目の配線層42dを設けて基準回路14上に配置するようにして構成し、シールド26としたものである。この場合は、独自の膜厚を設定することができ、膜厚を厚く形成することもできる。   FIG. 5 shows a shield 26 that is configured by further providing a fourth wiring layer 42 d for forming the shield 26 and disposing it on the reference circuit 14. In this case, a unique film thickness can be set and the film thickness can be increased.

図6に示すものは、ICチップ12上にさらにICチップ12aを配置したCoC(Chip on Chip)構造であって、基準回路14上にICチップ12aを配置したものである。ICチップ12aにはその上部に配線層42が設けられており、さらのその上部に金属層によって形成されたシールド26が設けられている。配線層42とシールド層26との間には図示しない絶縁層が設けられている。この場合はICチップ12a、配線層42及びシールド26がX線遮蔽物として機能しており、シールド26だけでなくICチップ12a及び配線層42が存在することにより遮蔽効果が向上する。   FIG. 6 shows a CoC (Chip on Chip) structure in which an IC chip 12 a is further arranged on the IC chip 12, and the IC chip 12 a is arranged on the reference circuit 14. The IC chip 12a is provided with a wiring layer 42 on its upper part, and further on its upper part is provided with a shield 26 formed of a metal layer. An insulating layer (not shown) is provided between the wiring layer 42 and the shield layer 26. In this case, the IC chip 12a, the wiring layer 42, and the shield 26 function as an X-ray shield, and the shielding effect is improved by the presence of the IC chip 12a and the wiring layer 42 as well as the shield 26.

図7に示すものは、基準回路14上に配線層42及び、金属皮膜によって形成したシールド26が形成されているものである。配線層42とシールド層26との間には図示しない絶縁層が設けられている。この場合、シールド26としては、例えば銀ペーストなどの塗布膜によって形成された金属皮膜や、FIB(Focused Ion Beam)による局所成膜を用いて形成された金属皮膜、又は、はんだ印刷によって形成された金属皮膜を用いることができる。   In FIG. 7, a wiring layer 42 and a shield 26 formed of a metal film are formed on the reference circuit 14. An insulating layer (not shown) is provided between the wiring layer 42 and the shield layer 26. In this case, the shield 26 is formed by, for example, a metal film formed by a coating film such as silver paste, a metal film formed by local film formation by FIB (Focused Ion Beam), or solder printing. A metal film can be used.

図8は実施形態に係る電子装置10の電気的構成を模式的に示す概略平面図である。ICチップ12は比較器32、メモリ34、基準電源回路36、差異調整回路38を備えており、これらは基準回路14を構成している、基準回路14はシールド26によって覆われておりX線遮蔽されている。従って基準回路14にはX線が照射されない。   FIG. 8 is a schematic plan view schematically showing an electrical configuration of the electronic device 10 according to the embodiment. The IC chip 12 includes a comparator 32, a memory 34, a reference power supply circuit 36, and a difference adjustment circuit 38, which constitute the reference circuit 14. The reference circuit 14 is covered by a shield 26 and is shielded from X-rays. Has been. Therefore, the reference circuit 14 is not irradiated with X-rays.

ICチップ12は被調整回路30a、30b、30c、調整回路40a、40b、40cを備えている。これら被調整回路30は、シールド26によって覆われていないため、X線の照射を受けて回路特性が変動をきたしうる回路である。調整回路40はこれら被調整回路30の特性を調整するための回路であり、基準回路14からの調整信号を入力可能に接続されている。   The IC chip 12 includes adjusted circuits 30a, 30b, and 30c and adjusting circuits 40a, 40b, and 40c. Since the circuit to be adjusted 30 is not covered with the shield 26, the circuit characteristics may be changed by being irradiated with X-rays. The adjustment circuit 40 is a circuit for adjusting the characteristics of the circuit to be adjusted 30 and is connected so that an adjustment signal from the reference circuit 14 can be input.

基準回路14は、調整回路40に調整信号を生成して各調整回路40に出力することにより被調整回路30の特性調整を行う。比較器32は被調整回路30の変動前の特性と、変動後の特性を比較する。被調整回路30の変動前の特性すなわち初期特性はメモリ34に保存されており、比較器32は被調整回路30の初期特性をメモリ34から呼び出して比較に用いる。基準電源回路36は基準となる内部電圧を発生させるための回路であり、同じく、被調整回路30のX線照射後の特性と初期特性とを比較するために用いられる。   The reference circuit 14 adjusts the characteristics of the circuit to be adjusted 30 by generating an adjustment signal to the adjustment circuit 40 and outputting the adjustment signal to each adjustment circuit 40. The comparator 32 compares the characteristic before the change of the adjusted circuit 30 with the characteristic after the change. The characteristic before the change of the adjusted circuit 30, that is, the initial characteristic is stored in the memory 34, and the comparator 32 calls the initial characteristic of the adjusted circuit 30 from the memory 34 and uses it for comparison. The reference power supply circuit 36 is a circuit for generating a reference internal voltage, and is also used for comparing the characteristics after the X-ray irradiation of the adjusted circuit 30 with the initial characteristics.

差異調整回路38は比較器32による素子特性の比較結果の入力を受け、被調整回路30の初期特性からの変動を判定し、この初期特性からの変動分を補正する調整信号を生成し、調整回路40に出力する判定制御部として機能する。調整回路40は入力された調整信号に基づいて、各被調整回路30の素子特性を補正する。この補正された素子特性は、再度、比較器32と差異調整回路38により初期特性との差分が判定され、差分が所定の値以下になった場合は調整が終了する。   The difference adjustment circuit 38 receives the comparison result of the element characteristics from the comparator 32, determines a variation from the initial characteristic of the circuit 30 to be adjusted, generates an adjustment signal for correcting the variation from the initial characteristic, and adjusts the difference. It functions as a determination control unit that outputs to the circuit 40. The adjustment circuit 40 corrects the element characteristics of each circuit to be adjusted 30 based on the input adjustment signal. The difference between the corrected element characteristic and the initial characteristic is determined again by the comparator 32 and the difference adjustment circuit 38, and the adjustment is finished when the difference is equal to or less than a predetermined value.

図9および図10に比較器32および差異調整回路38の構成例を示す。図9に示す構成は、比較器32および差異調整回路38をアナログ回路により構成した例であり、基準電源回路36からの基準電源電圧と被調整回路30からの信号すなわちアナログ値を比較器32によって比較し、差異調整回路38によって差分に対応した調整信号を調整回路40に出力する。   9 and 10 show configuration examples of the comparator 32 and the difference adjustment circuit 38. FIG. The configuration shown in FIG. 9 is an example in which the comparator 32 and the difference adjustment circuit 38 are configured by analog circuits, and the reference power supply voltage from the reference power supply circuit 36 and the signal from the circuit to be adjusted 30, that is, the analog value, are output by the comparator 32. The difference adjustment circuit 38 outputs an adjustment signal corresponding to the difference to the adjustment circuit 40.

図10に示す構成は、比較器32および差異調整回路38をデジタル回路により構成した例であり、メモリ34からの初期特性と被調整回路30からの信号をA/D変換回路33によりA/D変換したものを、差異調整回路によって比較し、差分に対応した調整信号を生成して調整回路40に出力する。この場合は、差異調整回路38は比較器32も兼ねている。   The configuration shown in FIG. 10 is an example in which the comparator 32 and the difference adjustment circuit 38 are configured by digital circuits, and the initial characteristics from the memory 34 and the signal from the circuit to be adjusted 30 are converted into A / D by the A / D conversion circuit 33. The converted signals are compared by the difference adjustment circuit, and an adjustment signal corresponding to the difference is generated and output to the adjustment circuit 40. In this case, the difference adjustment circuit 38 also serves as the comparator 32.

図11および図12に調整回路40の構成例を示す。図11に示す調整回路40は、直列に複数段の抵抗を備え各々の抵抗に対して並列にスイッチを設けた構成を備えている。差異調整回路38によって各スイッチを切り替えることにより、調整回路40の出力値が調整される。図12に示す調整回路40は、直列に複数段の抵抗を備え、各々の抵抗間と出力線との間を接続し、その途中にスイッチを備える接続線により構成される。差異調整回路38によって各スイッチを切り替えることにより調整回路40の出力値が調整される。   11 and 12 show a configuration example of the adjustment circuit 40. FIG. The adjustment circuit 40 shown in FIG. 11 has a configuration in which a plurality of stages of resistors are provided in series and a switch is provided in parallel with each resistor. By switching each switch by the difference adjustment circuit 38, the output value of the adjustment circuit 40 is adjusted. The adjustment circuit 40 illustrated in FIG. 12 includes a plurality of stages of resistors in series, and includes a connection line that connects between each resistor and an output line, and includes a switch in the middle. The output value of the adjustment circuit 40 is adjusted by switching each switch by the difference adjustment circuit 38.

上記構成によれば、シールド26は基準回路14の上方のみを覆うようにして配置されるため、X線の遮蔽物の設置範囲を最小限とすることができる。これにより、はんだボール24を配置しない領域を最小限とすることができる。また、X線透過画像の解析によって電子装置10裏面に配置されたはんだボール24の出来映え検査を行う際に、基準回路14はシールド26により遮蔽されているためX線の照射がされない。この場合、X線は図2において矢印にて図示するように、上方から垂直に下方に向かって照射される。また、遮蔽領域28には、はんだボール24が配置されていない。以上から、遮蔽領域28にはX線が照射されないためX線透過画像が得られないが、遮蔽領域28には、はんだボール24すなわち被検査物が配置されていないため、X線透過画像により出来映え検査ができないという事態を回避できる。従って、はんだボール24の出来映え検査ができない領域が生じない。また、基準回路14にはX線の照射がされないため、基準回路14に配置される回路素子の特性は変動しない。従って基準回路14を用いて被調整回路30の特性変動を補正する調整信号を正しく発生させることができる。これにより、電子装置10全体の正常な回路動作が確保できる。   According to the above configuration, the shield 26 is disposed so as to cover only the upper part of the reference circuit 14, so that the installation range of the X-ray shield can be minimized. Thereby, the area | region which does not arrange | position the solder ball 24 can be minimized. In addition, when the workmanship inspection of the solder ball 24 arranged on the back surface of the electronic device 10 is performed by analysis of the X-ray transmission image, the reference circuit 14 is shielded by the shield 26 and thus is not irradiated with X-rays. In this case, X-rays are irradiated vertically downward from above as shown by arrows in FIG. Further, the solder ball 24 is not disposed in the shielding region 28. From the above, an X-ray transmission image cannot be obtained because the shielding area 28 is not irradiated with X-rays. However, since the solder ball 24, that is, the inspection object is not arranged in the shielding area 28, the X-ray transmission image can be obtained. It is possible to avoid the situation where inspection is not possible. Accordingly, there is no region where the inspection of the solder ball 24 cannot be performed. Further, since the reference circuit 14 is not irradiated with X-rays, the characteristics of the circuit elements arranged in the reference circuit 14 do not change. Therefore, it is possible to correctly generate the adjustment signal for correcting the characteristic variation of the circuit to be adjusted 30 using the reference circuit 14. As a result, normal circuit operation of the entire electronic device 10 can be ensured.

(第2実施形態)
次に第2実施形態について図13から図15を参照して説明する。第2実施形態に係る電子装置10が、第1実施形態と異なる点は、シールド26による遮蔽領域28が、電子装置10の端部に配置されている点である。図に示すように、電子装置10端部に配置された遮蔽領域28に、はんだボール24が配置されている例を示しているが、第1実施形態と同様に、遮蔽領域28に、はんだボール24を配置しないように構成してもよい。なお、第2実施形態に係る電子装置10においてはボンディングワイヤ22に代えて貫通電極23によりICチップ12とはんだボール24を電気的に接続している。
(Second Embodiment)
Next, a second embodiment will be described with reference to FIGS. The electronic device 10 according to the second embodiment is different from the first embodiment in that a shielding region 28 by the shield 26 is disposed at an end portion of the electronic device 10. As shown in the figure, an example in which the solder ball 24 is arranged in the shielding area 28 arranged at the end of the electronic device 10 is shown, but the solder ball 24 is arranged in the shielding area 28 as in the first embodiment. You may comprise so that 24 may not be arrange | positioned. In the electronic device 10 according to the second embodiment, the IC chip 12 and the solder ball 24 are electrically connected by the through electrode 23 instead of the bonding wire 22.

第2実施形態によれば第1実施形態と同様の効果を得る。また、シールド26すなわち遮蔽領域28が電子装置10の端部に配置されているため、遮蔽領域28にはんだボール24を配置しても、目視によりはんだボール24の出来映え検査が可能である。また、目視によらなくても、光学的画像処理、あるいはレーザ照射による反射散乱光の解析等によりはんだボール24の出来映え検査をしてもよい。また、第1実施形態と同様に、遮蔽領域28にはんだボール24を配置しない構成とした場合は、X線が遮蔽された遮蔽領域28にはんだボール24が存在しないため、X線透過画像により出来映え検査ができないという事態を回避できる。
(その他の実施形態)
図2又は図4に示すように、シールド26は、図において封止樹脂18内のICチップ12の上方に配置されている例を示して説明したが、これに限定されるものではない。例えば、電子装置10の封止樹脂18の上面に配置してもよい。また、ICチップ12の下方や、電子装置10の裏面に配置してもよいし、上方および下方の両方に配置してもよい。シールド26をICチップ12の下方に配置した場合には、下方からのX線照射に対しても、ICチップ12を遮蔽可能となる。
According to the second embodiment, the same effect as the first embodiment is obtained. In addition, since the shield 26, that is, the shielding area 28 is disposed at the end of the electronic device 10, even if the solder ball 24 is disposed in the shielding area 28, it is possible to visually inspect the workmanship of the solder ball 24. Further, the workmanship inspection of the solder ball 24 may be performed by optical image processing, analysis of reflected / scattered light by laser irradiation, or the like without using visual observation. Similarly to the first embodiment, when the solder ball 24 is not disposed in the shielding region 28, the solder ball 24 does not exist in the shielding region 28 where the X-ray is shielded, so that the result is obtained by the X-ray transmission image. It is possible to avoid the situation where inspection is not possible.
(Other embodiments)
As shown in FIG. 2 or FIG. 4, the shield 26 has been described with reference to the example in which the shield 26 is disposed above the IC chip 12 in the sealing resin 18 in the figure, but is not limited thereto. For example, the electronic device 10 may be disposed on the upper surface of the sealing resin 18. Moreover, you may arrange | position to the downward direction of the IC chip 12, and the back surface of the electronic apparatus 10, and may be arrange | positioned both above and below. When the shield 26 is disposed below the IC chip 12, the IC chip 12 can be shielded against X-ray irradiation from below.

また、BGAパッケージを例示して説明したが、これに限定されるものではない。例えば、QFNパッケージ、LGA(Land grid array)パッケージ、又はSON(Small-Outline No Lead)パッケージ等、電子装置10の裏面に電極が配置されている製品全般に適用することができる。   Further, although the BGA package has been described as an example, the present invention is not limited to this. For example, the present invention can be applied to all products in which electrodes are arranged on the back surface of the electronic device 10, such as a QFN package, an LGA (Land grid array) package, or a SON (Small-Outline No Lead) package.

本開示は、実施例に準拠して記述されたが、本開示は当該実施例や構造に限定されるものではないと理解される。本開示は、様々な変形例や均等範囲内の変形をも包含する。加えて、様々な組み合わせや形態、さらには、それらに一要素のみ、それ以上、あるいはそれ以下、を含む他の組み合わせや形態をも、本開示の範疇や思想範囲に入るものである。   Although the present disclosure has been described with reference to the embodiments, it is understood that the present disclosure is not limited to the embodiments and structures. The present disclosure includes various modifications and modifications within the equivalent range. In addition, various combinations and forms, as well as other combinations and forms including only one element, more or less, are within the scope and spirit of the present disclosure.

10…電子装置、12…ICチップ、14…基準回路、24…はんだボール(被検査物)、26…シールド(遮蔽物)、28…遮蔽領域、30、30a、30b、30c、30d…被調整回路、32…比較器(比較部)、34…メモリ(記憶部)、36…基準電源回路、38…差異調整回路(判定制御部)、40、40a、40b、40c…調整回路   DESCRIPTION OF SYMBOLS 10 ... Electronic device, 12 ... IC chip, 14 ... Standard circuit, 24 ... Solder ball (inspection object), 26 ... Shield (shielding object), 28 ... Shielding area, 30, 30a, 30b, 30c, 30d ... Circuit 32... Comparator (comparator) 34. Memory (storage unit) 36. Reference power supply circuit 38. Difference adjustment circuit (determination control unit) 40, 40 a, 40 b, 40 c.

Claims (10)

第1方向に第1面を、前記第1方向に対して反対方向の第2方向に第2面を備える回路基板(16)と、
前記回路基板の前記第1面に設けられるICチップ(12)と、
前記回路基板の前記第2面に設けられる被検査物(24)と、
前記ICチップに配置された基準回路(14)と、
前記ICチップに配置された前記基準回路以外の回路(30、30a、30b、30c、30d)と、
前記基準回路の第1方向側を覆い、前記基準回路以外の回路の前記第1方向側を覆わない、X線を遮蔽可能な遮蔽物(26)と、を備える電子装置(10)。
A circuit board (16) comprising a first surface in a first direction and a second surface in a second direction opposite to the first direction;
An IC chip (12) provided on the first surface of the circuit board;
A test object (24) provided on the second surface of the circuit board;
A reference circuit (14) disposed on the IC chip;
Circuits other than the reference circuit (30, 30a, 30b, 30c, 30d) arranged on the IC chip,
An electronic device (10) comprising: a shield (26) capable of shielding X-rays that covers the first direction side of the reference circuit and does not cover the first direction side of circuits other than the reference circuit.
前記遮蔽物を第2方向に投影した領域である遮蔽領域(28)には前記被検査物が配置されない請求項1に記載の電子装置。   2. The electronic device according to claim 1, wherein the object to be inspected is not arranged in a shielding area (28) that is an area in which the shielding object is projected in the second direction. 前記遮蔽領域は、前記回路基板の端部に位置する請求項1又は2に記載の電子装置。   The electronic device according to claim 1, wherein the shielding region is located at an end portion of the circuit board. 前記基準回路は、前記基準回路以外の回路の特性変動を調整するために用いられる回路(32、34、36、38)を含む請求項1から3のいずれか一項に記載の電子装置10。   4. The electronic device 10 according to claim 1, wherein the reference circuit includes a circuit (32, 34, 36, 38) used for adjusting a characteristic variation of a circuit other than the reference circuit. 5. 前記基準回路は、X線の照射により特性変動が生じた場合に、当該特性変動を補正しても期待される機能を回復しない回路(32、34、36、38)を含む請求項1から4のいずれか一項に記載の電子装置。   5. The circuit according to claim 1, wherein the reference circuit includes a circuit (32, 34, 36, 38) that does not recover the expected function even when the characteristic variation occurs due to the X-ray irradiation. The electronic device according to any one of the above. 前記遮蔽物は金属又は合金を含む請求項1から5のいずれか一項に記載の電子装置。   The electronic device according to claim 1, wherein the shield includes a metal or an alloy. 前記金属又は合金は少なくともAl、Cu、W、Ag、Ti、Sn、Pb、Ta、Mo、Ge、Bi、Zn、Mo及びPtのいずれかを含む請求項6に記載の電子装置。   The electronic device according to claim 6, wherein the metal or alloy includes at least one of Al, Cu, W, Ag, Ti, Sn, Pb, Ta, Mo, Ge, Bi, Zn, Mo, and Pt. 前記基準回路は、前記基準回路以外の回路の初期特性を記憶する記憶部(34)と、前記基準回路以外の回路の変動後の特性と初期特性を比較する比較部(32)と、前記比較部での結果を判定して調整信号を生成する判定制御部(38)と、を備える請求項1から7のいずれか一項に記載の電子装置。   The reference circuit includes a storage unit (34) that stores initial characteristics of circuits other than the reference circuit, a comparison unit (32) that compares initial characteristics and characteristics after variation of circuits other than the reference circuit, and the comparison An electronic device according to any one of claims 1 to 7, further comprising: a determination control unit (38) that determines a result of the unit and generates an adjustment signal. 前記判定制御部で生成された調整信号が入力され、入力された調整信号に基づき前記基準回路以外の回路の特性変動を調整する調整回路(40、40a、40b、40c)を備える請求項8に記載の電子装置。   The adjustment signal (40, 40a, 40b, 40c) which adjusts the characteristic variation of circuits other than the above-mentioned reference circuit based on the inputted adjustment signal is inputted into the adjustment signal generated by the judgment control part. The electronic device described. 前記被検査物は、はんだボール(24)である請求項1から9に記載の電子装置。   The electronic device according to claim 1, wherein the object to be inspected is a solder ball (24).
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CN114687202B (en) * 2022-04-20 2023-07-11 西安工程大学 X-ray-proof shielding fabric and preparation method and application thereof

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