JP2012209432A - Semiconductor device built-in substrate module and mounting structure of the same, and method of manufacturing semiconductor device built-in substrate module - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a semiconductor device built-in substrate module and a mounting structure of the same, and a method of manufacturing the semiconductor device built-in substrate module capable of reducing a plane size of the substrate module and achieving good circuit characteristics even when providing a configuration conducting between wiring layers or electrodes provided on an upper surface side and a lower surface side of a semiconductor chip, in a substrate module incorporating the semiconductor chip.SOLUTION: In a semiconductor device built-in substrate module 10, a semiconductor device 20 is embedded in an opening 11h provided to a core substrate 11, and lamination wires are provided on an upper surface side and a lower surface side of the core substrate 11. The semiconductor device 20 has: an integrated circuit formed on an upper surface of a silicon substrate 21; wiring layers 25a and 25b, columnar electrodes 26a and 26b for external connection, and first and second sealing layers 27a and 27b provided on the upper surface side and a lower surface side of the silicon substrate 21; and a through electrode 22c conducting between the upper surface side and the lower surface side of the silicon substrate 21, and connected to the wiring layers 25a and 25b.

Description

  The present invention relates to a semiconductor device built-in substrate module, a mounting structure of the semiconductor device built-in substrate module on a circuit board, and a method of manufacturing the semiconductor device built-in substrate module.

  In recent years, portable electronic devices such as cellular phones, portable information terminals, digital cameras, and multimedia players have been widely used. In portable electronic devices, market demands for miniaturization and higher functionality are high, and high-density mounting technology for semiconductor devices mounted on electronic devices plays an important role in order to meet such demands.

  Conventionally, as an example of a semiconductor device to which a high-density mounting technology is applied, a configuration in which a semiconductor chip is sandwiched between a pair of core substrates or a configuration in which an opening provided in the core substrate is embedded is known. In the semiconductor device having such a configuration, the terminal provided on the upper surface of the semiconductor chip is connected to an external connection provided on the upper or lower surface of the semiconductor device via a connection pad or a wiring layer outside the semiconductor chip. It has the structure connected to the electrode. Among such semiconductor devices, the former is described in Patent Document 1, for example. The latter will be described as a comparative example in an embodiment described later.

JP 2008-135781 A

  In the semiconductor device having the above-described configuration, the terminal on the upper surface of the semiconductor chip is connected to a predetermined wiring layer outside the semiconductor chip, an electrical connection member or a through hole that conducts the wiring layer on the upper surface side and the lower surface side of the semiconductor chip. Via, the external connection electrode provided on the upper or lower surface of the semiconductor device is connected. Here, since the electrical connection members and through holes that conduct the wiring layers on the upper surface side and the lower surface side of the semiconductor chip are provided around the semiconductor chip, there is a problem that the planar size of the semiconductor device is increased. It was. In the case of such a wiring structure, the wiring path from the terminal of the semiconductor chip to the external connection electrode provided on the upper surface or the lower surface of the semiconductor device may be complicated and the wiring length may be increased. Therefore, there has been a problem that the circuit characteristics are deteriorated due to signal delay or the like.

  Accordingly, in view of the above-described problems, the present invention is a case where a substrate module incorporating a semiconductor chip is provided with a configuration in which wiring layers and electrodes provided on the upper surface side and the lower surface side of the semiconductor chip are electrically connected. In addition, the planar size of the substrate module can be reduced, and a semiconductor device built-in substrate module capable of realizing good circuit characteristics, a mounting structure of the semiconductor device built-in substrate module on a circuit board, and It is an object of the present invention to provide a method for manufacturing the semiconductor device built-in substrate module.

A substrate module with a built-in semiconductor device according to the present invention,
An insulating substrate provided with an opening penetrating from the upper surface to the lower surface;
A semiconductor substrate provided with connection pads on the upper surface and the lower surface; a first connection electrode provided on the upper surface side of the semiconductor substrate so as to be connected to the connection pad on the upper surface; and a first connection electrode A first sealing layer provided so as to cover a peripheral side portion; a second connection electrode provided on a lower surface side of the semiconductor substrate so as to be connected to a connection pad on the lower surface; A second sealing layer provided so as to cover a peripheral side portion of the connection electrode, and a semiconductor device embedded in the opening of the insulating substrate;
A first wiring layer provided on the upper surface side of the semiconductor device so as to be connected to the first connection electrode of the semiconductor substrate;
A second wiring layer provided on the lower surface side of the semiconductor device so as to be connected to the second connection electrode of the semiconductor substrate;
It is characterized by providing.

The mounting structure of the semiconductor device built-in substrate module according to the present invention is as follows.
An insulating substrate provided with an opening penetrating from the upper surface to the lower surface;
A semiconductor substrate provided with connection pads on the upper surface and the lower surface; a first connection electrode provided on the upper surface side of the semiconductor substrate so as to be connected to the connection pad on the upper surface; and a first connection electrode A first sealing layer provided so as to cover a peripheral side portion; a second connection electrode provided on a lower surface side of the semiconductor substrate so as to be connected to a connection pad on the lower surface; A second sealing layer provided so as to cover a peripheral side portion of the connection electrode, and a semiconductor device embedded in the opening of the insulating substrate;
A first wiring layer provided on the upper surface side of the semiconductor device so as to be connected to the first connection electrode of the semiconductor substrate;
A semiconductor device built-in substrate module comprising: a second wiring layer provided on the lower surface side of the semiconductor device so as to be connected to the second connection electrode of the semiconductor substrate;
It is characterized by being bonded to a circuit board provided with connection pads.

A method for manufacturing a semiconductor device built-in substrate module according to the present invention includes:
Preparing an insulating substrate provided with an opening penetrating from the upper surface to the lower surface;
A semiconductor substrate provided with connection pads on the upper surface and the lower surface; a first connection electrode provided on the upper surface side of the semiconductor substrate so as to be connected to the connection pad on the upper surface; and a first connection electrode A first sealing layer provided so as to cover a peripheral side portion; a second connection electrode provided on a lower surface side of the semiconductor substrate so as to be connected to a connection pad on the lower surface; Embedding a semiconductor device having a second sealing layer provided so as to cover a peripheral side portion of the connection electrode in the opening of the insulating substrate;
A first wiring layer is formed on the upper surface side of the semiconductor device so as to be connected to the first connection electrode of the semiconductor substrate, and the second surface of the semiconductor substrate is formed on the lower surface side of the semiconductor device. Forming a second wiring layer so as to be connected to the connection electrode.

  According to the present invention, even if a substrate module incorporating a semiconductor chip is provided with a configuration in which wiring layers and electrodes provided on the upper surface side and the lower surface side of the semiconductor chip are electrically connected, the planar size of the substrate module Of the semiconductor device built-in substrate module capable of realizing good circuit characteristics, a mounting structure of the semiconductor device built-in substrate module on a circuit board, and the semiconductor device built-in substrate module A manufacturing method can be provided.

It is a schematic sectional drawing which shows one Embodiment of the board | substrate module with a built-in semiconductor device which concerns on this invention. 1 is a schematic plan view showing an embodiment of a semiconductor device applicable to a substrate module with a built-in semiconductor device according to the present invention. It is a schematic sectional drawing which shows the semiconductor device applicable to this embodiment. It is a schematic sectional drawing which shows an example of the mounting structure of the board | substrate module with a built-in semiconductor device which concerns on this embodiment. It is a schematic sectional drawing which shows an example of the semiconductor device laminated | stacked and mounted on the board | substrate module with a built-in semiconductor device which concerns on this embodiment. It is process sectional drawing (the 1) which shows an example of the manufacturing method of the board | substrate module with a built-in semiconductor device which concerns on this embodiment. It is process sectional drawing (the 2) which shows an example of the manufacturing method of the semiconductor device built-in substrate module which concerns on this embodiment. It is process sectional drawing (the 3) which shows an example of the manufacturing method of the semiconductor device built-in substrate module which concerns on this embodiment. It is process sectional drawing (the 4) which shows an example of the manufacturing method of the semiconductor device built-in substrate module which concerns on this embodiment. It is process sectional drawing (the 5) which shows an example of the manufacturing method of the semiconductor device built-in substrate module which concerns on this embodiment. It is process sectional drawing (the 6) which shows an example of the manufacturing method of the board | substrate module with a built-in semiconductor device which concerns on this embodiment. It is process sectional drawing (the 7) which shows an example of the manufacturing method of the semiconductor device built-in substrate module which concerns on this embodiment. It is a schematic sectional drawing which shows the comparative example of the semiconductor device built-in substrate module which concerns on this embodiment.

Hereinafter, a semiconductor device built-in substrate module according to the present invention, its mounting structure, and a semiconductor device built-in substrate module manufacturing method will be described in detail with reference to embodiments.
(Semiconductor device built-in substrate module)
First, a semiconductor device built-in substrate module according to the present invention will be described. In the present embodiment, a configuration including a semiconductor chip and a wiring layer, a columnar electrode, and a sealing layer provided on the semiconductor chip is defined as a “semiconductor device”. A specific configuration of the semiconductor device according to the present embodiment will be described in detail later.

FIG. 1 is a schematic cross-sectional view showing an embodiment of a substrate module with a built-in semiconductor device according to the present invention.
The semiconductor device built-in substrate module 10 according to the present embodiment has a configuration in which the semiconductor device 20 is embedded and embedded in an opening (cavity) 11h provided in the core substrate 11, for example, as shown in FIG. ing. Here, the semiconductor device 20 incorporated in the semiconductor device built-in substrate module 10 according to the present embodiment is a wafer level CSP (or wafer level package) which is a form of a so-called chip size package (CSP); It has a package structure called WLP).

  The semiconductor device 20 will be described in detail later. As a general rule, a silicon substrate (semiconductor substrate) 21 having an integrated circuit (not shown) formed on the upper surface (the upper surface in FIG. 1) and the silicon substrate 21 in the thickness direction ( A through electrode 22c that penetrates in the vertical direction in FIG. 1 and conducts between the upper surface side and the lower surface (lower surface in FIG. 1), and a wiring that is provided on the upper surface side and the lower surface side of the silicon substrate 21 and connected to the through electrode 22c Layers 25a and 25b and external connection columnar electrodes (first external connection electrode and second external connection electrode) 26a and 26b, and a first seal for sealing the upper surface side and the lower surface side of the silicon substrate 21 A stop layer 27a and a second sealing layer 27b. The dimension in the thickness direction of the semiconductor device 20 is set to be substantially the same as the dimension in the thickness direction of the core substrate 11. That is, with the semiconductor device 20 embedded in the opening 11h of the core substrate 11, the upper surface of the core substrate 11 and the upper surface of the semiconductor device 20 are substantially flush, and the lower surface of the core substrate 11 and the lower surface of the semiconductor device 20 are It is set to be substantially flush. Here, the opening 11h of the core substrate 11 is a through-hole penetrating from the upper surface to the lower surface of the core substrate 11 so as to penetrate the core substrate 11 in the thickness direction.

  For the core substrate 11, for example, a member (insulating substrate) called a prepreg made of a sheet-like insulating material obtained by impregnating glass fiber with an epoxy resin or the like is applied. A plurality of insulating layers (first insulating layers) 12a and 14a made of, for example, a prepreg are stacked on the upper surface (the upper surface in FIG. 1; the first surface) 11a of the core substrate 11. Wiring layers (first wiring layers) 13a and 15a having a predetermined wiring pattern are provided on the upper surfaces of the insulating layers 12a and 14a, and vias (first vias) penetrating the insulating layers 12a and 14a in the thickness direction. ) The wiring layers 13a and 15a are electrically connected to the wiring layers and electrodes on the lower layer side of the insulating layers 12a and 14a by 13va and 15va. Thus, the wiring layer provided on the upper surface side of the core substrate 11 has a stacked structure in which the insulating layer 12a, the wiring layer 13a, the insulating layer 14a, and the wiring layer 15a are stacked in this order from the semiconductor device 20 side. Yes. That is, the semiconductor device built-in substrate module 10 shown in FIG. 1 has a single-sided two-layer build-up substrate structure.

  Specifically, in the semiconductor device built-in substrate module 10 shown in FIG. 1, two insulating layers 12 a and 14 a are laminated on the upper surface 11 a side of the core substrate 11. The first layered wiring includes an insulating layer 12a laminated on the upper surface side of the core substrate 11 and the semiconductor device 20, a wiring layer 13a provided on the insulating layer 12a, and a wiring penetrating the insulating layer 12a. The layer 13a and the via 13va electrically connected to the end of the columnar electrode 26a exposed on the upper surface of the first sealing layer 27a of the semiconductor device 20 are provided. Further, the second layered wiring includes an insulating layer 14a stacked on the first insulating layer 12a and the wiring layer 13a, a wiring layer 15a provided on the insulating layer 14a, and an insulating layer 14a. And a via 15va electrically connected to the first wiring layer 13a. A protective insulating film 16a such as a solder resist is provided so as to cover the second insulating layer 14a which is the uppermost layer. The protective insulating film 16a is provided with an opening 16ha from which the upper surface of the second wiring layer 15a is exposed. An external connection solder ball 17 is connected to the wiring layer 15a exposed through the opening 16ha.

  In addition, a plurality of insulating layers (second insulating layers) 12b and 14b made of, for example, a prepreg are stacked on the lower surface (lower surface in FIG. 1; second surface) 11b side of the core substrate, similarly to the upper surface side. . Wiring layers (second wiring layers) 13b and 15b having a predetermined wiring pattern are provided on the lower surfaces of the insulating layers 12b and 14b, and vias (second vias) penetrating the insulating layers 12b and 14b in the thickness direction. ) The wiring layers 13b and 15b and the wiring layers and electrodes on the upper layer side of the insulating layers 12b and 14b are electrically connected by 13vb and 15vb. As described above, the wiring layer provided on the lower surface side of the core substrate 11 is also formed by laminating the insulating layer 12b, the wiring layer 13b, the insulating layer 14b, and the wiring layer 15b sequentially from the semiconductor device 20 side in the same manner as the wiring on the upper surface side. Has a laminated structure.

  Specifically, in the semiconductor device built-in substrate module 10 shown in FIG. 1, two insulating layers 12 b and 14 b are laminated on the lower surface 11 b side of the core substrate 11. The first layered wiring includes an insulating layer 12b stacked on the lower surface side of the core substrate 11 and the semiconductor device 20, and a wiring layer 13b provided on the insulating layer 12b (corresponding to the lower surface side in the drawing). And a via 13vb penetrating through the insulating layer 12b and electrically connected to the end of the columnar electrode 26b exposed on the lower surface of the second sealing layer 27b of the semiconductor device 20. . The second layered wiring includes an insulating layer 14b stacked on the first insulating layer 12b and the wiring layer 13b (corresponding to the lower surface side in the drawing) and the insulating layer 14b (in the drawing). Wiring layer 15b provided on the lower surface side) and via 15vb penetrating through insulating layer 14b and electrically connected to wiring layer 15b and first wiring layer 13b. . A protective insulating film 16b such as a solder resist is provided so as to cover the second insulating layer 14b as the lowermost layer. The protective insulating film 16b is provided with an opening 16hb from which the lower surface of the second wiring layer 15b is exposed.

  In FIG. 1, the semiconductor device 20 is shown in a simplified manner for convenience of illustration. In FIG. 1, the wiring layers 13a, 13b, 15a, and 15b provided on the insulating layers 12a, 12b, 14a, and 14b are a part of the wiring layers necessary for forming a laminated structure. However, it is not limited to this. Further, the number of layers of the laminated wiring is only an example, and is not limited thereto. For example, the laminated wiring may be only one layer, or the upper surface side and the lower surface side of the core substrate 11. The number of layers of the laminated wiring provided in may be different. Here, when the number of laminated wiring layers provided on the upper surface side and the lower surface side of the core substrate 11 (particularly, the number of insulating layers made of prepreg) is configured to be the same, the substrate with a built-in semiconductor device described later. The module manufacturing method has the following advantages. That is, the tensile stress generated on the upper surface side and the lower surface side of the core substrate (see FIGS. 6 to 12) 11w in the aggregate substrate state can be balanced in the process until the semiconductor device built-in substrate module is separated. The warpage of the core substrate 11w can be reduced, and the manufacturing yield can be improved.

  Next, a semiconductor device having a wafer level CSP structure applicable to the substrate module with a built-in semiconductor device according to the present embodiment will be described in detail with reference to the drawings. Here, a basic configuration of a semiconductor device having a wafer level CSP structure applicable to this embodiment will be described.

  FIG. 2 is a schematic plan view showing an embodiment of a semiconductor device applicable to the substrate module with a built-in semiconductor device according to the present invention, and FIG. 3 is a schematic sectional view showing the semiconductor device applicable to the embodiment. is there. 3A is a line IIIA-IIIA in the semiconductor device shown in FIG. 2 (in this specification, as a symbol corresponding to the Roman numeral “3” shown in FIG. 3 is a diagram showing a cross section taken along line IIIB-IIIB in the semiconductor device shown in FIG.

  In the semiconductor device 20 applicable to the present embodiment, for example, as shown in FIGS. 2, 3A, and 3B, an integrated circuit (not shown) having a predetermined function is provided on the upper surface 21a side (FIG. 2). A silicon substrate (semiconductor substrate) 21 formed on the front side of the paper and on the upper surface side of FIG. 3A and FIG. 3B (first surface) is provided. Here, the integrated circuit is formed of each known element such as a transistor, a diode, a resistor, a capacitor, and the like, and a wiring layer that connects these elements to each other.

  As shown in FIGS. 2, 3A and 3B, the upper surface 21a of the silicon substrate 21 is provided with a plurality of connection pads 22a made of aluminum-based metal or the like connected to each element of the integrated circuit. Yes. A passivation film 23 made of silicon oxide, silicon nitride or the like is provided on the upper surface 21a of the silicon substrate 21 as an insulating film for protecting the integrated circuit. Here, the passivation film 23 is provided so as to cover the plurality of connection pads 22a described above, and a plurality of openings 23h that expose a part (for example, a central portion) of the upper surface of each connection pad 22a are provided. .

  On the upper surface of the passivation film 23, an insulating film 24a made of polyimide resin or the like is in the direction of the normal line with respect to the upper surface 21a of the silicon substrate 21 (the front side in FIG. 2 or in FIGS. 3A and 3B). In other words, when the silicon substrate 21 is viewed in plan view from the upper surface side, a rectangular shape or a square shape is formed so that the region including the outer peripheral edge of the upper surface of the passivation film 23 is exposed in a frame shape. Is provided. A portion of the insulating film 24a corresponding to the opening 23h of the passivation film 23 is provided with an opening 24ha, and a part of the upper surface (for example, the central portion) of each connection pad 22a is exposed. That is, the upper surface of each connection pad 22a is exposed through the opening 24ha of the insulating film 24a provided at a position aligned with the opening 23h provided in the passivation film 23.

  In the present embodiment, as shown in FIG. 2, a case is shown in which a plurality of connection pads 22 a are arranged along the outer peripheral edge of the upper surface 21 a of the silicon substrate 21 so as to form a substantially rectangular frame shape. However, the arrangement of the connection pads 22a is not limited to this. In this embodiment, as shown in FIGS. 2, 3A, and 3B, the insulating film 24a is formed on the silicon substrate 21 on the upper surface side (the front side in FIG. 2 or FIG. 3A). , (Corresponding to the upper side of (b)), a configuration in which the insulating film 24a is provided in a rectangular shape or a square shape so that the upper surface of the outer peripheral edge portion of the passivation film 23 is exposed in a frame shape will be described. However, it is not limited to this. That is, the configuration is not limited to the configuration in which the planar shapes of the passivation film 23 and the insulating film 24a are different from each other, but the planar shape of the passivation film 23 and the insulating film 24a is provided to be the same so that the outer peripheral portion of the silicon substrate 21 The upper surface 21a may be configured to be exposed in a frame shape.

  Also, as shown in FIGS. 2, 3A, and 3B, a plurality of wiring layers 25a are provided on the upper surface of the insulating film 24a so as to extend with a predetermined wiring pattern. . The wiring layer 25a includes, for example, a seed metal layer 25-1a made of copper or the like provided on the upper surface of the insulating film 24a, and a wiring metal layer 25-2a made of copper or the like provided on the upper surface of the seed metal layer 25-1a. And a two-layer structure. One end portion 25x of each wiring layer 25a is electrically connected to the upper surface of each connection pad 22a through openings 23h and 24ha provided in the passivation film 23 and the insulating film 24a. A land 25y is formed at the other end of each wiring layer 25a. The one end portion 25x and the other end portion (land 25y) of each wiring layer 25a are connected by a lead wire portion 25z formed integrally therewith.

  Also, as shown in FIGS. 2, 3A and 3B, the upper surface of the land 25y of each wiring layer 25a is made of copper or the like extending in the direction of the normal to the upper surface 21a of the silicon substrate 21. The external connection columnar electrode (first connection electrode) 26a is provided, and the land 25y and the columnar electrode 26a are electrically connected. Here, as shown in FIG. 2, for example, the columnar electrodes 26a are arranged in a square so as to have equal intervals in each side direction (vertical direction and horizontal direction in the drawing) of the rectangular silicon substrate 21.

  Further, as shown in FIGS. 3A and 3B, the upper surface side of the silicon substrate 21 provided with the wiring layer 25a and the insulating film 24a is covered with the insulating film 24a among the upper surface of the passivation film 23. The first sealing made of an epoxy resin containing silica filler or the like so as to cover the exposed region and the exposed region of the upper surface of the insulating film 24a without being covered with the wiring layer 25a A layer 27a is provided. The upper surface of the first sealing layer 27a is flattened so as to be substantially flush with the upper surface (end portion) of the columnar electrode 26a described above.

  Further, as shown in FIGS. 3A and 3B, silicon is not formed on the lower surface 21b side of the silicon substrate 21 (the back side of the paper in FIG. 2 and the lower surface side of FIGS. 3A and 3B). A plurality of connection pads provided on the upper surface 21a side, for example, when the substrate 21 is viewed in plan from the lower surface side (corresponding to the back side of FIG. 2 or the lower side of FIGS. 3A and 3B). A plurality of connection pads 22b are provided at positions aligned with 22a. Here, the number and arrangement interval (pitch) of the connection pads 22a on the upper surface 21a side and the connection pads 22b on the lower surface 21b side may be set to be the same. It may be set to the arrangement interval.

  In the semiconductor device 20 according to the present embodiment, as shown in FIGS. 2, 3A, and 3B, the silicon substrate 21 is arranged in the thickness direction (the vertical direction in FIGS. 3A and 3B). A through electrode 22c made of an aluminum-based metal or the like for electrically connecting the connection pad 22a on the upper surface 21a side and the connection pad 22b on the lower surface 21b side of the silicon substrate 21. Yes. Here, for example, as shown in FIGS. 2, 3A, and 3B, the through electrode 22c is a pair of connection pads 22a and 22b provided on the upper surface 21a side and the lower surface 21b side of the silicon substrate 21. It is provided so as to be connected in the relationship of 1. 2, 3 (a), and (b), the configuration is shown in which all connection pads 22 a and 22 b provided on the upper surface 21 a side and the lower surface 21 b side are connected to each other in a one-to-one relationship. Alternatively, only the connection pads 22a and 22b at arbitrary arrangement positions may be connected via the through electrode 12c. That is, connection pads 22a and 22b that are not connected to each other may be provided through the through electrode 22c. Further, as shown in FIGS. 2, 3A, and 3B, the through electrode 22c is provided on the upper surface 21a side and the lower surface 21b side when the silicon substrate 21 is viewed in plan view from the upper surface side or the lower surface side. It is provided at a position that matches the arrangement of the connection pads 22a and 22b. According to this, when the silicon substrate 21 is viewed from the upper surface side or the lower surface side, the connection pads 22a and 22b and the through electrodes 22c on the upper surface 21a side and the lower surface 21b side are planarly arranged at the same position or region. It can provide so that it may overlap. Accordingly, when viewed in plan, it is not necessary to provide the formation region of the through electrode 22c separately from the formation region of the connection pads 22a and 22b, and therefore, the layout design of the semiconductor device (integrated circuit) is not restricted.

  3A and 3B, an insulating film 24b made of polyimide resin or the like is provided on the lower surface 21b of the silicon substrate 21 so as to cover the plurality of connection pads 22b described above. ing. The insulating film 24b is provided in a rectangular shape or a square shape so that a region including the outer peripheral edge of the lower surface 21b of the outer peripheral edge portion of the silicon substrate 21 is exposed in a frame shape when the silicon substrate 21 is viewed from the lower surface side. It has been. The insulating film 24b is provided with a plurality of openings 24hb that expose a part (for example, the center) of the lower surface of each connection pad 22b.

  Also, as shown in FIGS. 3A and 3B, a plurality of wiring layers 25b are provided on the lower surface of the insulating film 24b so as to extend with a predetermined wiring pattern. Similar to the wiring layer 25a described above, the wiring layer 25b includes, for example, a seed metal layer 25-1b made of copper or the like provided on the lower surface of the insulating film 24b and a copper provided on the upper surface of the seed metal layer 25-1b. It has a two-layer structure with a wiring metal layer 25-2b made of or the like. One end portion 25x of each wiring layer 25b is electrically connected to the lower surface of each connection pad 22b through an opening 24hb provided in the insulating film 24b. A land 25y is formed at the other end of each wiring layer 25b. The one end portion 25x and the other end portion (land 25y) of each wiring layer 25b are connected by a lead wire portion 25z formed integrally therewith.

  Further, as shown in FIGS. 3A and 3B, the external connection made of copper or the like extending in the direction of the normal to the lower surface 21b of the silicon substrate 21 is provided on the lower surface of the land 25y of each wiring layer 25b. Columnar electrodes (second connection electrodes) 26b are provided, and the lands 25y and the columnar electrodes 26b are electrically connected. Here, like the columnar electrode 26a shown in FIG. 2, for example, the columnar electrodes 26b are arranged in a square so as to have equal intervals in each side direction (vertical direction and horizontal direction in the drawing) of the rectangular silicon substrate 21. Yes.

  3A and 3B, the lower surface side of the silicon substrate 21 provided with the wiring layer 25b and the insulating film 24b is covered with the insulating film 24b among the lower surface of the silicon substrate 21. A second sealing made of an epoxy resin containing silica filler so as to cover the exposed region and the exposed region of the lower surface of the insulating film 24b that is not covered by the wiring layer 25b. A layer 27b is provided. The lower surface of the second sealing layer 27b is flattened so as to be substantially flush with the lower surface (end portion) of the columnar electrode 26b described above.

  3A and 3B, when all the columnar electrodes 26a and 26b provided on the upper surface side and the lower surface side of the silicon substrate 21 are viewed in plan view from the upper surface side or the lower surface side. Although the structure provided at the substantially aligned position is shown, the installation positions of the columnar electrodes 26a and 26b are not limited to this. For example, as will be described later, when a semiconductor device built-in substrate module incorporating the semiconductor device 20 according to the present embodiment is mounted on a circuit board, other semiconductor devices are stacked in a package-on-package (POP) structure. In this case, the columnar electrodes 26a and 26b are provided at positions where electrical connection with electrodes provided on at least a circuit board to be mounted or another semiconductor device to be stacked is possible. I just need it. 3A and 3B show a configuration in which the same number of columnar electrodes 26a and 26b provided on the upper surface side and the lower surface side of the silicon substrate 21 are provided, but as shown in FIG. Any number of columnar electrodes 26a and 26b may be provided.

  Thus, in the semiconductor device 20 applicable to the present embodiment, the connection pads 22a and 22b connected to each other by the through electrode 22c are provided on the upper surface 21a and the lower surface 21b of the silicon substrate 21. Further, wiring layers 25a and 25b connected to the connection pads 22a and 22b and column electrodes 26a and 26b for external connection are provided on the upper surface side and the lower surface side of the silicon substrate 21, respectively. A first sealing layer 27a and a second sealing layer 27b are respectively provided so as to cover the peripheral side portions of 26a and 26b and to expose the upper surface of the columnar electrode 26a and the lower surface of the columnar electrode 26b. . Thereby, the columnar electrodes 26a and 26b provided on the upper surface side and the lower surface side of the silicon substrate 21 are electrically connected via the wiring layer 25a, the connection pad 22a, the through electrode 22c, the connection pad 22b, and the wiring layer 25b. The resulting configuration is obtained. That is, the columnar electrodes 26a and 26b on the upper surface side and the lower surface side of the silicon substrate 21 are connected to a single connection pad 22a directly connected to the integrated circuit, and a predetermined signal or voltage is passed through the columnar electrodes 26a and 26b. Thus, input / output is common to the integrated circuits. Alternatively, it functions as a through conduction path through which a predetermined signal or voltage is transmitted as it is between the columnar electrodes 26a and 26b on the upper surface side and the lower surface side.

  In addition, as described above, the semiconductor device 20 applied to the present embodiment has an upper surface side in addition to the configuration in which the columnar electrodes 26a and 26b on the upper surface side and the lower surface side of the silicon substrate 21 are electrically connected to each other. The columnar electrode 26a may be mixed with a configuration in which only the connection pad 22a is connected via the wiring layer 25a, or the columnar electrode 26b on the lower surface side may be connected to the wiring layer 25b, the connection pad 22b, and the through-hole. A configuration in which only the connection pad 22a on the upper surface side is connected via the electrode 22c may be mixed. Moreover, although the case where the connection pad 22a on the upper surface side of the silicon substrate 21 is connected to the integrated circuit has been described, the connection pad 22a may be configured not to be connected to the integrated circuit. Good. Furthermore, the columnar electrodes 26a and 26b provided on the upper surface side or the lower surface side of the silicon substrate 21 may have an electrically independent configuration, or a specific columnar electrode may be formed by, for example, the wiring layers 25a and 25b. 26a or 26b (for example, columnar electrodes 26a or 26b provided at adjacent positions) may be configured to be electrically connected to each other.

  Thus, in the semiconductor device built-in substrate module 10 according to the present embodiment, the through electrode 22c is electrically connected to the upper surface 21a side and the lower surface 21b side of the silicon substrate 21 of the semiconductor device 20 built in the core substrate 11. The wiring layers 25a and 25b and the columnar electrodes 26a and 26b are provided. Thereby, a configuration in which the columnar electrodes 26 a and 26 b provided on the upper surface side and the lower surface side of the semiconductor device 20 are conductive is obtained.

  Therefore, by embedding such a semiconductor device 20 in the opening 11 h provided in the core substrate 11, the wiring layers 13 a and 15 a on the upper surface side of the core substrate 11 and the wiring on the lower surface side are connected via the semiconductor device 20. The layers 13b and 15b can be electrically connected. Thereby, since it is not necessary to form a through hole in the core substrate 11 around the opening 11h in which the semiconductor device 20 is embedded, the planar size of the semiconductor device built-in substrate module 10 (in other words, the semiconductor device built-in substrate module 10 is formed). The size of the core substrate 11 to be reduced) can be reduced. In this case, the wiring length is longer than that in the case where the upper wiring layers 13a and 15a and the lower wiring layers 13b and 15b are connected via the through holes provided around the opening 11h of the core substrate 11. And the deterioration of circuit characteristics such as signal delay can be suppressed. The effects of the semiconductor device built-in substrate module 10 according to the present embodiment will be described in more detail in the comparative verification described later.

  In addition, in the semiconductor device built-in substrate module 10 according to the present embodiment, the semiconductor device 20 has a CSP structure as a function and effect unique to the semiconductor device 20 built in the core substrate 11. It is possible to approximate the outer dimensions of individual semiconductor chips (corresponding to the silicon substrate 21 on which the integrated circuit is formed). Therefore, in a semiconductor device provided with a columnar electrode and a sealing layer covering the columnar electrode, when the columnar electrode is provided on both sides of the semiconductor device, the planar size is prevented from becoming larger than that of the silicon substrate. can do.

  In addition, the semiconductor device 20 applied to the present embodiment has columnar electrodes 26a and 26b that are directly connected to the wiring layers 25a and 25b on the upper surface side and the lower surface side of the silicon substrate 21, and further includes the columnar electrodes. The peripheral side portions of 26a and 26b are covered, and a first sealing layer 27a and a second sealing layer 27b for protecting the upper surface side and the lower surface side of the silicon substrate 21 are provided. Therefore, the internal stress and external stress of the semiconductor device built-in substrate module 10 after the manufacturing process and product shipment can be buffered, and the occurrence of damage and disconnection of the integrated circuit can be suppressed, and the circuit characteristics are good. In addition, a highly reliable semiconductor device can be applied.

  Further, the semiconductor device 20 applied to this embodiment has a configuration in which columnar electrodes 26 a and 26 b are provided on both the upper surface side and the lower surface side of the silicon substrate 21. Thereby, compared with the case where the columnar electrodes for external connection are arranged only on either side of the silicon substrate 21, the columnar electrodes can be distributed and arranged, so that the arrangement density of the electrodes can be reduced. In addition, the degree of freedom in designing the wiring layers 25a and 25b can be improved. Therefore, when the semiconductor device 20 is built in the core substrate 11, connection failure with the multilayer wiring layers (corresponding to the wiring layers 13a and 13b and the vias 13va and 13vb) provided on the upper surface side and the lower surface side of the core substrate 11 Generation of a short circuit between adjacent electrodes can be suppressed, and a highly reliable semiconductor device can be applied. Alternatively, since the columnar electrodes 26a and 26b can be dispersed and arranged at arbitrary positions on both surfaces of the silicon substrate 21, the wiring patterns of the wiring layers 25a and 25b can be increased in density or functionality. Therefore, it is possible to simplify the wiring pattern of the laminated wiring originally provided on the upper surface side and the lower surface side of the core substrate 11, thereby shortening the wiring length and reducing the number of wiring layers stacked. Alternatively, when the number of stacked wiring layers is the same, a stacked wiring having a more complicated and highly functional wiring pattern can be realized.

  Further, in the semiconductor device 20 having the wafer level CSP structure as shown in the present embodiment, the product inspection can be easily performed as compared with the so-called bare chip type semiconductor device, and the integrated circuit has a sealing layer or the like. Therefore, it is difficult to be affected by external environment such as external stress and contaminants. Therefore, defective products can be appropriately removed before the core substrate 11 is embedded in the opening 11h, and only good semiconductor devices can be built in the core substrate 11, so that the manufacturing yield can be improved.

  In the semiconductor device 20 shown in FIGS. 2 and 3, the seed is used as the wiring layer 25a connected to the connection pad 22a and the columnar electrode 26a, and the wiring layer 25b connected to the connection pad 22b and the columnar electrode 26b. The case where the metal layer 25-1a and the wiring metal layer 25-2a, or the wiring having the two-layer structure including the seed metal layer 25-1b and the wiring metal layer 25-2b has been described. This wiring structure is only for explaining an example of the semiconductor device 20, and the present invention is not limited to this. That is, the wiring layers 25a and 25b applied to the semiconductor device 20 may be composed of, for example, a single metal layer or a conductive layer, or a stack of three or more layers of metal layers or conductive layers. It may have a wiring structure.

(Mounting structure of substrate module with built-in semiconductor device)
Next, a structure when the semiconductor device built-in substrate module according to the present embodiment is mounted on a circuit board will be described.

  FIG. 4 is a schematic cross-sectional view showing an example of the mounting structure of the semiconductor device built-in substrate module according to this embodiment. Here, a mounting structure when the semiconductor device built-in substrate module 10 shown in FIG. 1 is mounted on a circuit board in an upside down state will be described. FIG. 5 is a schematic cross-sectional view showing an example of a semiconductor device stacked and mounted on the substrate module with a built-in semiconductor device according to the present embodiment. For simplicity, the semiconductor device 40 is illustrated in a simplified manner in FIG.

  The mounting structure to which the semiconductor device built-in substrate module 10 having the above-described configuration is applied is provided on the lower surface side of the semiconductor device built-in substrate module 10 and exposed to each opening 16ha of the protective insulating film 16a, for example, as shown in FIG. A wiring layer 15a to be connected is bonded to each connection pad 32x provided on the upper surface of the circuit board 30 via individual solder balls 17 or solder paste. As a result, the integrated circuit (not shown) provided in the semiconductor device 20 embedded in the core substrate 11 of the semiconductor device built-in substrate module 10 includes the connection pad 22a, the wiring layer 25a, the columnar electrode 26a, and the via 13va. The wiring layer 13a, the via 15va, the wiring layer 15a, and the solder ball 17 are electrically connected to the connection pad 32x on the upper surface of the circuit board 30 (see FIG. 3A).

  The circuit board 30 applied to the mounting structure shown in FIG. 4 has a structure in which a predetermined wiring pattern is formed on a film-like or flat insulator 31 by a conductor foil 32 made of a metal film such as copper. An insulating film 33 is formed so as to cover the entire top surface of the conductor foil 32. The conductor foil 32 is provided with a plurality of connection pads 32x that are electrically connected to an external circuit such as the substrate module 10 with a built-in semiconductor device. The insulating film 33 exposes the upper surfaces of these connection pads 32x. An opening 33h is provided in the front.

  Further, in this mounting structure example, for example, as shown in FIG. 4, the wiring layer 15b provided on the upper surface side of the semiconductor device built-in substrate module 10 and exposed to each opening 16hb of the protective insulating film 16b is formed by individual soldering. It is bonded to each columnar electrode 46 of another semiconductor device 40 having a wafer level CSP structure via a ball 48. Thereby, the integrated circuit provided in the semiconductor device 20 embedded in the core substrate 11 of the semiconductor device built-in substrate module 10 includes a connection pad 22a, a through electrode 22c, a connection pad 22b, a wiring layer 25b, a columnar electrode 26b, and It is electrically connected to another semiconductor device 40 via the via 13 vb, the wiring layer 13 b, the via 15 vb, the wiring layer 15 b, and the solder ball 48.

  Here, the semiconductor device 40 stacked and mounted on the upper surface side of the semiconductor device built-in substrate module 10 in the POP structure is, as shown in FIG. 5, the lower surface side of the silicon substrate in the semiconductor device 20 shown in FIGS. The insulating layer, the wiring layer, the columnar electrode, the sealing layer, and the through electrode penetrating the silicon substrate are not provided.

  That is, the semiconductor device 40 includes a semiconductor substrate 41 provided with a connection pad 42 on one of the upper surface and the lower surface, and one of the semiconductor substrates 41 so as to be connected to the connection pad 42 on the one surface. A columnar electrode (third connection electrode) 46 provided on the surface side and a third sealing layer 47 provided so as to cover the peripheral side portion of the columnar electrode 46 are included. Specifically, as shown in FIG. 5, a plurality of connection pads 42 connected to the integrated circuit and a passivation film 43 for protecting the integrated circuit are provided on the upper surface 41a of the semiconductor substrate 41. Here, the passivation film 43 is provided with a plurality of openings 43 h that expose a part of the upper surface of each connection pad 42. In addition, an insulating film 44 is provided on the upper surface of the passivation film 43, and an opening 44 h is provided in a portion corresponding to the opening 43 h of the passivation film 43, and a part of the upper surface of each connection pad 42 is exposed. .

  Also, as shown in FIG. 5, a plurality of wiring layers 45 are provided on the upper surface of the insulating film 44 so as to extend with a predetermined wiring pattern. The wiring layer 45 may have a laminated structure composed of a plurality of metal layers, or may be composed of a single metal layer, like the semiconductor device 20 described above. . One end of each wiring layer 45 is electrically connected to each connection pad 42 through openings 43h and 44h, and a columnar electrode 46 is provided on the other end of each wiring layer 45. . A third sealing layer 47 is provided on the upper surface side of the semiconductor substrate 41 provided with the wiring layer 45 and the insulating film 44 so that the end of the columnar electrode 46 is exposed on the upper surface.

  According to such a mounting structure, as described above, the planar size of the substrate module 10 with a built-in semiconductor device can be reduced, so that an increase in mounting area on the circuit board 30 can be suppressed. The mounting structure can be densified. Further, as described above, the wiring length provided in the semiconductor device built-in substrate module 10 can be shortened as compared with the case where the core substrate 11 is provided with a through hole for wiring, so that a circuit such as a signal delay is provided. A mounting structure in which deterioration of characteristics is suppressed can be realized.

(Manufacturing method of substrate module with built-in semiconductor device)
Next, a method for manufacturing the semiconductor device built-in substrate module according to the present embodiment will be described.
6 to 12 are process cross-sectional views illustrating an example of a method for manufacturing a substrate module with a built-in semiconductor device according to the present embodiment. Here, a manufacturing method of the semiconductor device built-in substrate module applied to the mounting structure shown in FIG. 4 will be described. 6A is a VIA-VIA line in the core substrate 11w shown in FIG. 6B (in this specification, as a symbol corresponding to the Roman numeral “6” shown in FIG. 6 for convenience). FIG. 6 is a diagram showing a cross section along “VI”. In addition, in the plan view shown in FIG. 6B, the core substrate 11w is hatched for the sake of convenience in order to clarify the shape of the core substrate 11w.

  In the manufacturing method of the semiconductor device built-in substrate module 10 described above, first, as shown in FIG. 6A, a core substrate 11w in a collective substrate state is prepared. Here, as shown in FIG. 6B, a plurality of substrate module formation regions 10r are set in the core substrate 11w, and openings (cavities) penetrating the upper surface side and the lower surface side in each substrate module formation region 10r. ) 11hw is provided. Then, as shown in FIGS. 6A and 6C, the semiconductor device 20 having the configuration shown in FIGS. 2 and 3 is embedded in the opening 11hw of the core substrate 11w. Thereby, a configuration in which the semiconductor device 20 is embedded in the opening 11hw of each substrate module forming region 10r of the core substrate 11w is obtained. In FIGS. 6A and 6C, a region indicated by reference numeral 18 is a dicing street.

  Here, as described above, the semiconductor device 20 is provided with the wiring layers 25 a and 25 b and the columnar electrodes 26 a and 26 b on the upper surface side and the lower surface side of the silicon substrate 21. The semiconductor device 20 has a configuration in which the upper and lower wiring layers 25a and 25b and the columnar electrodes 26a and 26b are electrically connected by a through electrode 22c that penetrates the silicon substrate 21. In the semiconductor device 20, the first sealing layer 27a and the second sealing layer 27b are provided on the upper surface side and the lower surface side of the silicon substrate 21 so that the ends of the columnar electrodes 26a and 26b are exposed. ing.

  Next, as shown in FIG. 7A, the semiconductor device 20 side so as to cover the upper surface 11wa of the core substrate 11w and the upper surface of the semiconductor device 20 in a state where the semiconductor device 20 is embedded in the opening 11hw of the core substrate 11w. In order from the semiconductor device 20, an insulating layer 12 a made of prepreg and a metal conductive layer (first metal layer) 13 wa made of copper foil or the like are stacked and the lower surface 11 wb of the core substrate 11 w and the lower surface of the semiconductor device 20 are covered. In order from the side, an insulating layer 12b made of prepreg and a metal conductive layer (second metal layer) 13wb made of copper foil or the like are laminated. Next, as shown in FIG. 7B, the core substrate 11w on which the insulating layers 12a and 12b and the metal conductive layers 13wa and 13wb are laminated is hot-pressed to bond and harden the layers.

  Next, as shown in FIG. 8A, using a laser via formation method, for example, the metal conductive layer 13wa and the insulating layer 12a on the upper surface side of the core substrate 11w are drilled by a laser drill apparatus, and the metal conductive layer 13wa and A via opening (first opening) 12ha is formed in the insulating layer 12a. Further, also on the lower surface side of the core substrate 11w, the metal conductive layer 13wb and the insulating layer 12b are drilled to form via openings (second openings) 12hb in the metal conductive layer 13wb and the insulating layer 12b. Here, the positions where the via openings 12ha and 12hb are formed are exposed on the upper or lower surface of the semiconductor device 20 embedded in the opening 11hw of the core substrate 11w when the core substrate 11w is viewed from the upper surface side or the lower surface side. It is set so as to be aligned with the arrangement position of the columnar electrodes 26a, 26b. As a result, the end portions of the columnar electrodes 26a and 26b exposed on the upper surface or the lower surface of the semiconductor device 20 are exposed in the via openings 12ha and 12hb.

  Next, as shown in FIG. 8B, at least the columnar electrodes 26a and 26b are formed by performing electrolytic plating of copper using the columnar electrodes 26a and 26b exposed on the upper and lower surfaces of the semiconductor device 20 as plating current paths. Copper plating is grown in the via openings 12ha and 12hb of the exposed insulating layers 12a and 12b to form vias 13va and 13vb. Here, the vias 13va and 13vb are formed so as to be electrically connected to the metal conductive layers 13wa and 13wb on the upper surface side or the lower surface side of the core substrate 11w, respectively. Further, since the columnar electrodes 26a and 26b of the semiconductor device 20 are electrically connected via the through electrode 22c provided on the silicon substrate 21, one of the columnar electrodes 26a and 26b is plated. By connecting to the electrodes for use, the vias 13va and 13vb are simultaneously formed in the same electrolytic plating process. In addition, since the part formed by the electrolytic plating of copper is formed so as to be integrated with the metal conductive layers 13wa and 13wb made of copper foil, their boundaries are not shown in the drawing.

  Next, the metal conductive layer 13wa formed on the upper surface side of the core substrate 11w is subjected to exposure and development processing using a photolithography method, whereby a predetermined amount is formed on the insulating layer 12a as shown in FIG. 8C. The wiring layer 13a having the wiring pattern and connected to the via 13va is formed. Next, similarly on the lower surface side of the core substrate 11w, the metal conductive layer 13wb is exposed and developed by using a photolithography method, so that the metal conductive layer 13wb is formed on the insulating layer 12b as shown in FIG. A wiring layer 13b having a predetermined wiring pattern and connected to the via 13vb is formed (first layered wiring forming step).

  Next, as shown in FIG. 9A, an insulating layer 14a made of prepreg and a metal conductive layer made of copper foil (first layer) are formed on the insulating layer 12a on which the wiring layer 13a is formed on the upper surface side of the core substrate 11w. 1 metal layer) 15wa is laminated, and on the insulating layer 12a on which the lower wiring layer 13a is formed, an insulating layer 14b made of prepreg and a metal conductive layer made of copper foil or the like (second metal layer) Laminate 15 wb. Then, the core substrate 11w in which the insulating layers 14a and 14b and the metal conductive layers 15wa and 15wb are stacked is hot-pressed to bond and cure the layers.

  Next, as shown in FIG. 9B, the metal conductive layer 15wa and the insulating layer 14a on the upper surface side of the core substrate 11w are used, as shown in FIG. Then, drilling is performed to form a via opening (first opening) 14ha in the metal conductive layer 15wa and the insulating layer 14a. Further, also on the lower surface side of the core substrate 11w, the metal conductive layer 15wb and the insulating layer 14b are drilled to form via openings (second openings) 14hb in the metal conductive layer 15wb and the insulating layer 14b. Here, the via openings 14ha and 14b are formed in the wiring pattern of the wiring layers 13a and 13b, which are the first layer laminated wiring, or vias when the core substrate 11w is viewed from the upper surface side or the lower surface side. It is set so as to be consistent with the 13 va and 13 vb formation regions. As a result, the wiring layers 13a and 13b or the vias 13va and 13vb which are the first layered wirings are exposed in the via openings 14ha and 14hb.

  Here, in the drilling process using the laser via forming method, which is also performed in the above-described first layer laminated wiring forming step, the formation positions of the via openings 12ha and 12hb or 14ha and 14b are in the lower layer. It is preferable to set so as to be aligned with the formed region of the columnar electrodes 26a and 26b or the vias 13va and 13vb. That is, when drilling is performed directly on a wiring layer in a region where the columnar electrodes 26a and 26b and the vias 13va and 13vb are not formed in the lower layer during drilling by the laser via forming method, the copper foil forming the wiring layer is burned out. May disappear. In order to prevent such a problem, it is conceivable to form a thick copper foil for forming the wiring layer. In this case, however, the tensile stress generated on the upper surface side and the lower surface side of the core substrate 11w in the aggregate substrate state is reduced. As the size of the core substrate 11w increases, the core substrate 11w is likely to be warped. On the other hand, when holes are formed on the formation regions of the columnar electrodes 26a and 26b and the vias 13va and 13vb, the above-described problems can be suppressed.

  Next, as shown in FIG. 10 (a), copper electrolytic plating using the wiring layers 13a and 13b or vias 13va and 13vb formed in the first layered wiring forming step as a plating current path is performed. By doing so, copper plating is grown at least in the via openings 14ha and 14hb of the insulating layers 14a and 14b where the wiring layers 13a and 13b or the vias 13va and 13vb are exposed, thereby forming vias 15va and 15vb. . Here, the vias 15va and 15vb are formed so as to be electrically connected to the metal conductive layers 15wa and 15wb formed on the insulating layers 14a and 14b, respectively. In addition, the wiring layers 13a and 13b and the vias 13va and 13vb, which are the first layer stacked wirings, pass through the through electrodes 22c provided in the silicon substrate 21 of the semiconductor device 20 embedded in the core substrate 11w. Since they are electrically connected, one of the vias 13va and 13vb is connected to the electrode for plating, whereby the vias 15va and 15vb are simultaneously formed in the same electrolytic plating process. As described above, the portions formed by the electrolytic plating of copper are formed so as to be integrated with the metal conductive layers 15wa and 15wb made of copper foil, respectively. Absent.

  Next, in the same manner as the first layered wiring formation process described above, the metal conductive layers 15wa and 15wb formed on the upper surface side and the lower surface side of the core substrate 11w are exposed and developed using photolithography, respectively. By performing the processing, as shown in FIG. 10B, wiring layers 15a and 15b having a predetermined wiring pattern on the insulating layers 14a and 14b and connected to the vias 15va or 15vb are formed (see FIG. 10B). Second layer laminated wiring forming step).

Then
As shown in FIG. 11A, a solder resist made of a thermosetting epoxy resin or the like is formed on the insulating layer 14a on the upper surface side of the core substrate 11w where the wiring layer 15a and the via 15va are formed. Formed as. Here, the protective insulating film 16a is formed with an opening 16ha through which the wiring layer 15a or the via 15va is exposed. A protective insulating film 16b is also formed on the lower surface side of the core substrate 11w on the insulating layer 14b in which the wiring layer 15b and the via 15vb are formed. Here, the protective insulating film 16b is formed with an opening 16hb through which the wiring layer 15b or the via 15vb is exposed.

  Next, as shown in FIG. 11B, solder balls 17 for external connection are connected to the wiring layer 15a or the vias 15va through the openings 16ha formed in the protective insulating film 16a on the upper surface side of the core substrate 11w. Formed to be. Although the case where the solder balls 17 are formed has been described here, a protruding electrode pad is formed by solder printing as applied to a land grid array (LGA) type package. There may be.

  Next, as shown in FIG. 12A, the wiring layer 15b or the via 15vb exposed in the opening 16hb formed in the protective insulating film 16b on the lower surface side of the core substrate 11w is connected to the wiring layer 15b or the via 15vb via the solder ball 48. Another semiconductor device 40 as shown in FIG.

  Next, as shown in FIG. 12B, the core substrate 11w having the solder ball 17 formed on the upper surface side and another semiconductor device 40 bonded to the lower surface side is formed on the dicing street 18 for each substrate module forming region 10r. A plurality of substrate modules 10 with a built-in semiconductor device applied to the mounting structure shown in FIG. 4 is obtained by cutting along the lines.

  In such a manufacturing method of the substrate module 10 with a built-in semiconductor device, an existing manufacturing method of a substrate module with a built-in semiconductor device can be applied almost as it is. Therefore, by using manufacturing technology that has already established manufacturing processes, manufacturing conditions, etc., it is possible to reduce the plane size while reducing the manufacturing cost, and realize a highly reliable semiconductor device built-in substrate module with good circuit characteristics. can do.

(Comparison verification)
Next, the operation and effect of the semiconductor device built-in substrate module according to the present embodiment will be verified by showing a comparative example.
FIG. 13 is a schematic cross-sectional view showing a comparative example of the semiconductor device built-in substrate module according to the present embodiment. Here, about the structure equivalent to embodiment mentioned above, the same or equivalent code | symbol is attached | subjected and shown for convenience.

  As shown in FIG. 13, the comparative example of the substrate module with a built-in semiconductor device according to the present embodiment is a semiconductor device having a configuration equivalent to the semiconductor device 40 shown in FIG. 5 in the opening 11 h provided in the core substrate 11. It is assumed that 20p is embedded. That is, the semiconductor device 20p has a configuration in which the integrated circuit, the wiring layer 25, the columnar electrode 26, the sealing layer 27, and the like are provided only on the upper surface side of the silicon substrate 21.

  In the semiconductor device built-in substrate module 10p having such a configuration, the wiring layer 25, the columnar electrode 26, and the like are provided only on the upper surface side of the semiconductor device 20p. Therefore, in order to obtain electrical connection between the semiconductor device 20p and the wiring layers 13b and 15b provided on the lower surface side of the core substrate 11, it is provided around the opening 11h of the core substrate 11 in which the semiconductor device 20p is embedded. It was necessary to connect via the through-hole 11v and the wiring layers 19a and 19b. As a result, in the comparative example, the planar size of the semiconductor device built-in substrate module 10p (in other words, the dimension of the core substrate 11 forming the semiconductor device built-in substrate module 10p) is increased and mounted on the circuit board. There is a problem that the area increases. In addition, since the laminated wiring on the upper surface side and the lower surface side of the core substrate 11 is electrically connected by the wiring path via the through hole 11v provided in the core substrate 11 around the opening 11h, the entire wiring length is reduced. There is a problem that circuit characteristics such as signal delay are deteriorated due to lengthening.

  On the other hand, in the semiconductor device built-in substrate module 10 according to the present embodiment, the semiconductor device 20 built in the core substrate 11 has a through electrode 22 c that penetrates the silicon substrate 21, and the upper surface side of the silicon substrate 21. And the lower wiring layers 25a and 25b and the columnar electrodes 26a and 26b are electrically connected to each other. Then, by incorporating such a semiconductor device 20 in the core substrate 11, the wiring layers 13 a, 13 b and 15 a, 15 b provided on the upper surface side and the lower surface side of the core substrate 11 are electrically connected via the semiconductor device 20. Therefore, it is not necessary to provide the through hole 11v as shown in the comparative example (see FIG. 13) in the peripheral region of the opening 11h in which the semiconductor device 20p is embedded. Therefore, according to the present embodiment, the planar size of the semiconductor device built-in substrate module (or the dimension of the core substrate forming the semiconductor device built-in substrate module) can be reduced, so that the mounting area occupied on the circuit board can be reduced. It is possible to suppress the increase and increase the density of the mounting structure.

  Further, according to the present embodiment, the wiring layers 13a, 13b and 15a, 15b on the upper surface side and the lower surface side of the core substrate 11 are avoided without using the wiring path that passes through the through hole 11v while avoiding the opening 11h. Since it can be directly electrically connected via the semiconductor device 20, the wiring length can be made shorter than the configuration shown in the comparative example, and deterioration of circuit characteristics such as signal delay can be suppressed.

As mentioned above, although some embodiment of this invention was described, this invention is not limited to embodiment mentioned above, It includes the invention described in the claim, and its equivalent range.
Hereinafter, the invention described in the scope of claims of the present application will be appended.

(Appendix)
The invention described in claim 1
An insulating substrate provided with an opening penetrating from the upper surface to the lower surface;
A semiconductor substrate provided with connection pads on the upper surface and the lower surface; a first connection electrode provided on the upper surface side of the semiconductor substrate so as to be connected to the connection pad on the upper surface; and a first connection electrode A first sealing layer provided so as to cover a peripheral side portion; a second connection electrode provided on a lower surface side of the semiconductor substrate so as to be connected to a connection pad on the lower surface; A second sealing layer provided so as to cover a peripheral side portion of the connection electrode, and a semiconductor device embedded in the opening of the insulating substrate;
A first wiring layer provided on the upper surface side of the semiconductor device so as to be connected to the first connection electrode of the semiconductor substrate;
A second wiring layer provided on the lower surface side of the semiconductor device so as to be connected to the second connection electrode of the semiconductor substrate;
A substrate module with a built-in semiconductor device.

The invention described in claim 2
2. The first connection electrode and the second connection electrode have a columnar shape extending in a direction of a normal line with respect to the upper surface and the lower surface of the insulating substrate. The substrate module with a built-in semiconductor device according to the above.

The invention according to claim 3
An integrated circuit is provided on the upper surface side of the semiconductor substrate,
3. The semiconductor device built-in substrate module according to claim 1, wherein the first connection electrode and the second connection electrode are connected to the integrated circuit. 4. .

The invention according to claim 4
Each of the first wiring layer and the second wiring layer includes a plurality of wiring layers, and an insulating layer is provided between the plurality of wiring layers of the first wiring layer and the second wiring layer. 4. The semiconductor device built-in substrate module according to claim 1, wherein the substrate module has a laminated structure provided so as to be interposed. 5.

The invention described in claim 5
5. The semiconductor device according to claim 1, further comprising a through electrode that penetrates through the semiconductor substrate and connects the connection pad on the upper surface and the connection pad on the lower surface of the semiconductor substrate. A semiconductor device built-in substrate module according to claim 1.

The invention described in claim 6
An insulating substrate provided with an opening penetrating from the upper surface to the lower surface;
A semiconductor substrate provided with connection pads on the upper surface and the lower surface; a first connection electrode provided on the upper surface side of the semiconductor substrate so as to be connected to the connection pad on the upper surface; and a first connection electrode A first sealing layer provided so as to cover a peripheral side portion; a second connection electrode provided on a lower surface side of the semiconductor substrate so as to be connected to a connection pad on the lower surface; A second sealing layer provided so as to cover a peripheral side portion of the connection electrode, and a semiconductor device embedded in the opening of the insulating substrate;
A first wiring layer provided on the upper surface side of the semiconductor device so as to be connected to the first connection electrode of the semiconductor substrate;
A semiconductor device built-in substrate module comprising: a second wiring layer provided on the lower surface side of the semiconductor device so as to be connected to the second connection electrode of the semiconductor substrate;
A mounting structure for a substrate module with a built-in semiconductor device, which is mounted on a circuit board provided with a connection pad.

The invention described in claim 7
A semiconductor substrate provided with a connection pad on one of the upper surface and the lower surface, and a third connection provided on one surface side of the semiconductor substrate so as to be connected to the connection pad on the one surface An electrode of another semiconductor device having an electrode for use and a third sealing layer provided so as to cover a peripheral side portion of the third connection electrode. 7. The mounting structure for a substrate module with a built-in semiconductor device according to claim 6, wherein one wiring layer of one wiring layer or the second wiring layer is connected.

The invention according to claim 8 provides:
8. The mounting structure of a semiconductor device built-in substrate module according to claim 7, wherein the one wiring layer is connected to the electrode of the other semiconductor device via a solder ball.

The invention according to claim 9 is:
9. The semiconductor device according to claim 6, further comprising a through electrode that penetrates through the semiconductor substrate and connects the connection pad on the upper surface and the connection pad on the lower surface of the semiconductor substrate. A semiconductor device built-in substrate module according to claim 1.

The invention according to claim 10 is:
Preparing an insulating substrate provided with an opening penetrating from the upper surface to the lower surface;
A semiconductor substrate provided with connection pads on the upper surface and the lower surface; a first connection electrode provided on the upper surface side of the semiconductor substrate so as to be connected to the connection pad on the upper surface; and a first connection electrode A first sealing layer provided so as to cover a peripheral side portion; a second connection electrode provided on a lower surface side of the semiconductor substrate so as to be connected to a connection pad on the lower surface; Embedding a semiconductor device having a second sealing layer provided so as to cover a peripheral side portion of the connection electrode in the opening of the insulating substrate;
A first wiring layer is formed on the upper surface side of the semiconductor device so as to be connected to the first connection electrode of the semiconductor substrate, and the second surface of the semiconductor substrate is formed on the lower surface side of the semiconductor device. Forming a second wiring layer so as to be connected to the connection electrode. A method of manufacturing a substrate module with a built-in semiconductor device.

The invention according to claim 11
Forming the first and second wiring layers includes:
Providing a first insulating layer and a first metal layer sequentially from the semiconductor device side so as to cover the upper surface of the insulating substrate and the upper surface of the semiconductor device;
Providing a first opening exposing the first connection electrode of the semiconductor device;
Providing a second insulating layer and a second metal layer in order from the semiconductor device side so as to cover the lower surface of the insulating substrate and the lower surface of the semiconductor device;
Providing a second opening for exposing the second connection electrode of the semiconductor device;
A first via connected to the first connection electrode and the first metal layer by performing electroplating using the first connection electrode and the second connection electrode as a plating current path. And forming a second via connected to the second connection electrode and the second metal layer on the lower surface side of the semiconductor device at the same time. The method of manufacturing a substrate module with a built-in semiconductor device according to claim 10.

The invention according to claim 12
12. The semiconductor according to claim 10, wherein after the step of forming the first and second wiring layers, the insulating substrate is cut to separate the substrate module with a built-in semiconductor device. It is a manufacturing method of an apparatus built-in substrate module.

DESCRIPTION OF SYMBOLS 10 Semiconductor device built-in board module 11 Core board 12a, 14a Insulating layer (1st insulating layer)
12b, 14b Insulating layer (second insulating layer)
13a, 15a Wiring layer (first wiring layer)
13b, 15b Wiring layer (second wiring layer)
13va, 15va via (first via)
13vb, 15vb via (second via)
16a, 16b Protective insulating film 17 Solder ball 20 Semiconductor device 21 Silicon substrate 22c Through electrode 25a, 25b Wiring layer 26a, 26b Columnar electrode (external connection electrode)
27a 1st sealing layer 27b 2nd sealing layer 30 Circuit board 40 Semiconductor device

Claims (12)

An insulating substrate provided with an opening penetrating from the upper surface to the lower surface;
A semiconductor substrate provided with connection pads on the upper surface and the lower surface; a first connection electrode provided on the upper surface side of the semiconductor substrate so as to be connected to the connection pad on the upper surface; and a first connection electrode A first sealing layer provided so as to cover a peripheral side portion; a second connection electrode provided on a lower surface side of the semiconductor substrate so as to be connected to a connection pad on the lower surface; A second sealing layer provided so as to cover a peripheral side portion of the connection electrode, and a semiconductor device embedded in the opening of the insulating substrate;
A first wiring layer provided on the upper surface side of the semiconductor device so as to be connected to the first connection electrode of the semiconductor substrate;
A second wiring layer provided on the lower surface side of the semiconductor device so as to be connected to the second connection electrode of the semiconductor substrate;
A substrate module with a built-in semiconductor device.   2. The first connection electrode and the second connection electrode have a columnar shape extending in a direction of a normal line with respect to the upper surface and the lower surface of the insulating substrate. The board | substrate module with a built-in semiconductor device of description. An integrated circuit is provided on the upper surface side of the semiconductor substrate,
3. The semiconductor device built-in substrate module according to claim 1, wherein the first connection electrode and the second connection electrode are connected to the integrated circuit. 4.   Each of the first wiring layer and the second wiring layer includes a plurality of wiring layers, and an insulating layer is provided between the plurality of wiring layers of the first wiring layer and the second wiring layer. 4. The semiconductor device built-in substrate module according to claim 1, wherein the substrate module has a laminated structure provided so as to be interposed. 5.   5. The semiconductor device according to claim 1, further comprising a through electrode that penetrates through the semiconductor substrate and connects the connection pad on the upper surface and the connection pad on the lower surface of the semiconductor substrate. A semiconductor device built-in substrate module according to claim 1. An insulating substrate provided with an opening penetrating from the upper surface to the lower surface;
A semiconductor substrate provided with connection pads on the upper surface and the lower surface; a first connection electrode provided on the upper surface side of the semiconductor substrate so as to be connected to the connection pad on the upper surface; and a first connection electrode A first sealing layer provided so as to cover a peripheral side portion; a second connection electrode provided on a lower surface side of the semiconductor substrate so as to be connected to a connection pad on the lower surface; A second sealing layer provided so as to cover a peripheral side portion of the connection electrode, and a semiconductor device embedded in the opening of the insulating substrate;
A first wiring layer provided on the upper surface side of the semiconductor device so as to be connected to the first connection electrode of the semiconductor substrate;
A semiconductor device built-in substrate module comprising: a second wiring layer provided on the lower surface side of the semiconductor device so as to be connected to the second connection electrode of the semiconductor substrate;
A mounting structure of a substrate module with a built-in semiconductor device, which is mounted on a circuit board provided with a connection pad.   A semiconductor substrate provided with a connection pad on one of the upper surface and the lower surface, and a third connection provided on one surface side of the semiconductor substrate so as to be connected to the connection pad on the one surface An electrode of another semiconductor device having an electrode for use and a third sealing layer provided so as to cover a peripheral side portion of the third connection electrode. 7. The mounting structure for a substrate module with a built-in semiconductor device according to claim 6, wherein one wiring layer of one wiring layer or the second wiring layer is connected.   8. The mounting structure of a semiconductor device built-in substrate module according to claim 7, wherein the one wiring layer is connected to the electrode of the other semiconductor device via a solder ball.   9. The semiconductor device according to claim 6, further comprising a through electrode that penetrates through the semiconductor substrate and connects the connection pad on the upper surface and the connection pad on the lower surface of the semiconductor substrate. A semiconductor device built-in substrate module according to claim 1. Preparing an insulating substrate provided with an opening penetrating from the upper surface to the lower surface;
A semiconductor substrate provided with connection pads on the upper surface and the lower surface; a first connection electrode provided on the upper surface side of the semiconductor substrate so as to be connected to the connection pad on the upper surface; and a first connection electrode A first sealing layer provided so as to cover a peripheral side portion; a second connection electrode provided on a lower surface side of the semiconductor substrate so as to be connected to a connection pad on the lower surface; Embedding a semiconductor device having a second sealing layer provided so as to cover a peripheral side portion of the connection electrode in the opening of the insulating substrate;
A first wiring layer is formed on the upper surface side of the semiconductor device so as to be connected to the first connection electrode of the semiconductor substrate, and the second surface of the semiconductor substrate is formed on the lower surface side of the semiconductor device. Forming a second wiring layer so as to be connected to the connection electrode. A method for manufacturing a substrate module with a built-in semiconductor device, comprising: Forming the first and second wiring layers includes:
Providing a first insulating layer and a first metal layer sequentially from the semiconductor device side so as to cover the upper surface of the insulating substrate and the upper surface of the semiconductor device;
Providing a first opening exposing the first connection electrode of the semiconductor device;
Providing a second insulating layer and a second metal layer in order from the semiconductor device side so as to cover the lower surface of the insulating substrate and the lower surface of the semiconductor device;
Providing a second opening for exposing the second connection electrode of the semiconductor device;
A first via connected to the first connection electrode and the first metal layer by performing electroplating using the first connection electrode and the second connection electrode as a plating current path. And forming a second via connected to the second connection electrode and the second metal layer on the lower surface side of the semiconductor device at the same time. The method for manufacturing a substrate module with a built-in semiconductor device according to claim 10.   12. The semiconductor according to claim 10, wherein after the step of forming the first and second wiring layers, the insulating substrate is cut to separate the substrate module with a built-in semiconductor device. Manufacturing method of substrate module with built-in device.

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