JP2018041963A - ラップアラウンドコンタクト一体化スキーム - Google Patents
ラップアラウンドコンタクト一体化スキーム Download PDFInfo
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- JP2018041963A JP2018041963A JP2017172005A JP2017172005A JP2018041963A JP 2018041963 A JP2018041963 A JP 2018041963A JP 2017172005 A JP2017172005 A JP 2017172005A JP 2017172005 A JP2017172005 A JP 2017172005A JP 2018041963 A JP2018041963 A JP 2018041963A
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- 230000010354 integration Effects 0.000 title abstract description 6
- 239000002184 metal Substances 0.000 claims abstract description 74
- 229910052751 metal Inorganic materials 0.000 claims abstract description 74
- 238000000034 method Methods 0.000 claims abstract description 59
- 238000005530 etching Methods 0.000 claims abstract description 36
- 239000000758 substrate Substances 0.000 claims abstract description 26
- 238000000151 deposition Methods 0.000 claims abstract description 11
- 238000003672 processing method Methods 0.000 claims abstract description 8
- 229910018072 Al 2 O 3 Inorganic materials 0.000 claims description 32
- 230000001681 protective effect Effects 0.000 claims description 25
- 230000004888 barrier function Effects 0.000 claims description 6
- 229910004298 SiO 2 Inorganic materials 0.000 claims description 5
- 229910044991 metal oxide Inorganic materials 0.000 claims description 5
- 150000004706 metal oxides Chemical class 0.000 claims description 5
- 229910052741 iridium Inorganic materials 0.000 claims description 3
- 229910052759 nickel Inorganic materials 0.000 claims description 3
- 229910052697 platinum Inorganic materials 0.000 claims description 3
- 229910052703 rhodium Inorganic materials 0.000 claims description 3
- 229910052707 ruthenium Inorganic materials 0.000 claims description 3
- 229910052721 tungsten Inorganic materials 0.000 claims description 3
- 229910021193 La 2 O 3 Inorganic materials 0.000 claims description 2
- 229910000577 Silicon-germanium Inorganic materials 0.000 claims description 2
- 229910010413 TiO 2 Inorganic materials 0.000 claims description 2
- ATJFFYVFTNAWJD-UHFFFAOYSA-N Tin Chemical compound [Sn] ATJFFYVFTNAWJD-UHFFFAOYSA-N 0.000 claims description 2
- 229910052914 metal silicate Inorganic materials 0.000 claims description 2
- 150000004767 nitrides Chemical class 0.000 claims description 2
- 230000015572 biosynthetic process Effects 0.000 abstract description 4
- 239000010408 film Substances 0.000 description 79
- 239000007789 gas Substances 0.000 description 10
- 239000000463 material Substances 0.000 description 7
- 238000001878 scanning electron micrograph Methods 0.000 description 6
- 238000000231 atomic layer deposition Methods 0.000 description 5
- 229910052799 carbon Inorganic materials 0.000 description 5
- 229910052760 oxygen Inorganic materials 0.000 description 5
- 239000004065 semiconductor Substances 0.000 description 5
- 229910052710 silicon Inorganic materials 0.000 description 5
- 229910052782 aluminium Inorganic materials 0.000 description 4
- 238000010586 diagram Methods 0.000 description 4
- GETQZCLCWQTVFV-UHFFFAOYSA-N trimethylamine Chemical compound CN(C)C GETQZCLCWQTVFV-UHFFFAOYSA-N 0.000 description 4
- 229910004541 SiN Inorganic materials 0.000 description 3
- 229910052731 fluorine Inorganic materials 0.000 description 2
- 239000011261 inert gas Substances 0.000 description 2
- 238000004519 manufacturing process Methods 0.000 description 2
- 229910052757 nitrogen Inorganic materials 0.000 description 2
- 239000002243 precursor Substances 0.000 description 2
- 238000010926 purge Methods 0.000 description 2
- 229910052814 silicon oxide Inorganic materials 0.000 description 2
- 239000000126 substance Substances 0.000 description 2
- OKTJSMMVPCPJKN-UHFFFAOYSA-N Carbon Chemical compound [C] OKTJSMMVPCPJKN-UHFFFAOYSA-N 0.000 description 1
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 description 1
- 239000006227 byproduct Substances 0.000 description 1
- 238000004140 cleaning Methods 0.000 description 1
- 230000007797 corrosion Effects 0.000 description 1
- 238000005260 corrosion Methods 0.000 description 1
- 230000005669 field effect Effects 0.000 description 1
- 238000010438 heat treatment Methods 0.000 description 1
- 239000012212 insulator Substances 0.000 description 1
- 238000001459 lithography Methods 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 239000001301 oxygen Substances 0.000 description 1
- 230000003071 parasitic effect Effects 0.000 description 1
- 229920002120 photoresistant polymer Polymers 0.000 description 1
- 239000010703 silicon Substances 0.000 description 1
- 239000010409 thin film Substances 0.000 description 1
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- H01L21/8232—Field-effect technology
- H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
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- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
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- H01L21/3105—After-treatment
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- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
- H01L21/321—After treatment
- H01L21/3213—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer
- H01L21/32139—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer using masks
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- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
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- H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
- H01L21/76816—Aspects relating to the layout of the pattern or to the size of vias or trenches
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- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76829—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers
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- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76829—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers
- H01L21/76831—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers in via holes or trenches, e.g. non-conductive sidewall liners
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- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76886—Modifying permanently or temporarily the pattern or the conductivity of conductive members, e.g. formation of alloys, reduction of contact resistances
- H01L21/76892—Modifying permanently or temporarily the pattern or the conductivity of conductive members, e.g. formation of alloys, reduction of contact resistances modifying the pattern
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- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
- H01L29/417—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions carrying the current to be rectified, amplified or switched
- H01L29/41725—Source or drain electrodes for field effect devices
- H01L29/41791—Source or drain electrodes for field effect devices for transistors with a horizontal current flow in a vertical sidewall, e.g. FinFET, MuGFET
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- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66787—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel
- H01L29/66795—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
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- H01L23/482—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of lead-in layers inseparably applied to the semiconductor body
- H01L23/485—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of lead-in layers inseparably applied to the semiconductor body consisting of layered constructions comprising conductive layers and insulating layers, e.g. planar contacts
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- H01L27/1203—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body the substrate comprising an insulating body on a semiconductor body, e.g. SOI
- H01L27/1211—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body the substrate comprising an insulating body on a semiconductor body, e.g. SOI combined with field-effect transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
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Abstract
Description
本出願は、2016年9月7日に出願された米国仮特許出願第62/384,494号明細書に関連しその優先権を主張するものであり、この内容全体が参照により本明細書に援用される。
2 基板
130 トレース
132 トレース
134 トレース
200 第1誘電体膜
201 側壁
202 第2誘電体膜
205 くぼみ
207 幅
208 金属含有膜
210 コンタクト開口部
211 幅
212 エッチストップ層
213 マスク開口部
214 金属含有側壁保護膜
215 凹状特徴
216 隆起コンタクト
218 誘電体膜
219 パターン化された金属含有膜
221 層
222 金属
400 水平線
Claims (20)
- 基板加工方法であって、
第1誘電体膜中の隆起コンタクトと前記第1誘電体膜上の第2誘電体膜とを含む基板を提供するステップと、
前記第2誘電体膜の上に金属含有膜を堆積するステップと、
前記金属含有膜中にマスク開口部をエッチングすることによってパターン化された金属含有膜を形成するステップと、
前記パターン化された金属含有膜をマスクとして使用して、前記隆起コンタクトの上の前記第2誘電体膜中に凹状特徴の異方性エッチングを行うステップであって、前記異方性エッチングにより、前記凹状特徴の側壁上に前記パターン化された金属含有膜の一部が再堆積されることによって、金属含有側壁保護膜が形成されるステップと、
を含む方法。 - 前記第1誘電体膜中にコンタクト開口部の等方性エッチングを行って、前記第2誘電体膜中の前記凹状特徴の下の前記隆起コンタクトを露出させるステップであって、前記コンタクト開口部の幅が、前記金属含有側壁保護膜によって画定される前記凹状特徴の幅よりも広いステップをさらに含み、請求項1に記載の方法。
- 前記等方性エッチングのステップの後、前記パターン化された金属含有膜および前記金属含有側壁保護膜を前記基板から除去するステップをさらに含む、請求項2に記載の方法。
- 前記コンタクト開口部の等方性エッチングのステップの前に、前記凹状特徴を前記第1誘電体膜中の前記隆起コンタクトまで延長するステップをさらに含む、請求項2に記載の方法。
- 前記凹状特徴の中、および前記コンタクト開口部中の前記隆起コンタクトの上に、コンタクト金属層を堆積するステップをさらに含む、請求項2に記載の方法。
- 前記コンタクト金属層が、Ti金属層、Co金属層、またはNi金属層を含む、請求項5に記載の方法。
- 前記コンタクト金属層の上に障壁層を堆積するステップをさらに含む、請求項5に記載の方法。
- 前記障壁層がTiN層を含む、請求項7に記載の方法。
- 前記凹状特徴および前記コンタクト開口部に金属を充填するステップをさらに含む、請求項2に記載の方法。
- 前記金属がRu、Rh、Os、Pd、Ir、Pt、Ni、Co、W、およびそれらの組合せからなる群から選択される、請求項9に記載の方法。
- 前記の充填するステップの前に、前記金属含有側壁保護膜を前記凹状特徴から除去するステップをさらに含む、請求項9に記載の方法。
- 前記第1誘電体膜、前記第2誘電体膜、または前記第1および第2誘電体膜の両方がSiO2を含む、請求項1に記載の方法。
- 前記金属含有膜が、金属酸化物膜、金属窒化物膜、金属酸窒化物膜、金属ケイ酸塩膜、およびそれらの組合せからなる群から選択される、請求項1に記載の方法。
- 前記金属酸化物膜が、Al2O3、HfO2、TiO2、ZrO2、Y2O3、La2O3、UO2、Lu2O3、Ta2O5、Nb2O5、ZnO、MgO、CaO、BeO、V2O5、FeO、FeO2、CrO、Cr2O3、CrO2、MnO、Mn2O3、RuO、およびそれらの組合せからなる群から選択される、請求項13に記載の方法。
- 前記隆起コンタクトがSiGeまたはSiCを含む、請求項1に記載の方法。
- 基板加工方法であって、
第1誘電体膜中の隆起コンタクトと前記第1誘電体膜の上の第2誘電体膜とを含む基板を提供するステップと、
前記第2誘電体膜の上にAl2O3膜を堆積するステップと、
前記Al2O3膜中にマスク開口部をエッチングすることによってパターン化されたAl2O3膜を形成するステップと、
前記パターン化されたAl2O3膜をマスクとして使用して、前記隆起コンタクトの上の前記第2誘電体膜中に凹状特徴の異方性エッチングを行うステップであって、前記異方性エッチングにより、前記凹状特徴の側壁上に前記パターン化されたAl2O3膜の一部が再堆積されることによって、Al2O3側壁保護膜が形成されるステップと、
前記第1誘電体膜中にコンタクト開口部の等方性エッチングを行って、前記第2誘電体膜中の前記凹状特徴の下の前記隆起コンタクトを露出させるステップであって、前記コンタクト開口部の幅が、前記Al2O3側壁保護膜によって画定される前記凹状特徴の幅よりも広いステップと、
を含む方法。 - 前記等方性エッチングのステップの後、前記パターン化されたAl2O3膜および前記Al2O3側壁保護膜を前記基板から除去するステップをさらに含む、請求項16に記載の方法。
- 前記コンタクト開口部の等方性エッチングのステップの前に、前記凹状特徴を前記第1誘電体膜中の前記隆起コンタクトまで延長するステップをさらに含む、請求項16に記載の方法。
- 前記凹状特徴の中、および前記コンタクト開口部中の前記隆起コンタクトの上に、コンタクト金属層を堆積するステップと、
前記コンタクト金属層の上に障壁層を堆積するステップと、
をさらに含む請求項16に記載の方法。 - 前記凹状特徴および前記コンタクト開口部に、Ru、Rh、Os、Pd、Ir、Pt、Ni、Co、W、およびそれらの組合せからなる群から選択される金属を充填するステップをさらに含む、請求項16に記載の方法。
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