JP2018032745A - Dresser, method of manufacturing dresser, and method of manufacturing semiconductor device - Google Patents

Dresser, method of manufacturing dresser, and method of manufacturing semiconductor device Download PDF

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Publication number
JP2018032745A
JP2018032745A JP2016164015A JP2016164015A JP2018032745A JP 2018032745 A JP2018032745 A JP 2018032745A JP 2016164015 A JP2016164015 A JP 2016164015A JP 2016164015 A JP2016164015 A JP 2016164015A JP 2018032745 A JP2018032745 A JP 2018032745A
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Japan
Prior art keywords
dresser
chip
substrate
manufacturing
base metal
Prior art date
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Japanese (ja)
Inventor
川崎 貴彦
Takahiko Kawasaki
貴彦 川崎
松井 之輝
Yukiteru Matsui
之輝 松井
聡文 側瀬
Akifumi Kawase
聡文 側瀬
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Kioxia Corp
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Toshiba Memory Corp
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Priority to JP2016164015A priority Critical patent/JP2018032745A/en
Priority to US15/429,542 priority patent/US10195716B2/en
Publication of JP2018032745A publication Critical patent/JP2018032745A/en
Pending legal-status Critical Current

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    • BPERFORMING OPERATIONS; TRANSPORTING
    • B24GRINDING; POLISHING
    • B24BMACHINES, DEVICES, OR PROCESSES FOR GRINDING OR POLISHING; DRESSING OR CONDITIONING OF ABRADING SURFACES; FEEDING OF GRINDING, POLISHING, OR LAPPING AGENTS
    • B24B53/00Devices or means for dressing or conditioning abrasive surfaces
    • B24B53/017Devices or means for dressing, cleaning or otherwise conditioning lapping tools
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/302Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
    • H01L21/306Chemical or electrical treatment, e.g. electrolytic etching
    • H01L21/30625With simultaneous mechanical treatment, e.g. mechanico-chemical polishing

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  • Engineering & Computer Science (AREA)
  • Mechanical Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Grinding-Machine Dressing And Accessory Apparatuses (AREA)
  • Mechanical Treatment Of Semiconductor (AREA)
  • Polishing Bodies And Polishing Tools (AREA)
  • Finish Polishing, Edge Sharpening, And Grinding By Specific Grinding Devices (AREA)

Abstract

PROBLEM TO BE SOLVED: To provide a polishing pad dresser that is excellent in productivity, and to provide a method of manufacturing the same.SOLUTION: A dresser 1 comprises: a base metal 10; and a chip part 20 provided on the base metal 10, and that includes an Si substrate having a projection on its upper part and whose plane orientation is a (111) plane, and a diamond thin-film layer formed on the projection of the Si substrate by using a plasma CVD method. Since the diamond thin-film layer is deposited on the Si substrate, an excellent high-temperature environment and a high productivity can be achieved compared with a case where the diamond thin-film layer is deposited on a metal-based substrate.SELECTED DRAWING: Figure 1

Description

本発明の実施形態は、ドレッサー、ドレッサーの製造方法、及び半導体装置の製造方法   Embodiments described herein relate to a dresser, a method for manufacturing a dresser, and a method for manufacturing a semiconductor device

に関する。 About.

半導体装置の製造プロセスにおいて、溝に埋め込まれた絶縁膜、金属膜、多結晶ケイ素
膜等を平坦化するための技術として化学機械研磨(Chemical Mechanic
al Polishing:CMP)が知られている。CMPでは、繰り返しの研磨に伴
い研磨パッドの表面が変形し研磨能力が低下するため、この低下を抑制するために一定時
間毎にドレッサーを用いて研磨パッドをドレッシングする。
As a technique for planarizing an insulating film, a metal film, a polycrystalline silicon film, etc. embedded in a trench in a semiconductor device manufacturing process, chemical mechanical polishing (Chemical Mechanical Polishing)
al Polishing: CMP) is known. In CMP, the surface of the polishing pad is deformed with repeated polishing and the polishing ability is lowered. Therefore, in order to suppress this drop, the polishing pad is dressed using a dresser at regular intervals.

特開平10−71559号公報JP-A-10-71559 特表2014−522739号公報Special table 2014-522739 gazette

本実施形態が解決しようとする課題は、高生産性に優れたドレッサー、ドレッサーの製
造方法、及び半導体装置の製造方法を提供する。
The problem to be solved by the present embodiment provides a dresser excellent in high productivity, a method for manufacturing a dresser, and a method for manufacturing a semiconductor device.

実施形態のドレッサーは、台金と、前記台金上に複数設けられ、上部に突起を有するS
i基板と前記Si基板の前記突起上に設けられたダイヤモンド薄膜層とを含むチップ部と
、を有する。
The dresser of the embodiment is provided with a base metal and a plurality of S on the base metal and having a protrusion on the top.
a chip portion including an i substrate and a diamond thin film layer provided on the protrusion of the Si substrate.

第1の実施形態に係るドレッサーを説明する図。The figure explaining the dresser which concerns on 1st Embodiment. 図1のチップ部の詳細を説明する図。The figure explaining the detail of the chip | tip part of FIG. 第1及び第2の実施形態のチップ部の製造方法を説明する図。The figure explaining the manufacturing method of the chip | tip part of 1st and 2nd embodiment. 第1及び第2の実施形態のチップ部の製造方法を説明する図。The figure explaining the manufacturing method of the chip | tip part of 1st and 2nd embodiment. マスクの平面図。The top view of a mask. 第1の実施形態に係るドレッサーの製造方法を説明する図。The figure explaining the manufacturing method of the dresser concerning a 1st embodiment. ドレッサー1を用いた具体例を示す図。The figure which shows the specific example using the dresser 1. FIG. 第2の実施形態に係るドレッサーを説明する図。The figure explaining the dresser which concerns on 2nd Embodiment. 第2の実施形態に係るドレッサーの製造方法を説明する図。The figure explaining the manufacturing method of the dresser which concerns on 2nd Embodiment.

以下、発明を実施するための実施形態について説明する。   Hereinafter, embodiments for carrying out the invention will be described.

(第1の実施形態)
第1の実施形態に係るドレッサーについて図1乃至図7を参照して説明する。なお、以
下の図面の記載において、同一な部分には同一の符号で表している。ただし、図面は厚さ
と平面寸法との関係、比率等は現実のものとは異なり、模式的なものである。
(First embodiment)
The dresser according to the first embodiment will be described with reference to FIGS. In the following description of the drawings, the same portions are denoted by the same reference numerals. However, the relationship between the thickness and the planar dimensions, the ratio, and the like are schematic, unlike the actual ones.

第1の実施形態に係るドレッサー1の構成を図1及び図2を用いて説明する。図1は本
実施形態のドレッサー1の作用面を示す平面模式図である。なお、作用面とは例えば研磨
パッド等のドレッシング対象物と対向する面のことである。
A configuration of the dresser 1 according to the first embodiment will be described with reference to FIGS. 1 and 2. FIG. 1 is a schematic plan view showing the working surface of the dresser 1 of the present embodiment. The working surface is a surface facing a dressing object such as a polishing pad.

図1に示すように、ドレッサー1の作用面は台金10上に複数のチップ部20を有する
。台金10は例えばステンレス(SUS)や鉄を含むがその材料は特に限定されない。チ
ップ部20はたとえばSiウエハ(Si基板)より形成される。チップ部20の大きさは
例えば、1mm〜50mmであるが、本実施形態においてチップ部20の大きさは特に限
定されない。また、本実施形態のドレッサー1のチップ部20の数も特に限定されないが
、チップ部20が複数個あることで均一にドレッシングされやすくなる。
As shown in FIG. 1, the working surface of the dresser 1 has a plurality of chip portions 20 on a base metal 10. The base 10 includes, for example, stainless steel (SUS) or iron, but the material is not particularly limited. The chip part 20 is formed from, for example, a Si wafer (Si substrate). The size of the chip portion 20 is, for example, 1 mm to 50 mm, but the size of the chip portion 20 is not particularly limited in the present embodiment. In addition, the number of the chip portions 20 of the dresser 1 of the present embodiment is not particularly limited, but a plurality of the chip portions 20 facilitates uniform dressing.

次にチップ部20の詳細について説明する。図2(a)はチップ部20の平面模式図、
図2(b)は図2(a)のA−A‘断面を示す断面模式図である。
Next, details of the chip unit 20 will be described. FIG. 2A is a schematic plan view of the chip portion 20.
FIG. 2B is a schematic cross-sectional view showing the AA ′ cross section of FIG.

図2(a)、(b)に示すように、チップ部20は基板21と基板21上の複数の突起
22とを有する。突起22は例えば半径0.15mm程度の円錐形状を有する。チップ部
20において、1つのチップ部20内にできるだけ多くの突起22を形成するために突起
22は例えばハニカム状に並んでいる。突起22は例えばSiを含み、基板21と一体化
している。図2(b)に示すように、突起22上にはダイヤモンド薄膜層23が形成され
ている。ダイヤモンド薄膜層23は突起22及び突起22から露出した基板21を含むチ
ップ部20の全面に亘って形成される。また、ダイヤモンド薄膜層23の厚みは略均一に
形成されている。なお、チップ部20における突起22の配置は図2のように限定されな
い。
As shown in FIGS. 2A and 2B, the chip unit 20 includes a substrate 21 and a plurality of protrusions 22 on the substrate 21. The protrusion 22 has a conical shape with a radius of about 0.15 mm, for example. In the chip part 20, the protrusions 22 are arranged in a honeycomb shape, for example, in order to form as many protrusions 22 as possible in one chip part 20. The protrusion 22 includes, for example, Si and is integrated with the substrate 21. As shown in FIG. 2B, a diamond thin film layer 23 is formed on the protrusion 22. The diamond thin film layer 23 is formed over the entire surface of the chip portion 20 including the protrusion 22 and the substrate 21 exposed from the protrusion 22. The diamond thin film layer 23 has a substantially uniform thickness. The arrangement of the protrusions 22 in the chip part 20 is not limited as shown in FIG.

次に、図3乃至図6を用いて、本実施形態のチップ部及びドレッサーの製造方法につい
て説明する。
Next, the manufacturing method of the chip part and the dresser according to the present embodiment will be described with reference to FIGS.

図3及び図4はSiウエハの一部の領域を示す断面模式図である。なお、以下の製造方
法においてSiウエハ内の位置による偏り等は無く、ウエハ全面に亘り略均一な構造に形
成されるものとする。
3 and 4 are schematic cross-sectional views showing a partial region of the Si wafer. In the following manufacturing method, there is no deviation due to the position in the Si wafer, and the wafer is formed in a substantially uniform structure over the entire surface of the wafer.

図3(a)に示すように、まずSiウエハを用意する。Siウエハ上に下地膜30をCV
D(Chemical Vapor Deposition)法を用いて形成する。下地
膜30は、例えば500nm程度のTEOS膜である。本実施形態では、Siウエハは半
導体製造プロセスにおいて一般的に用いられ、低価格で一定の硬度を有するため適してい
る。特に面方位が(111)面のSiウエハ(Si(111))は、結晶面方位が揃って
いるためビッカーズ硬度(Gpa)が高く(例えば、10.6Gpa以上)、より適して
いる。さらには、他の高硬度材料と比較して熱膨張係数がダイヤモンドと同程度(例えば
2.56×10‐6/K以下)なため適している。なお、Si(111)とは結晶内でS
i間の距離が等しくなるような原子配列を有する構造のことを言う。
As shown in FIG. 3A, an Si wafer is first prepared. CV is applied to the base film 30 on the Si wafer.
It is formed using D (Chemical Vapor Deposition) method. The base film 30 is a TEOS film of about 500 nm, for example. In this embodiment, the Si wafer is generally used in the semiconductor manufacturing process, and is suitable because it has a certain hardness at a low price. In particular, a Si wafer (Si (111)) having a (111) plane orientation has a higher Vickers hardness (Gpa) (for example, 10.6 Gpa or more) because the crystal plane orientation is uniform, and is more suitable. Furthermore, it is suitable because it has a thermal expansion coefficient comparable to that of diamond (for example, 2.56 × 10 −6 / K or less) as compared with other high hardness materials. Si (111) means S in the crystal.
A structure having an atomic arrangement in which the distances between i are equal.

次に、図3(b)に示すように下地膜30上にレジスト膜40を形成する。レジスト膜
40は例えばi線用レジスト膜である。その後例えば図5に示すようなマスクを介して例
えばi線によってレジスト膜を露光する。ただし、波長等は特に限定されない。
Next, a resist film 40 is formed on the base film 30 as shown in FIG. The resist film 40 is, for example, an i-line resist film. Thereafter, the resist film is exposed by, for example, i-line through a mask as shown in FIG. However, the wavelength and the like are not particularly limited.

次に、図3(c)に示すように、露光されたレジスト膜40を現像した後、ドライエッ
チングによってレジスト膜40をマスクに下地膜30を略垂直にエッチングする。この時
、例えばCFガス等を用いる。
Next, as shown in FIG. 3C, after the exposed resist film 40 is developed, the underlying film 30 is etched substantially vertically by dry etching using the resist film 40 as a mask. At this time, for example, CF 4 gas or the like is used.

次に、図3(d)に示すように、Siウエハのエッチングを行う。例えば、SF=7
0secm、C4F8=200sccm、O=500sccmの混合ガスを用いてエッチ
ングを行う。同条件下でさらにエッチングを進めると、図4(a)に示すように、Siウ
エハの上端が角の円錐形状に近づく。同時に、レジスト膜40及び下地膜30の大きさも
縮小していく。最終的には、Siウエハに複数の円錐状の突起22が形成される(図4(
b))。縮小したレジスト膜40及び下地膜30は突起22間に落下する。
Next, as shown in FIG. 3D, the Si wafer is etched. For example, SF 6 = 7
Etching is performed using a mixed gas of 0 secm, C4F8 = 200 sccm, and O 2 = 500 sccm. When the etching is further advanced under the same conditions, the upper end of the Si wafer approaches a corner cone shape as shown in FIG. At the same time, the sizes of the resist film 40 and the base film 30 are also reduced. Finally, a plurality of conical protrusions 22 are formed on the Si wafer (FIG. 4 (
b)). The reduced resist film 40 and base film 30 fall between the protrusions 22.

次に、アッシャー又はNH4OH洗浄等によって縮小したレジスト膜40及び下地膜3
0を除去する。以上の工程により、例えば円錐形状等の所望の形状の突起が形成されたS
iウエハが得られる。
Next, the resist film 40 and the underlying film 3 reduced by asher or NH4OH cleaning or the like.
Remove 0. Through the above steps, a protrusion having a desired shape such as a conical shape is formed.
An i-wafer is obtained.

次に、上述した複数の円錐形状の突起22が形成されたSiウエハを個片化するため、
所望のサイズにダイシングし、ベースプレートとなるチップ部20を得る(図6(a))。
チップ部20は例えば、300mmウエハの場合160チップ以上、200mmウエハの
場合70チップ以上取得可能であるが、チップ数は特に限定されない。
Next, in order to separate the Si wafer on which the plurality of conical protrusions 22 described above are formed,
Dicing to a desired size yields a chip portion 20 that becomes a base plate (FIG. 6A).
For example, the chip unit 20 can acquire 160 chips or more in the case of a 300 mm wafer and 70 chips or more in the case of a 200 mm wafer, but the number of chips is not particularly limited.

次に、チップ部20上にダイヤモンド薄膜層23を形成する。ダイヤモンド薄膜層23
は、例えばプラズマCVD法を用い、減圧容器の中に設けられる接地した陽極上にチップ
部20を置いて800度に加熱する。その後メタンと水素の混合気体を減圧下に流入させ
、陰極に直流1000V程度をかけ、異常グロー放電を行うことにより形成される。なお
、上記の形成方法は一例である。上記のようにして、ダイヤモンド薄膜層23が形成され
た突起22を有するチップ部20を得る。
Next, a diamond thin film layer 23 is formed on the tip portion 20. Diamond thin film layer 23
For example, using a plasma CVD method, the tip portion 20 is placed on a grounded anode provided in a decompression vessel and heated to 800 degrees. Thereafter, a mixed gas of methane and hydrogen is introduced under reduced pressure, a direct current of about 1000 V is applied to the cathode, and abnormal glow discharge is performed. The above forming method is an example. As described above, the tip portion 20 having the protrusion 22 on which the diamond thin film layer 23 is formed is obtained.

次に、図6(b)に示すように、チップ部20の突起22形成面の裏面に樹脂を塗布し
、例えばステンレス(SUS)等を含む台金10に貼付する。樹脂は、例えばエポキシ樹
脂とアミン系接着剤との混合剤又はエポキシ樹脂とポリアミドアミン系接着剤との混合剤
を用いる。台金10は例えば、リング状構造を有するが特に限定されない。
Next, as shown in FIG. 6B, a resin is applied to the back surface of the surface of the chip portion 20 where the protrusions 22 are formed, and is attached to a base metal 10 including, for example, stainless steel (SUS). As the resin, for example, a mixture of an epoxy resin and an amine adhesive or a mixture of an epoxy resin and a polyamidoamine adhesive is used. The base metal 10 has, for example, a ring-shaped structure, but is not particularly limited.

以上のようにして、本実施形態のドレッサー1が完成する。   As described above, the dresser 1 of the present embodiment is completed.

次に、本実施形態に係るドレッサー1を用いた具体例について説明する。   Next, a specific example using the dresser 1 according to the present embodiment will be described.

図7はドレッサー1を用いた具体例である研磨装置100の構成示す模式図である。図
7に示すように、研磨装置100はドレッシング機構2、研磨ヘッド3、ノズル4、研磨
パッド5、回転テーブル6を有する。また、この他に一部図示しない構成があっても良い
FIG. 7 is a schematic diagram showing a configuration of a polishing apparatus 100 as a specific example using the dresser 1. As shown in FIG. 7, the polishing apparatus 100 includes a dressing mechanism 2, a polishing head 3, a nozzle 4, a polishing pad 5, and a rotary table 6. In addition, there may be a configuration that is not illustrated in part.

回転テーブル6は、図示しない回転軸に下から支承され、回転軸が外部の駆動装置によ
り回転駆動されることによって所定速度で回転する。
The rotary table 6 is supported from below on a rotary shaft (not shown), and rotates at a predetermined speed when the rotary shaft is driven to rotate by an external driving device.

研磨ヘッド3の下部には半導体ウエハが位置する。ウエハは、研磨対象面を研磨パッド
5に対向するように設置され、研磨ヘッド3に保持される。研磨ヘッド3は、ウエハを回
転テーブル6に押圧可能な機構等が備えられている。
A semiconductor wafer is located below the polishing head 3. The wafer is placed so that the surface to be polished faces the polishing pad 5 and is held by the polishing head 3. The polishing head 3 includes a mechanism that can press the wafer against the rotary table 6.

回転テーブル6の上方にはスラリーを吐出するノズル4が配置されている。スラリーは
、例えば二酸化セリウムを砥粒としたものである。
A nozzle 4 for discharging slurry is disposed above the rotary table 6. The slurry is, for example, cerium dioxide as abrasive grains.

研磨処理時には、ノズル4から研磨パッド5上にスラリーを供給し、研磨ヘッド3を降
下させることによってウエハを研磨パッド5に接触させる。そして、回転テーブル6およ
び研磨ヘッド3を同一方向に回転させる。このようにして、ウエハ上に設けられた所定の
研磨対象材料を研磨することで半導体装置を製造する。
During the polishing process, slurry is supplied from the nozzle 4 onto the polishing pad 5 and the polishing head 3 is lowered to bring the wafer into contact with the polishing pad 5. Then, the rotary table 6 and the polishing head 3 are rotated in the same direction. In this way, a semiconductor device is manufactured by polishing a predetermined material to be polished provided on the wafer.

また、ドレッシング機構2には研磨パッド5側にドレッサー1が設けられている。ドレ
ッサー1は研磨パッド5と対向する面(作用面)にチップ部20の複数の突起22が位置
するように配置されている。ドレッシング機構2は、ウエハの研磨中または研磨前後にド
レッサー1を回転させ、ドレッサー1を揺動させながら研磨パッド5の目立てを行う。ド
レッシング機構2が設けられることで、ウエハの通過領域の表面を万遍なく目立てするこ
とが可能になる。
The dressing mechanism 2 is provided with a dresser 1 on the polishing pad 5 side. The dresser 1 is arranged such that a plurality of protrusions 22 of the tip portion 20 are located on the surface (working surface) facing the polishing pad 5. The dressing mechanism 2 rotates the dresser 1 during or before and after polishing the wafer, and sharpens the polishing pad 5 while swinging the dresser 1. By providing the dressing mechanism 2, the surface of the passing region of the wafer can be conspicuous uniformly.

以上、本実施形態に係るドレッサー1によれば、Si基板上にダイヤモンド薄膜層を成
膜するため、金属系の基板にダイヤモンド薄膜層を成膜する場合と比較して高温環境に強
いドレッサーを形成することが可能になる。例えば、ダイヤモンド薄膜層の成膜時に80
0度の高温環境下に晒した時に金属が溶出し、金属中の炭素が成長してすす状になると言
う問題を回避できる。また、Si基板とダイヤモンドの熱膨張係数が同程度のため、高温
環境下においてダイヤモンドとの熱膨張係数の差が大きいことによりダイヤモンド薄膜層
にクラックが発生してしまう虞を回避できる。
As described above, according to the dresser 1 according to the present embodiment, since the diamond thin film layer is formed on the Si substrate, the dresser resistant to a high temperature environment is formed as compared with the case where the diamond thin film layer is formed on the metal substrate. It becomes possible to do. For example, when a diamond thin film layer is formed, 80
It is possible to avoid the problem that the metal is eluted when exposed to a high temperature environment of 0 ° C., and the carbon in the metal grows to form soot. In addition, since the thermal expansion coefficients of the Si substrate and diamond are approximately the same, it is possible to avoid the possibility of cracks occurring in the diamond thin film layer due to a large difference in thermal expansion coefficient from diamond in a high temperature environment.

さらには、Si基板を円錐形状に加工し突起を形成するため、より効率的に研磨パッド
のドレッシングが可能になり、また、四角錐や他の突起形状と比較して、突起間に研磨パ
ッドの屑が溜まりにくくなる。
Furthermore, since the Si substrate is processed into a conical shape to form protrusions, the dressing of the polishing pad can be performed more efficiently. Also, compared to a quadrangular pyramid or other protrusion shapes, the polishing pad can be dressed between the protrusions. It becomes difficult to collect trash.

本実施形態に係るドレッサー1の製造方法によれば、Siウエハに突起を形成した後に
ダイシング工程により複数のチップ状にダイシングし、得たチップ部を台金に取り付ける
。そのため、一枚のウエハから製造できるドレッサーの数が多くなり、コストの削減が可
能になる。
According to the method for manufacturing the dresser 1 according to the present embodiment, after forming protrusions on the Si wafer, the wafer is diced into a plurality of chips by a dicing process, and the obtained chip portion is attached to the base metal. Therefore, the number of dressers that can be manufactured from a single wafer increases, and the cost can be reduced.

(第2の実施形態)
以下、第2の実施形態に係るドレッサーについて図8を用いて説明する。第2の実施形
態に係るドレッサーは第1の実施形態と比較して、台金とチップ部との間にチップ保持台
を用いるという点が異なる。
(Second Embodiment)
Hereinafter, the dresser according to the second embodiment will be described with reference to FIG. The dresser according to the second embodiment is different from the first embodiment in that a chip holder is used between the base metal and the chip portion.

図8に第2の実施形態に係るドレッサー1の構成を示す。なお、チップ部20の構造は
第1の実施形態と同様なためその説明は省略する。図8に示すように、本実施形態のドレ
ッサー1は台金10と、台金10上に設けられた複数のチップ保持台50を有し、各チッ
プ保持台50上にはそれぞれチップ部20を有する。
FIG. 8 shows the configuration of the dresser 1 according to the second embodiment. Since the structure of the chip part 20 is the same as that of the first embodiment, the description thereof is omitted. As shown in FIG. 8, the dresser 1 of the present embodiment has a base 10 and a plurality of chip holding bases 50 provided on the base 10, and chip parts 20 are respectively provided on the chip holding bases 50. Have.

チップ保持台50は例えばステンレス(SUS)等を含むがその材料は特に限定されな
い。台金10と同材料で構成され、台金10の一部分として一体化していても良い。また
、チップ保持台50の数は特に限定されず、少なくとも1つあればよい。なお、本実施形
態において、チップ保持台50を台金10の一部に含めても良い。
The chip holder 50 includes, for example, stainless steel (SUS), but the material is not particularly limited. The base metal 10 may be made of the same material and may be integrated as a part of the base metal 10. Further, the number of chip holding bases 50 is not particularly limited, and at least one chip holding base 50 is sufficient. In the present embodiment, the chip holder 50 may be included in a part of the base 10.

次に本実施形態のドレッサー1の製造方法について図9を用いて説明する。   Next, the manufacturing method of the dresser 1 of this embodiment is demonstrated using FIG.

まずチップ部20を作製する。なお、チップ部20の形成方法は第1の実施形態と同様
であるためその説明は省略する(図3、図4及び図6(a)図参照)。
First, the chip part 20 is produced. In addition, since the formation method of the chip | tip part 20 is the same as that of 1st Embodiment, the description is abbreviate | omitted (refer FIG.3, FIG4 and FIG.6 (a) figure).

次に、上記の方法で得たダイヤモンド薄膜層23が成膜されたチップ部20を突起22
形成面の裏面に樹脂を塗布し、チップ部20をチップ保持台50上に貼付する(図9(a
))。樹脂は例えばエポキシ樹脂とアミン系接着剤との混合剤を用いる。
Next, the tip portion 20 on which the diamond thin film layer 23 obtained by the above method is formed is formed as a protrusion 22.
Resin is applied to the back surface of the forming surface, and the chip portion 20 is stuck on the chip holding base 50 (FIG. 9A
)). As the resin, for example, a mixture of an epoxy resin and an amine adhesive is used.

最後に、チップ部20が貼付されたチップ保持台50を例えばネジ等を用いて台金10
に固定する。以上のようにして第2の実施形態のドレッサー1完成する。なお、固定方法
は特に限定されない。
Finally, the chip holder 50 to which the chip part 20 is attached is attached to the base 10 using, for example, screws.
Secure to. As described above, the dresser 1 of the second embodiment is completed. The fixing method is not particularly limited.

本実施形態に係るドレッサー1によれば、第1の実施形態と同様な効果を有し、かつチ
ップ部と台金との間にチップ保持台を有することによって、チップ部のみを研磨パッドに
作用させやすくなる。具体的には、研磨パッドが軟質な場合に台金からのチップ部の突出
量が小さいと台金にも研磨パッドが接触してしまい、研磨パッドに対するチップ部からの
圧力が台金に逃げる可能性がある。上記を回避するために、厚いSiウエハを用いてチッ
プ部の厚さを厚くする方法があるが、本実施形態では金属のチップ保持台を用いるためコ
ストを削減できる。
According to the dresser 1 according to the present embodiment, it has the same effect as that of the first embodiment, and by having the chip holding base between the chip part and the base metal, only the chip part acts on the polishing pad. It becomes easy to let you. Specifically, when the polishing pad is soft and the protrusion of the chip part from the base metal is small, the polishing pad comes into contact with the base metal, and the pressure from the chip part against the polishing pad can escape to the base metal. There is sex. In order to avoid the above, there is a method of increasing the thickness of the chip portion using a thick Si wafer. However, in this embodiment, since a metal chip holder is used, the cost can be reduced.

以上、本発明のいくつかの実施形態を説明したが、これらの実施形態は、例として提示
したものであり、発明の範囲を限定することは意図していない。これら新規な実施形態は
、その他の様々な形態で実施されることが可能であり、発明の要旨を逸脱しない範囲で、
種々の省略、置き換え、変更を行うことができる。これら実施形態やその変形は、発明の
範囲や要旨に含まれるとともに、特許請求の範囲に記載された発明とその均等の範囲に含
まれる。
As mentioned above, although some embodiment of this invention was described, these embodiment is shown as an example and is not intending limiting the range of invention. These novel embodiments can be implemented in various other forms, and without departing from the spirit of the invention,
Various omissions, replacements, and changes can be made. These embodiments and modifications thereof are included in the scope and gist of the invention, and are included in the invention described in the claims and the equivalents thereof.

1 ドレッサー
2 ドレッシング機構
3 研磨ヘッド
4 ノズル
5 研磨パッド
6 回転テーブル
10 台金
20 チップ部
21 基板
22 突起
23 ダイヤモンド薄膜層
30 下地膜
40 レジスト膜
50 チップ保持台
100 研磨装置
DESCRIPTION OF SYMBOLS 1 Dresser 2 Dressing mechanism 3 Polishing head 4 Nozzle 5 Polishing pad 6 Turntable 10 Base metal 20 Chip part 21 Substrate 22 Protrusion 23 Diamond thin film layer 30 Base film 40 Resist film 50 Chip holder 100 Polishing apparatus

Claims (13)

台金と、
前記台金上に設けられ、上部に突起を有し面方位が(111)面であるSi基板と前記
Si基板の前記突起上に設けられたダイヤモンド薄膜層とを含むチップ部と、
を有するドレッサー。
With the base metal,
A chip portion that is provided on the base metal and includes a Si substrate having a protrusion on the top and a plane orientation of (111) plane; and a diamond thin film layer provided on the protrusion of the Si substrate;
Having a dresser.
台金と、
前記台金上に複数設けられ、上部に突起を有するSi基板と前記Si基板の前記突起上
に設けられたダイヤモンド薄膜層とを含むチップ部と、
を有するドレッサー。
With the base metal,
A chip portion including a plurality of Si substrates provided on the base metal and having protrusions on the upper portion; and a diamond thin film layer provided on the protrusions of the Si substrate;
Having a dresser.
前記Si基板は面方位が(111)面であることを特徴とする請求項2に記載のドレッ
サー。
The dresser according to claim 2, wherein the Si substrate has a (111) plane.
前記台金は、前記チップ部との接合部が部分的に突出することを特徴とする請求項1乃
至3のいずれか1項に記載のドレッサー。
The dresser according to any one of claims 1 to 3, wherein the base metal partially protrudes from a joint portion with the chip portion.
前記突起の形状は、円錐形状であることを特徴とする請求項1乃至4のいずれか1項に
記載のドレッサー。
The dresser according to claim 1, wherein the shape of the protrusion is a conical shape.
表面に複数の突起を有するSi基板が個片化されたチップ部を用意し、
前記チップ部の前記突起上にダイヤモンド薄膜層を形成し、
台金上に前記ダイヤモンド薄膜層が形成された前記チップ部を設けるドレッサーの製造方
法。
Prepare a chip part in which a Si substrate having a plurality of protrusions on the surface is separated,
Forming a diamond thin film layer on the protrusion of the tip portion;
A method for manufacturing a dresser, wherein the tip portion having the diamond thin film layer formed on a base metal is provided.
前記個片化されたチップ部は複数用意され、前記複数のチップ部の前記突起上にダイヤモ
ンド薄膜層を形成した後、前記複数の前記チップ部を前記台金上に設けることを特徴とす
る請求項6に記載のドレッサーの製造方法。
A plurality of the chip parts divided into pieces are prepared, and after forming a diamond thin film layer on the protrusions of the plurality of chip parts, the plurality of chip parts are provided on the base metal. Item 7. A method for producing a dresser according to Item 6.
前記Si基板は面方位が(111)面であることを特徴とする請求項6または7に記載
のドレッサーの製造方法。
The method of manufacturing a dresser according to claim 6 or 7, wherein the Si substrate has a (111) plane orientation.
前記Si基板はSiウエハであることを特徴とする請求項6乃至8のいずれか1項に記
載のドレッサーの製造方法。
The method of manufacturing a dresser according to claim 6, wherein the Si substrate is a Si wafer.
前記突起の形状は、円錐形状であることを特徴とする請求項6乃至9のいずれか1項に
記載のドレッサーの製造方法。
The method for manufacturing a dresser according to claim 6, wherein the shape of the protrusion is a conical shape.
前記チップ部は、前記台金上に部分的に形成されたチップ保持台上に設けられることを
特徴とする請求項6乃至10のいずれか1項に記載のドレッサーの製造方法。
11. The dresser manufacturing method according to claim 6, wherein the chip portion is provided on a chip holding base partially formed on the base metal. 11.
前記Si基板表面の複数の突起は、エッチングによりそれぞれ同時に形成されることを特
徴とする請求項6乃至11のいずれか1項に記載のドレッサーの製造方法。
The method for manufacturing a dresser according to any one of claims 6 to 11, wherein the plurality of protrusions on the surface of the Si substrate are simultaneously formed by etching.
表面に複数の突起を有するSi基板が個片化された個々のチップ部の前記突起上にダイ
ヤモンド薄膜層が設けられ、前記個々のチップ部が台金上に設けられたドレッサーを用い
て、研磨パッドを目立てし、目立てされた研磨パッドを用いて半導体ウエハを研磨する半
導体装置の製造方法。
Using a dresser in which a diamond thin film layer is provided on the protrusions of each chip part obtained by dividing a Si substrate having a plurality of protrusions on the surface, and each chip part is provided on a base metal A method for manufacturing a semiconductor device, wherein a pad is sharpened and a semiconductor wafer is polished using the sharpened polishing pad.
JP2016164015A 2016-08-24 2016-08-24 Dresser, method of manufacturing dresser, and method of manufacturing semiconductor device Pending JP2018032745A (en)

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