JP2018026546A - Soft copper foil laminate film and manufacturing method therefor, capable of preventing circuit disconnection/short circuit - Google Patents

Soft copper foil laminate film and manufacturing method therefor, capable of preventing circuit disconnection/short circuit Download PDF

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Publication number
JP2018026546A
JP2018026546A JP2017137054A JP2017137054A JP2018026546A JP 2018026546 A JP2018026546 A JP 2018026546A JP 2017137054 A JP2017137054 A JP 2017137054A JP 2017137054 A JP2017137054 A JP 2017137054A JP 2018026546 A JP2018026546 A JP 2018026546A
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Prior art keywords
copper
layer
tie coat
coat layer
copper foil
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マン ヒュン イ
Man Hyung Lee
マン ヒュン イ
ハン グォン リュ
Han Gwon Ryu
ハン グォン リュ
ビョン キル ソン
Byeong Kil Song
ビョン キル ソン
ジュン ウン ヨム
Jung Eun Yeom
ジュン ウン ヨム
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LS Mtron Ltd
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LS Mtron Ltd
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    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00Apparatus or processes for manufacturing printed circuits
    • H05K3/10Apparatus or processes for manufacturing printed circuits in which conductive material is applied to the insulating support in such a manner as to form the desired conductive pattern
    • H05K3/108Apparatus or processes for manufacturing printed circuits in which conductive material is applied to the insulating support in such a manner as to form the desired conductive pattern by semi-additive methods; masks therefor
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00Apparatus or processes for manufacturing printed circuits
    • H05K3/02Apparatus or processes for manufacturing printed circuits in which the conductive material is applied to the surface of the insulating support and is thereafter removed from such areas of the surface which are not intended for current conducting or shielding
    • H05K3/06Apparatus or processes for manufacturing printed circuits in which the conductive material is applied to the surface of the insulating support and is thereafter removed from such areas of the surface which are not intended for current conducting or shielding the conductive material being removed chemically or electrolytically, e.g. by photo-etch process
    • CCHEMISTRY; METALLURGY
    • C23COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; CHEMICAL SURFACE TREATMENT; DIFFUSION TREATMENT OF METALLIC MATERIAL; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL; INHIBITING CORROSION OF METALLIC MATERIAL OR INCRUSTATION IN GENERAL
    • C23CCOATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; SURFACE TREATMENT OF METALLIC MATERIAL BY DIFFUSION INTO THE SURFACE, BY CHEMICAL CONVERSION OR SUBSTITUTION; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL
    • C23C14/00Coating by vacuum evaporation, by sputtering or by ion implantation of the coating forming material
    • C23C14/02Pretreatment of the material to be coated
    • C23C14/021Cleaning or etching treatments
    • C23C14/022Cleaning or etching treatments by means of bombardment with energetic particles or radiation
    • CCHEMISTRY; METALLURGY
    • C23COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; CHEMICAL SURFACE TREATMENT; DIFFUSION TREATMENT OF METALLIC MATERIAL; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL; INHIBITING CORROSION OF METALLIC MATERIAL OR INCRUSTATION IN GENERAL
    • C23CCOATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; SURFACE TREATMENT OF METALLIC MATERIAL BY DIFFUSION INTO THE SURFACE, BY CHEMICAL CONVERSION OR SUBSTITUTION; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL
    • C23C14/00Coating by vacuum evaporation, by sputtering or by ion implantation of the coating forming material
    • C23C14/06Coating by vacuum evaporation, by sputtering or by ion implantation of the coating forming material characterised by the coating material
    • C23C14/14Metallic material, boron or silicon
    • C23C14/16Metallic material, boron or silicon on metallic substrates or on substrates of boron or silicon
    • C23C14/165Metallic material, boron or silicon on metallic substrates or on substrates of boron or silicon by cathodic sputtering
    • CCHEMISTRY; METALLURGY
    • C23COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; CHEMICAL SURFACE TREATMENT; DIFFUSION TREATMENT OF METALLIC MATERIAL; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL; INHIBITING CORROSION OF METALLIC MATERIAL OR INCRUSTATION IN GENERAL
    • C23CCOATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; SURFACE TREATMENT OF METALLIC MATERIAL BY DIFFUSION INTO THE SURFACE, BY CHEMICAL CONVERSION OR SUBSTITUTION; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL
    • C23C14/00Coating by vacuum evaporation, by sputtering or by ion implantation of the coating forming material
    • C23C14/06Coating by vacuum evaporation, by sputtering or by ion implantation of the coating forming material characterised by the coating material
    • C23C14/14Metallic material, boron or silicon
    • C23C14/20Metallic material, boron or silicon on organic substrates
    • C23C14/205Metallic material, boron or silicon on organic substrates by cathodic sputtering
    • CCHEMISTRY; METALLURGY
    • C25ELECTROLYTIC OR ELECTROPHORETIC PROCESSES; APPARATUS THEREFOR
    • C25DPROCESSES FOR THE ELECTROLYTIC OR ELECTROPHORETIC PRODUCTION OF COATINGS; ELECTROFORMING; APPARATUS THEREFOR
    • C25D3/00Electroplating: Baths therefor
    • C25D3/02Electroplating: Baths therefor from solutions
    • C25D3/38Electroplating: Baths therefor from solutions of copper
    • CCHEMISTRY; METALLURGY
    • C25ELECTROLYTIC OR ELECTROPHORETIC PROCESSES; APPARATUS THEREFOR
    • C25DPROCESSES FOR THE ELECTROLYTIC OR ELECTROPHORETIC PRODUCTION OF COATINGS; ELECTROFORMING; APPARATUS THEREFOR
    • C25D5/00Electroplating characterised by the process; Pretreatment or after-treatment of workpieces
    • C25D5/34Pretreatment of metallic surfaces to be electroplated
    • CCHEMISTRY; METALLURGY
    • C25ELECTROLYTIC OR ELECTROPHORETIC PROCESSES; APPARATUS THEREFOR
    • C25DPROCESSES FOR THE ELECTROLYTIC OR ELECTROPHORETIC PRODUCTION OF COATINGS; ELECTROFORMING; APPARATUS THEREFOR
    • C25D7/00Electroplating characterised by the article coated
    • C25D7/06Wires; Strips; Foils
    • C25D7/0614Strips or foils
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00Printed circuits
    • H05K1/02Details
    • H05K1/09Use of materials for the conductive, e.g. metallic pattern
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00Printed circuits
    • H05K1/02Details
    • H05K1/11Printed elements for providing electric connections to or between printed circuits
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00Apparatus or processes for manufacturing printed circuits
    • H05K3/007Manufacture or processing of a substrate for a printed circuit board supported by a temporary or sacrificial carrier
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00Apparatus or processes for manufacturing printed circuits
    • H05K3/02Apparatus or processes for manufacturing printed circuits in which the conductive material is applied to the surface of the insulating support and is thereafter removed from such areas of the surface which are not intended for current conducting or shielding
    • H05K3/022Processes for manufacturing precursors of printed circuits, i.e. copper-clad substrates
    • H05K3/025Processes for manufacturing precursors of printed circuits, i.e. copper-clad substrates by transfer of thin metal foil formed on a temporary carrier, e.g. peel-apart copper
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00Apparatus or processes for manufacturing printed circuits
    • H05K3/38Improvement of the adhesion between the insulating substrate and the metal
    • H05K3/382Improvement of the adhesion between the insulating substrate and the metal by special treatment of the metal
    • H05K3/384Improvement of the adhesion between the insulating substrate and the metal by special treatment of the metal by plating
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2203/00Indexing scheme relating to apparatus or processes for manufacturing printed circuits covered by H05K3/00
    • H05K2203/03Metal processing
    • H05K2203/0307Providing micro- or nanometer scale roughness on a metal surface, e.g. by plating of nodules or dendrites

Abstract

PROBLEM TO BE SOLVED: To provide a soft copper foil laminate film and manufacturing method therefor, capable of preventing circuit disconnection and/or short-circuit by guaranteeing uniform chemical polishing.SOLUTION: A soft copper foil laminate film 100 includes a non-conductive polymer base material 110, a tie coat layer 120 on the non-conductive polymer base material and a copper layer 130 on the tie coat layer. When performing chemical polishing for decreasing the thickness of the copper layer by 1-2 μm, the polished copper layer has a surface roughness (Rz) of 0.1-0.15 μm and average copper crystal grains each of which has a size of not more than 2 μm in ND direction.SELECTED DRAWING: Figure 1

Description

本発明は軟性銅箔積層フィルムおよびその製造方法に関するもので、さらに具体的には、回路の断線および/または短絡を防止できる軟性銅箔積層フィルムおよびその製造方法に関するものである。   The present invention relates to a flexible copper foil laminated film and a method for producing the same, and more specifically, to a flexible copper foil laminated film capable of preventing circuit disconnection and / or short circuit and a method for producing the same.

ノートパソコン、携帯電話、PDA、小型ビデオカメラおよび電子手帳などの電子機器がますます小型化および軽量化されるにつれて、TAB(Tape Automated Bonding)、COF(Chip On Film)などに適用され得るフレキシブルプリント回路基板(Flexible Printed Circuit Board:FPCB)に対する需要が増加している。これに伴い、FPCB製造に利用される軟性銅箔積層フィルム(Flexible Copper Clad Laminate:FCCL)に対する需要も増加している。   Flexible printing that can be applied to TAB (Tape Automated Bonding), COF (Chip On Film), etc. as electronic devices such as notebook computers, mobile phones, PDAs, small video cameras and electronic notebooks become smaller and lighter. The demand for circuit boards (Flexible Printed Circuit Board: FPCB) is increasing. Accordingly, demand for flexible copper clad laminate (FCCL) used for FPCB production is also increasing.

軟性銅箔積層フィルムは非伝導性高分子膜と銅層の積層体であって、軟性銅箔積層フィルムの銅層を選択的に除去して前記非伝導性高分子膜上に所定の回路パターンを形成することによって、フレキシブルプリント回路基板を得ることができる。   The flexible copper foil laminated film is a laminate of a non-conductive polymer film and a copper layer, and a predetermined circuit pattern is formed on the non-conductive polymer film by selectively removing the copper layer of the flexible copper foil laminated film. By forming a flexible printed circuit board can be obtained.

軟性銅箔積層フィルムは、i)銅箔を製造した後、コーティングまたはラミネーティング工程を通じて前記銅箔上に非伝導性高分子膜を形成するか、またはii)非伝導性高分子膜上に銅を蒸着することによって形成され得る。後者の製造方法が非常に薄厚の銅層の形成を可能とする点で、前者の製造方法に比べて有利である。   The flexible copper foil laminated film is formed by i) forming a copper foil and then forming a nonconductive polymer film on the copper foil through a coating or laminating process, or ii) forming a copper on the nonconductive polymer film. Can be formed by vapor deposition. The latter manufacturing method is advantageous over the former manufacturing method in that a very thin copper layer can be formed.

前記軟性銅箔積層フィルムを利用して回路パターンを形成する方法としては、i)相対的に厚い厚さの初期銅層を形成した後、回路配線以外の残り部分を除去するサブトラクティブ(subtractive)方式と、ii)相対的に薄厚の初期銅層を形成した後、回路配線に対応する領域上に銅メッキ(以下、「銅パターンメッキ」)をさらに実施するセミ−アディティブ(semi−additive)方式がある。   As a method of forming a circuit pattern using the soft copper foil laminated film, i) a subtractive method of removing a remaining portion other than the circuit wiring after forming a relatively thick initial copper layer. And ii) a semi-additive method in which a relatively thin initial copper layer is formed and then copper plating (hereinafter referred to as “copper pattern plating”) is further performed on a region corresponding to the circuit wiring. There is.

より狭いピッチ(pitch)の具現ができるという点で、前記セミ−アディティブ方式が前記サブトラクティブ方式と比べて好まれている。   The semi-additive method is preferred over the subtractive method in that a narrower pitch can be realized.

前記セミ−アディティブ方式では、前記非伝導性高分子膜上に形成された銅層の厚さを減少させる化学的研磨工程が遂行される必要がある。   In the semi-additive method, it is necessary to perform a chemical polishing process for reducing the thickness of the copper layer formed on the non-conductive polymer film.

しかし、前記化学的研磨工程の遂行時に研磨速度が前記銅層の全体表面にかけて均一ではないため、前記銅層の一部領域において銅層の表面に凹凸が形成される問題が発生する。銅層の表面上に形成された凹凸は不均一な銅パターンメッキを誘発する。   However, since the polishing rate is not uniform over the entire surface of the copper layer when the chemical polishing process is performed, there is a problem that unevenness is formed on the surface of the copper layer in a partial region of the copper layer. Irregularities formed on the surface of the copper layer induce non-uniform copper pattern plating.

このような銅パターンメッキの不均一によって、回路パターンの形成時に除去されるべき銅層部分が完全に除去されずにその一部が残存することによって、回路の短絡が引き起こされるか、回路パターンの形成時に残存すべきである銅層部分が除去されることによって回路の断線が引き起こされる。   Due to such non-uniformity of the copper pattern plating, a portion of the copper layer that should be removed at the time of forming the circuit pattern is not completely removed and a part of the copper layer remains, thereby causing a short circuit of the circuit or the circuit pattern. The disconnection of the circuit is caused by removing the copper layer portion that should remain at the time of formation.

このような回路の短絡または断線は、フレキシブルプリント回路基板(FPCB)そのものはもちろん、それが適用される電子機器の歩留まりおよび信頼性を低下させる。   Such a short circuit or disconnection of the circuit reduces the yield and reliability of the electronic device to which the flexible printed circuit board (FPCB) itself is applied as well as the flexible printed circuit board (FPCB) itself.

したがって、本発明は前記のような関連技術の制限および短所に起因した問題点を防止できる軟性銅箔積層フィルムおよびその製造方法に関するものである。   Therefore, the present invention relates to a flexible copper foil laminated film that can prevent the problems caused by the limitations and disadvantages of the related art as described above and a method for producing the same.

本発明の一観点は、均一な化学的研磨を担保することによって回路の断線および/または短絡を防止できる軟性銅箔積層フィルムを提供することである。   One aspect of the present invention is to provide a flexible copper foil laminated film that can prevent disconnection and / or short circuit of a circuit by ensuring uniform chemical polishing.

本発明の他の観点は、均一な化学的研磨を担保することによって回路の断線および/または短絡を防止できる軟性銅箔積層フィルムの製造方法を提供することである。   Another aspect of the present invention is to provide a method for producing a flexible copper foil laminated film capable of preventing circuit disconnection and / or short circuit by ensuring uniform chemical polishing.

前記で言及された本発明の観点の他にも、本発明の他の特徴および利点が以下で説明されるか、そのような説明から本発明が属する技術分野で通常の知識を有した者に明確に理解できるであろう。   In addition to the aspects of the present invention referred to above, other features and advantages of the present invention are described below, or from such descriptions, to those of ordinary skill in the art to which the present invention belongs. It will be clearly understood.

前記のような本発明の一観点によって、第1面およびその反対側の第2面を有する非伝導性高分子基材(nonconductive polymer substrate);前記非伝導性高分子基材の前記第1面上の第1タイコート層(tiecoat layer);および前記第1タイコート層上の第1銅層(copper layer)を含むものの、前記第1銅層の厚さを1〜2μm減少させる化学的研磨を遂行する場合、前記研磨された第1銅層は0.1〜0.15μmの表面粗さ(Rz)および2μm以下のND(Normal Direction)方向の銅結晶粒平均大きさを有することを特徴とする、軟性銅箔積層フィルムが提供される。   According to one aspect of the present invention as described above, a nonconductive polymer substrate having a first surface and a second surface opposite thereto; the first surface of the nonconductive polymer substrate; A chemical polishing that includes a first tiecoat layer on the top; and a first copper layer on the first tiecoat layer, but reduces the thickness of the first copper layer by 1 to 2 μm. When the first copper layer is performed, the polished first copper layer has a surface roughness (Rz) of 0.1 to 0.15 μm and an average size of copper grains in the ND (Normal Direction) direction of 2 μm or less. A flexible copper foil laminated film is provided.

本発明の他の観点により、非伝導性高分子基材を準備する段階;前記非伝導性高分子基材の少なくとも一面上にタイコート層を形成する段階;スパッタリング工程を通じて前記タイコート層上に銅シード層を形成する段階;および前記銅シード層上に銅メッキ層を形成する段階を含むものの、前記タイコート層および前記銅シード層が形成されている前記非伝導性高分子基材を複数のメッキ槽を順次通過させる段階的電解メッキ(multistage electrolytic plating)を通じて前記銅メッキ層が形成され、前記メッキ槽のそれぞれから加えられる電流密度は0.5〜3ASDであり、前記メッキ槽から加えられる電流密度のうち最大電流密度は2.8〜3ASDであり、前記メッキ槽内の電解液の温度は34〜36℃に維持されることを特徴とする、軟性銅箔積層フィルムの製造方法が提供される。   According to another aspect of the present invention, providing a nonconductive polymer substrate; forming a tie coat layer on at least one surface of the nonconductive polymer substrate; and forming a tie coat layer on the tie coat layer through a sputtering process. Forming a copper seed layer; and forming a copper plating layer on the copper seed layer, wherein a plurality of the non-conductive polymer base material on which the tie coat layer and the copper seed layer are formed are provided. The copper plating layer is formed through multi-stage electroplating, and the current density applied from each of the plating baths is 0.5 to 3 ASD, and is applied from the plating bath. Among the current densities, the maximum current density is 2.8-3 ASD, and the temperature of the electrolyte in the plating tank is 34- There is provided a method for producing a flexible copper foil laminated film, which is maintained at 36 ° C.

前記のような本発明に対する一般的な記述は本発明を例示するか説明するためのものに過ぎず、本発明の権利範囲を制限しない。   The above general description of the present invention is only intended to illustrate or explain the present invention and does not limit the scope of the present invention.

本発明によれば、セミ−アディティブ方式を通じてフレキシブルプリント回路基板を製造することによって、より狭いピッチ(pitch)の回路パターンが具現できるだけでなく、回路の断線および/または短絡による製品の不良率を最小化することによって製品の生産性および信頼性を向上させることができる。   According to the present invention, by manufacturing a flexible printed circuit board through a semi-additive method, not only a circuit pattern with a narrower pitch can be realized, but also the defect rate of a product due to circuit disconnection and / or short circuit is minimized. Therefore, the productivity and reliability of the product can be improved.

添付された図面は、本発明の理解を助け、本明細書の一部を構成するためのものであって、本発明の実施例を例示し、発明の詳細な説明とともに本発明の原理を説明する。
本発明の一実施例に係る軟性銅箔積層フィルムの断面図である。 本発明の他の実施例による軟性銅箔積層フィルムの断面図である。 本発明の一実施例に係る軟性銅箔積層フィルムの製造方法を示す断面図である。 本発明の一実施例に係る軟性銅箔積層フィルムの製造方法を示す断面図である。 本発明の一実施例に係る軟性銅箔積層フィルムの製造方法を示す断面図である。 本発明の一実施例に係る軟性銅箔積層フィルムの製造方法を示す断面図である。 本発明の一実施例に係るフレキシブルプリント回路基板の製造方法を示す断面図である。 本発明の一実施例に係るフレキシブルプリント回路基板の製造方法を示す断面図である。 本発明の一実施例に係るフレキシブルプリント回路基板の製造方法を示す断面図である。 本発明の一実施例に係るフレキシブルプリント回路基板の製造方法を示す断面図である。 本発明の一実施例に係るフレキシブルプリント回路基板の製造方法を示す断面図である。 本発明の一実施例に係るフレキシブルプリント回路基板の製造方法を示す断面図である。 実施例1および比較例1のEBSD測定結果をそれぞれ示す写真である。 実施例1および比較例1のEBSD測定結果をそれぞれ示す写真である。
BRIEF DESCRIPTION OF THE DRAWINGS The accompanying drawings are included to assist in understanding and constitute a part of this specification, illustrate embodiments of the invention, and explain the principles of the invention together with a detailed description of the invention. To do.
It is sectional drawing of the flexible copper foil laminated film which concerns on one Example of this invention. It is sectional drawing of the flexible copper foil laminated film by the other Example of this invention. It is sectional drawing which shows the manufacturing method of the flexible copper foil laminated film which concerns on one Example of this invention. It is sectional drawing which shows the manufacturing method of the flexible copper foil laminated film which concerns on one Example of this invention. It is sectional drawing which shows the manufacturing method of the flexible copper foil laminated film which concerns on one Example of this invention. It is sectional drawing which shows the manufacturing method of the flexible copper foil laminated film which concerns on one Example of this invention. It is sectional drawing which shows the manufacturing method of the flexible printed circuit board based on one Example of this invention. It is sectional drawing which shows the manufacturing method of the flexible printed circuit board based on one Example of this invention. It is sectional drawing which shows the manufacturing method of the flexible printed circuit board based on one Example of this invention. It is sectional drawing which shows the manufacturing method of the flexible printed circuit board based on one Example of this invention. It is sectional drawing which shows the manufacturing method of the flexible printed circuit board based on one Example of this invention. It is sectional drawing which shows the manufacturing method of the flexible printed circuit board based on one Example of this invention. It is a photograph which shows the EBSD measurement result of Example 1 and Comparative Example 1, respectively. It is a photograph which shows the EBSD measurement result of Example 1 and Comparative Example 1, respectively.

以下、添付された図面を参照して本発明の実施例を詳細に説明する。   Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings.

本発明の技術的思想および範囲を逸脱しない範囲内で本発明の多様な変更および変形が可能であることは当業者に自明である。したがって、本発明は特許請求の範囲に記載された発明およびその均等な発明の範囲内に入る変更および変形をすべて含む。   It will be apparent to those skilled in the art that various modifications and variations can be made in the present invention without departing from the spirit or scope of the invention. Accordingly, this invention includes all modifications and variations that fall within the scope of the claimed invention and its equivalents.

図1は本発明の一実施例に係る軟性銅箔積層フィルムの断面図である。   FIG. 1 is a cross-sectional view of a flexible copper foil laminated film according to an embodiment of the present invention.

図1に例示された通り、本発明の軟性銅箔積層フィルム100は、第1面およびその反対側の第2面を有する非伝導性高分子基材(nonconductive polymer substrate)110、前記非伝導性高分子基材110の前記第1面上の第1タイコート層120、および前記第1タイコート層120上の第1銅層130を含む。   As illustrated in FIG. 1, the flexible copper foil laminated film 100 of the present invention includes a nonconductive polymer substrate 110 having a first surface and a second surface opposite to the first surface, the nonconductive polymer substrate 110. A first tie coat layer 120 on the first surface of the polymer substrate 110 and a first copper layer 130 on the first tie coat layer 120 are included.

前記非伝導性高分子基材110はポリイミドを含むことができ、ロールツーロール(roll−to−roll)装置の活用を可能にし、軟性銅箔積層フィルム100に軟性を付与するために10〜40μmの厚さを有することができる。   The non-conductive polymer substrate 110 may include polyimide and may be used in a roll-to-roll apparatus, and may be 10 to 40 μm to impart flexibility to the flexible copper foil laminate film 100. Can have a thickness of

前記第1タイコート層120は、相異する物質からなる非伝導性高分子基材110と第1銅層130との間の接着力を向上させるためにこれらの間に介在されたもので、ニッケル(Ni)、クロム(Cr)、モリブデン(Mo)、ニオブ(Nb)、鉄(Fe)またはこれらのうち2以上の混合物を含むことができる。   The first tie coat layer 120 is interposed between the non-conductive polymer substrate 110 made of different materials and the first copper layer 130 in order to improve the adhesion between them. Nickel (Ni), chromium (Cr), molybdenum (Mo), niobium (Nb), iron (Fe), or a mixture of two or more thereof may be included.

本発明の一実施例によれば、前記第1タイコート層120はニッケル合金である。例えば、前記第1タイコート層120はニッケルおよびクロムを含むことができ、前記第1タイコート層120内の前記クロムの含量は5〜25重量%であり得る。クロム含量が前記範囲から外れると非伝導性高分子基材110と第1銅層130との間に所望の界面接着力を確保できない。   According to an embodiment of the present invention, the first tie coat layer 120 is a nickel alloy. For example, the first tie coat layer 120 may include nickel and chromium, and the chromium content in the first tie coat layer 120 may be 5 to 25 wt%. If the chromium content is out of the above range, a desired interfacial adhesive force cannot be secured between the non-conductive polymer substrate 110 and the first copper layer 130.

本発明の一実施例によれば、前記第1タイコート層120は150〜300Åの厚さを有する。前記厚さが150Å未満であると、非伝導性高分子基材110と第1銅層130との間に所望の界面接着力を確保できず、前記厚さが300Åを超過すると後続の回路パターンの形成時に食刻されるべき部分が食刻されずに残存する危険が大きくなる。   According to an embodiment of the present invention, the first tie coat layer 120 has a thickness of 150 to 300 mm. If the thickness is less than 150 mm, a desired interfacial adhesive force cannot be secured between the non-conductive polymer substrate 110 and the first copper layer 130, and if the thickness exceeds 300 mm, a subsequent circuit pattern is obtained. There is a greater risk that the portion to be etched at the time of forming will remain without being etched.

図1に例示された通り、前記第1銅層130は、前記第1タイコート層120上の第1銅シード層131および前記第1銅シード層131上の第1銅メッキ層132を含むことができる。   As illustrated in FIG. 1, the first copper layer 130 includes a first copper seed layer 131 on the first tie coat layer 120 and a first copper plating layer 132 on the first copper seed layer 131. Can do.

前記第1銅シード層131はスパッタリング工程を通じて、500〜1,500Åの厚さを有するように形成され得、前記第1銅メッキ層132は電解メッキ工程を通じて1.8〜2.4μmの厚さを有するように形成され得る。前記第1銅シード層131は、ロールツーロール装置を活用して電解メッキ工程を遂行する時に電気配線として機能する。   The first copper seed layer 131 may be formed to have a thickness of 500-1500 through a sputtering process, and the first copper plating layer 132 may have a thickness of 1.8-2.4 μm through an electrolytic plating process. Can be formed. The first copper seed layer 131 functions as electrical wiring when performing an electrolytic plating process using a roll-to-roll apparatus.

本発明の軟性銅箔積層フィルム100は前記第1銅層130上の保護層(図示されず)をさらに含むことができる。前記保護層は前記第1銅層130の酸化および腐食を防止するためのものであり、有機物で形成され得る。   The flexible copper foil laminated film 100 of the present invention may further include a protective layer (not shown) on the first copper layer 130. The protective layer is for preventing oxidation and corrosion of the first copper layer 130 and may be formed of an organic material.

本発明の軟性銅箔積層フィルム100はセミ−アディティブ方式によるフレキシブルプリント回路基板の製造に適用されるためのものである。セミ−アディティブ方式によれば、前記第1銅層130の中で回路配線に対応する領域上にのみ電解メッキを通じて銅パターン層が追加的に形成される。したがって、このような追加のメッキ工程を遂行する前に、銅パターン層が形成されてはならない領域上にはメッキ防止のためのパターン、例えば感光性パターンを形成する工程が要求される。   The flexible copper foil laminated film 100 of the present invention is for application to the production of a flexible printed circuit board by a semi-additive method. According to the semi-additive method, a copper pattern layer is additionally formed through electrolytic plating only on a region corresponding to the circuit wiring in the first copper layer 130. Therefore, before performing such an additional plating process, a process for forming a pattern for preventing plating, for example, a photosensitive pattern, is required on a region where the copper pattern layer should not be formed.

前記感光性パターンと前記第1銅層130との間の接着力が不充分であると、前記感光性パターンが全体的または部分的に前記第1銅層130から剥離される危険がある。前記感光性パターンと前記第1銅層130との剥離は、微細回路パターン形成のための前記追加のメッキ工程を遂行する時に銅パターン層が所望しない所に形成される結果を引き起こす。   If the adhesive force between the photosensitive pattern and the first copper layer 130 is insufficient, there is a risk that the photosensitive pattern may be peeled from the first copper layer 130 in whole or in part. The peeling of the photosensitive pattern and the first copper layer 130 causes a copper pattern layer to be formed at an undesired place when performing the additional plating process for forming a fine circuit pattern.

したがって、前記感光性パターンと前記第1銅層130との間の接着力を向上させるために、前記感光性パターンを前記第1銅層130上に形成する前に前記第1銅層130の化学的研磨を遂行する。   Therefore, in order to improve the adhesive force between the photosensitive pattern and the first copper layer 130, the chemistry of the first copper layer 130 is formed before the photosensitive pattern is formed on the first copper layer 130. Perform mechanical polishing.

前述した通り、化学的研磨工程を遂行する時、研磨速度が前記第1銅層130の全体表面に亘って均一でないため、第1銅層130の一部領域において凹凸が形成される問題が発生する。第1銅層130の表面上に形成された凹凸は、銅パターン層形成のための電解メッキの不均一を誘発する。このような電解メッキの不均一によって、回路パターンの形成時に除去されなければならない銅層部分が完全に除去されずにその一部が残存することによって回路の短絡が引き起こされるか、回路パターンの形成時に残存すべきである銅層部分が除去されることによって回路の断線が引き起こされる。   As described above, when the chemical polishing process is performed, the polishing rate is not uniform over the entire surface of the first copper layer 130, so that a problem occurs that unevenness is formed in a part of the first copper layer 130. To do. The unevenness formed on the surface of the first copper layer 130 induces non-uniformity of the electrolytic plating for forming the copper pattern layer. Due to such non-uniform electroplating, the copper layer portion that must be removed during the formation of the circuit pattern is not completely removed and a part of the copper layer remains, thereby causing a short circuit of the circuit or formation of the circuit pattern. The disconnection of the circuit is caused by the removal of portions of the copper layer that should sometimes remain.

したがって、本発明によれば、前記第1銅層130の厚さを1〜2μm減少させる化学的研磨を遂行する場合、前記研磨された第1銅層130は0.1〜0.15μmの表面粗さ(Rz)および2μm以下のND(Normal Direction)方向の銅結晶粒平均大きさを有するようになる。すなわち、第1銅層130の化学的研磨後研磨された表面上に凹凸が存在しない。したがって、本発明の軟性銅箔積層フィルム100で軟性回路基板を製造する場合、回路の断線および/または短絡による不良を顕著に減少させることができ、その結果、製品の生産性および信頼性を向上させることができる。   Therefore, according to the present invention, when performing chemical polishing to reduce the thickness of the first copper layer 130 by 1 to 2 μm, the polished first copper layer 130 has a surface of 0.1 to 0.15 μm. It has a roughness (Rz) and an average size of copper crystal grains in the ND (Normal Direction) direction of 2 μm or less. That is, there is no unevenness on the surface of the first copper layer 130 that has been polished after chemical polishing. Therefore, when a flexible circuit board is manufactured using the flexible copper foil laminated film 100 of the present invention, defects due to circuit disconnection and / or short-circuiting can be significantly reduced, and as a result, product productivity and reliability are improved. Can be made.

前記第1銅層130の化学的研磨のために使われる銅食刻液は、プンウォン化学社のMFE−500(過酸化水素10重量%、硫酸23重量%、水67重量%)原液を20%に希釈することによって得られ、前記化学的研磨は常温(room temperature)で遂行される。   The copper etchant used for the chemical polishing of the first copper layer 130 is 20% of Pungwon Chemical's MFE-500 (hydrogen peroxide 10 wt%, sulfuric acid 23 wt%, water 67 wt%). The chemical polishing is performed at room temperature.

以下では、図2を参照して本発明の他の実施例に係る軟性銅箔積層フィルム100を説明する。   Below, with reference to FIG. 2, the flexible copper foil laminated film 100 which concerns on the other Example of this invention is demonstrated.

図2に例示された通り、本発明の他の実施例に係る軟性銅箔積層フィルム100は前記非伝導性高分子基材110の前記第2面上の第2タイコート層120aと前記第2タイコート層120a上の第2銅層130aをさらに含む。   As illustrated in FIG. 2, the flexible copper foil laminated film 100 according to another embodiment of the present invention includes a second tie coat layer 120a on the second surface of the non-conductive polymer substrate 110 and the second tie coat layer 120a. A second copper layer 130a on the tie coat layer 120a is further included.

前記第1タイコート層120と同じように、前記第2タイコート層120aもニッケルおよびクロムを含むものの、前記クロムの含量は5〜25重量%であり得、150〜300Åの厚さを有することができる。   Similar to the first tie coat layer 120, the second tie coat layer 120a also includes nickel and chromium, but the chromium content may be 5 to 25% by weight and has a thickness of 150 to 300%. Can do.

前記第2銅層130aは前記第2タイコート層120a上の第2銅シード層131aおよび前記第2銅シード層131a上の第2銅メッキ層132aを含む。前記第2銅シード層131aはスパッタリング工程を通じて500〜1,500Åの厚さを有するように形成され得、前記第2銅メッキ層132aは電解メッキ工程を通じて1.8〜2.4μmの厚さを有するように形成され得る。   The second copper layer 130a includes a second copper seed layer 131a on the second tie coat layer 120a and a second copper plating layer 132a on the second copper seed layer 131a. The second copper seed layer 131a may be formed to have a thickness of 500-1500 through a sputtering process, and the second copper plating layer 132a may have a thickness of 1.8-2.4 μm through an electrolytic plating process. It can be formed to have.

前記第1銅層130と同じように、前記第2銅層130aの厚さを1〜2μm減少させる化学的研磨を遂行する場合、研磨された第2銅層130aも0.1〜0.15μmの表面粗さ(Rz)および2μm以下のND方向の銅結晶粒平均大きさを有するようになる。   Similar to the first copper layer 130, when performing chemical polishing for reducing the thickness of the second copper layer 130 a by 1 to 2 μm, the polished second copper layer 130 a is also 0.1 to 0.15 μm. Surface roughness (Rz) and an average size of copper crystal grains in the ND direction of 2 μm or less.

以下では、図3〜図6を参照して、本発明の一実施例に係る軟性銅箔積層フィルム100の製造方法を具体的に説明する。   Below, with reference to FIGS. 3-6, the manufacturing method of the flexible copper foil laminated film 100 which concerns on one Example of this invention is demonstrated concretely.

まず、図3に例示された通り、非伝導性高分子基材110を準備する。   First, as illustrated in FIG. 3, a nonconductive polymer substrate 110 is prepared.

前記非伝導性高分子基材110は10〜40μmの厚さを有することができ、熱硬化性樹脂(例えば、フェノール樹脂、フェノールアルデヒド樹脂、アリル樹脂、エポキシ樹脂など)、ポリオレフィン樹脂(例えば、ポリエチレン樹脂、ポリプロピレン樹脂など)、ポリエステル樹脂(例えば、PET、PENなど)、またはポリイミド樹脂で形成され得る。   The non-conductive polymer substrate 110 may have a thickness of 10 to 40 μm, and may be a thermosetting resin (eg, phenol resin, phenol aldehyde resin, allyl resin, epoxy resin, etc.), polyolefin resin (eg, polyethylene). Resin, polypropylene resin, etc.), polyester resin (eg, PET, PEN, etc.), or polyimide resin.

好ましくは、前記非伝導性高分子基材110はポリイミド樹脂で形成される。例えば、ポリイミド前駆体であるポリアミック酸を圧出してフィルムを製造し、前記ポリアミック酸のイミド化のために前記フィルムを熱処理することによって、ポリイミドを含む非伝導性高分子基材110を製造することができる。   Preferably, the non-conductive polymer substrate 110 is formed of a polyimide resin. For example, a non-conductive polymer substrate 110 containing polyimide is manufactured by extruding a polyamic acid that is a polyimide precursor to produce a film, and heat-treating the film for imidization of the polyamic acid. Can do.

前記非伝導性高分子基材110の水分および残留ガスを除去するための乾燥段階が真空雰囲気で赤外線(IR)ヒーターを利用して50〜300℃で遂行され得る。赤外線(IR)ヒーターの温度が50℃未満であると水分をきちんと除去することができず、赤外線(IR)ヒーターの温度が300℃を超過すると非伝導性高分子基材110が損傷して品質低下が引き起こされる。   A drying process for removing moisture and residual gas from the non-conductive polymer substrate 110 may be performed at 50 to 300 ° C. using an infrared (IR) heater in a vacuum atmosphere. If the temperature of the infrared (IR) heater is less than 50 ° C., moisture cannot be removed properly, and if the temperature of the infrared (IR) heater exceeds 300 ° C., the non-conductive polymer substrate 110 is damaged and the quality is increased. A decline is caused.

前記乾燥段階後、前記非伝導性高分子基材110の表面上に存在し得る汚染物質を除去し、表面改質を通じて後続工程で形成されるタイコート層120との接着力を向上させるために、前記非伝導性高分子基材110はプラズマで処理され得る。   In order to remove contaminants that may be present on the surface of the non-conductive polymer substrate 110 after the drying step and improve adhesion with the tie coat layer 120 formed in a subsequent process through surface modification. The non-conductive polymer substrate 110 may be treated with plasma.

引き続き、図4に例示された通り、前記非伝導性高分子基材110の少なくとも一面上にタイコート層120を形成する。   Subsequently, as illustrated in FIG. 4, a tie coat layer 120 is formed on at least one surface of the non-conductive polymer substrate 110.

前記タイコート層120はDCスパッタリング装置を利用したスパッタリング工程を通じて150〜300Åの厚さを有するように形成され得る。前記タイコート層120の厚さが150Å未満である場合には、前記非伝導性高分子基材110と後続工程で形成される銅層130との間の接着力が不充分となる。反面、前記タイコート層120の厚さが300Åを超過する場合には、回路パターン形成のためのエッチング工程が遂行される時、除去されなければならないタイコート層120の一部が残存して回路の短絡が誘発される危険性が高まる。   The tie coat layer 120 may be formed to have a thickness of 150 to 300 mm through a sputtering process using a DC sputtering apparatus. When the thickness of the tie coat layer 120 is less than 150 mm, the adhesive force between the non-conductive polymer substrate 110 and the copper layer 130 formed in a subsequent process becomes insufficient. On the other hand, when the thickness of the tie coat layer 120 exceeds 300 mm, a part of the tie coat layer 120 that must be removed remains when the etching process for forming the circuit pattern is performed. The risk of inducing a short circuit is increased.

前述した通り、前記タイコート層120は前記非伝導性高分子基材110と後続工程で形成される銅層130の接着力を高めるためのものであって、ニッケル(Ni)、クロム(Cr)、モリブデン(Mo)、ニオブ(Nb)、鉄(Fe)またはこれらのうち2以上の混合物を含むことができる。   As described above, the tie coat layer 120 is for increasing the adhesion between the non-conductive polymer substrate 110 and the copper layer 130 formed in a subsequent process, and includes nickel (Ni) and chromium (Cr). , Molybdenum (Mo), niobium (Nb), iron (Fe), or a mixture of two or more thereof.

本発明の一実施例によれば、前記タイコート層120はニッケル合金である。例えば、前記タイコート層120はニッケルおよびクロムを含むことができ、前記タイコート層120内の前記クロムの含量は5〜25重量%であり得る。   According to an embodiment of the present invention, the tie coat layer 120 is a nickel alloy. For example, the tie coat layer 120 may include nickel and chromium, and the chromium content in the tie coat layer 120 may be 5 to 25 wt%.

前記スパッタリング装置の電力調節を通じて前記タイコート層120の密度が調節され得、チャンバーの真空度を調節することによってタイコート層120の酸素含量が調節され得る。   The density of the tie coat layer 120 may be adjusted through power adjustment of the sputtering apparatus, and the oxygen content of the tie coat layer 120 may be adjusted by adjusting the degree of vacuum in the chamber.

引き続き、前記タイコート層120上に銅層130を形成する。前記銅層130の形成段階は、図5に例示された通り、前記タイコート層120上に銅シード層131を形成する段階および図6に例示された通り、前記銅シード層131上に銅メッキ層132を形成する段階を含む。   Subsequently, a copper layer 130 is formed on the tie coat layer 120. The step of forming the copper layer 130 includes forming a copper seed layer 131 on the tie coat layer 120 as illustrated in FIG. 5 and copper plating on the copper seed layer 131 as illustrated in FIG. Forming a layer 132;

前記銅シード層131はDCスパッタリング装置を利用したスパッタリング工程を通じて500〜1,500Åの厚さを有するように形成され得、前記銅メッキ層132は電解メッキ工程を通じて1.8〜2.4μmの厚さを有するように形成され得る。   The copper seed layer 131 may be formed to have a thickness of 500 to 1,500 mm through a sputtering process using a DC sputtering apparatus, and the copper plating layer 132 may have a thickness of 1.8 to 2.4 μm through an electrolytic plating process. It can be formed to have a thickness.

以下では、前記銅メッキ層132形成のための本発明の電解メッキ工程をさらに具体的に説明する。   Hereinafter, the electrolytic plating process of the present invention for forming the copper plating layer 132 will be described in more detail.

前記タイコート層120および前記銅シード層131が形成されている前記非伝導性高分子基材110が30〜40g/Lの銅、170〜180g/Lの硫酸、および45〜55ppmのClを含む電解液が入れられている10〜20個のメッキ槽を順次通過することによって本発明の段階的電解メッキ(multistage electrolytic plating)が遂行される。   The non-conductive polymer substrate 110 on which the tie coat layer 120 and the copper seed layer 131 are formed includes 30 to 40 g / L copper, 170 to 180 g / L sulfuric acid, and 45 to 55 ppm Cl. The multistage electrolytic plating of the present invention is performed by sequentially passing through 10 to 20 plating tanks in which an electrolytic solution is placed.

前記銅層130の化学的研磨後、凹凸発生を防止するために、前記メッキ槽のそれぞれから加えられる電流密度は0.5〜3ASDであり、前記メッキ槽から加えられる電流密度のうち最大電流密度は2.8〜3ASDである。   In order to prevent unevenness after the copper layer 130 is chemically polished, the current density applied from each of the plating tanks is 0.5 to 3 ASD, and the maximum current density among the current densities applied from the plating tanks. Is 2.8-3 ASD.

本発明の一実施例によれば、前記段階的電解メッキを遂行する時に実施される順序によって各段階別に電流密度を増加させることができる。   According to an exemplary embodiment of the present invention, the current density may be increased for each step according to the order in which the stepwise electrolytic plating is performed.

本発明によれば、前記銅層130の化学的研磨後、凹凸発生を防止するために、前記メッキ槽内の電解液の温度は34〜36℃に維持される。   According to the present invention, after chemical polishing of the copper layer 130, the temperature of the electrolyte in the plating tank is maintained at 34 to 36 ° C. in order to prevent unevenness.

このような本発明の段階的電解メッキを通じて、化学的研磨時のエッチング速度の不均一を最大限抑制できる銅層130が製造され得る。また、前記銅層130の厚さを1〜2μm減少させる化学的研磨を遂行する場合、前記研磨された銅層130は0.1〜0.15μmの表面粗さ(Rz)および2μm以下のND方向の銅結晶粒平均大きさを有するようになる。すなわち、銅層130の化学的研磨後研磨された表面上に凹凸が存在しない。したがって、前記のように製造された本発明の軟性銅箔積層フィルム100で軟性回路基板を製造する場合、回路の断線および/または短絡による不良を顕著に減少させることができ、その結果、製品の生産性および信頼性を向上させることができる。   Through such stepwise electrolytic plating of the present invention, the copper layer 130 that can suppress the non-uniformity of the etching rate during chemical polishing to the maximum can be manufactured. In addition, when performing chemical polishing for reducing the thickness of the copper layer 130 by 1 to 2 μm, the polished copper layer 130 has a surface roughness (Rz) of 0.1 to 0.15 μm and an ND of 2 μm or less. It has a copper crystal grain average size in the direction. That is, there are no irregularities on the surface of the copper layer 130 that has been polished after chemical polishing. Accordingly, when a flexible circuit board is manufactured using the flexible copper foil laminated film 100 of the present invention manufactured as described above, defects due to circuit disconnection and / or short-circuiting can be remarkably reduced. Productivity and reliability can be improved.

以下では、図7〜図12を参照して、本発明の一実施例に係るフレキシブルプリント回路基板の製造方法を具体的に説明する。   Hereinafter, a method for manufacturing a flexible printed circuit board according to an embodiment of the present invention will be described in detail with reference to FIGS.

まず、前述のように製造された本発明の軟性銅箔積層フィルム100を準備する。   First, the flexible copper foil laminated film 100 of this invention manufactured as mentioned above is prepared.

引き続き、図8に例示された通り、前記銅層130[より正確には、前記銅メッキ層132]を銅食刻液を利用して化学的に研磨することによって前記銅層130の厚さを1〜2μmだけ減少させる。   Subsequently, as illustrated in FIG. 8, the thickness of the copper layer 130 is reduced by chemically polishing the copper layer 130 [more precisely, the copper plating layer 132] using a copper etching solution. Decrease by 1-2 μm.

本発明の一実施例によれば、前記銅メッキ層132の化学的研磨は銅食刻液を噴射することによって遂行されるものの、0.03〜0.04μm/secの食刻速度で25〜30秒の間遂行され得る。   According to an embodiment of the present invention, the chemical polishing of the copper plating layer 132 is performed by spraying a copper etching solution, but 25 to 25 at an etching rate of 0.03 to 0.04 μm / sec. Can be performed for 30 seconds.

研磨された銅層130’は0.5〜1.5μmの厚さを有することができる。研磨された銅層130’の厚さが0.5μm未満であるとエッチング不均一によって研磨された表面上に凹凸が形成される危険がある。   The polished copper layer 130 'may have a thickness of 0.5 to 1.5 [mu] m. If the polished copper layer 130 ′ has a thickness of less than 0.5 μm, there is a risk that irregularities are formed on the polished surface due to non-uniform etching.

引き続き、図9に例示された通り、研磨された銅層130’上に感光性パターン10を形成する。前記感光性パターン10は通常のフォトリソグラフィ工程を通じて遂行され得る。前記研磨された銅層130’は前記感光性パターン10でカバーされた第1部分と前記感光性パターン10でカバーされていない第2部分を含む。   Subsequently, as illustrated in FIG. 9, a photosensitive pattern 10 is formed on the polished copper layer 130 ′. The photosensitive pattern 10 may be performed through a normal photolithography process. The polished copper layer 130 ′ includes a first portion covered with the photosensitive pattern 10 and a second portion not covered with the photosensitive pattern 10.

引き続き、前記感光性パターンを利用して回路パターンを形成する。以下では、本発明の一実施例に係る回路パターン形成方法を説明する。   Subsequently, a circuit pattern is formed using the photosensitive pattern. Hereinafter, a circuit pattern forming method according to an embodiment of the present invention will be described.

まず、図10に例示された通り、電解メッキを実施することによって前記感光性パターン10でカバーされていない前記研磨された銅層130’の第2部分の表面上に8〜12μmの厚さを有する銅パターン層140を形成する。   First, as illustrated in FIG. 10, by performing electrolytic plating, a thickness of 8 to 12 μm is formed on the surface of the second portion of the polished copper layer 130 ′ not covered with the photosensitive pattern 10. The copper pattern layer 140 is formed.

引き続き、図11に例示された通り、通常のアッシング(ashing)工程を通じて感光性パターン10を除去する。   Subsequently, as illustrated in FIG. 11, the photosensitive pattern 10 is removed through a normal ashing process.

引き続き、図12に例示された通り、前記感光性パターン10でカバーされていた前記研磨された銅層130’の第1部分およびそれに対応するタイコート層120部分を選択的に除去することによって回路パターンを完成する。   Subsequently, as illustrated in FIG. 12, a circuit is formed by selectively removing the first portion of the polished copper layer 130 ′ and the corresponding tie coat layer 120 portion covered by the photosensitive pattern 10. Complete the pattern.

以下では、実施例および比較例を通じて本発明を具体的に説明する。ただし、下記の実施例は本発明の理解を助けるためのものに過ぎず、本発明の権利範囲はこれらの実施例に制限されない。   Hereinafter, the present invention will be described in detail through examples and comparative examples. However, the following examples are only for helping understanding of the present invention, and the scope of rights of the present invention is not limited to these examples.

実施例1〜6および比較例1〜12
ポリイミドフィルムを赤外線(IR)ヒーターで乾燥させた後プラズマ表面処理を遂行した。引き続き、スパッタリング工程を通じて200Å厚さのNiCrタイコート層を形成した。引き続き、スパッタリング工程を通じて700Å厚さの銅シード層を形成した。引き続き、下記の表1の相異する条件下で電解メッキを実施して2μm厚さの銅メッキ層を形成することによって、実施例1〜6および比較例1〜12の軟性銅箔積層フィルムを完成した。
Examples 1-6 and Comparative Examples 1-12
The polyimide film was dried with an infrared (IR) heater and then subjected to plasma surface treatment. Subsequently, a NiCr tie coat layer having a thickness of 200 mm was formed through a sputtering process. Subsequently, a copper seed layer having a thickness of 700 mm was formed through a sputtering process. Subsequently, by performing electrolytic plating under the different conditions shown in Table 1 to form a copper plating layer having a thickness of 2 μm, the flexible copper foil laminated films of Examples 1 to 6 and Comparative Examples 1 to 12 were formed. completed.

表1で最大電流密度は、メッキ槽からそれぞれ加えられる電流密度値のうち最大値を意味する。   The maximum current density in Table 1 means the maximum value among the current density values added from the plating tank.

前記の実施例および比較例によって製造された軟性銅箔積層フィルムに銅食刻液(プンウォン化学社のMFE−500、20%希釈)を噴射する化学的研磨を遂行して銅層の最終厚さ(すなわち、銅シード層の厚さ+銅メッキ層の厚さ)が0.8μmとなるようにした後、前記銅層の研磨された表面の表面粗さ(Rz)、ND方向の銅結晶粒平均大きさ、および凹凸発生の有無をそれぞれ測定または観察し、その結果を下記の表2に表わした。   The final thickness of the copper layer is achieved by performing chemical polishing by spraying a copper etching solution (Pungwon Chemical MFE-500, diluted 20%) onto the soft copper foil laminated film manufactured according to the above-described examples and comparative examples. (Ie, the thickness of the copper seed layer + the thickness of the copper plating layer) is 0.8 μm, and then the surface roughness (Rz) of the polished surface of the copper layer and the copper crystal grains in the ND direction The average size and the presence or absence of unevenness were measured or observed, and the results are shown in Table 2 below.

*表面粗さ(Rz)
AFM(Atomic Force Microscope)を利用して標準規格JIS B0601:1994に沿って接触式評価(測定面積:10μm×10μm)を遂行した。
* Surface roughness (Rz)
Contact type evaluation (measurement area: 10 μm × 10 μm) was performed according to the standard JIS B0601: 1994 using AFM (Atomic Force Microscope).

*ND方向の銅結晶粒平均大きさ
EBSD(Electron backscatter diffraction)装置を利用してND方向の銅結晶粒平均大きさを測定したが、ND方向の視野四方は300μmであり、ステップサイズは0.5μmであり、分析面積は25μm×25μmであった。解釈(算出)用のソフトウェアとしては、TSL社のOIMTMが使われた。図13aおよび図13bは実施例1および比較例1のEBSD測定結果をそれぞれ示す写真である。
* Average size of copper crystal grains in the ND direction The average size of copper crystal grains in the ND direction was measured using an EBSD (Electron Backscatter Diffraction) apparatus. The analysis area was 25 μm × 25 μm. OSLTM from TSL was used as interpretation (calculation) software. 13a and 13b are photographs showing the EBSD measurement results of Example 1 and Comparative Example 1, respectively.

*凹凸発生の有無
FIB(Focused Ion Beam)装置を利用(加速電圧:30kV、倍率:2000倍)して得られた断面形状を観察し、Cu粒子の不均一残留による突起が存在すると凹凸が発生したとみなした。
* Presence / absence of irregularities Observation of the cross-sectional shape obtained using an FIB (Focused Ion Beam) device (acceleration voltage: 30 kV, magnification: 2000 times), and irregularities occur when there are protrusions due to uneven residue of Cu particles. It was considered that.

表2からわかるように、銅メッキ層の形成のための電解メッキを遂行する時、最大電流密度が2.8〜3ASDから外れ、メッキ温度(すなわち、電解液の温度)が34〜36℃から外れる場合(比較例1、2、5−8、12)はもちろん、最大電流密度が2.8〜3ASDであってもメッキ温度(すなわち、電解液の温度)が34〜36℃から外れる場合(比較例3、4、9、10)にも、銅層の表面粗さ(Rz)が0.15μmを超過した。また、比較例1−6および8−11の場合には、ND方向の銅結晶粒平均大きさが2μmを超過した。結果的に、すべての比較例で化学的研磨後凹凸が発生した。   As can be seen from Table 2, when performing electroplating for forming a copper plating layer, the maximum current density deviates from 2.8 to 3 ASD, and the plating temperature (that is, the temperature of the electrolyte) is from 34 to 36 ° C. Of course, in the case of deviating (Comparative Examples 1, 2, 5-8, 12), even when the maximum current density is 2.8-3 ASD, the plating temperature (ie, the temperature of the electrolyte) deviates from 34-36 ° C. In Comparative Examples 3, 4, 9, and 10), the surface roughness (Rz) of the copper layer exceeded 0.15 μm. In Comparative Examples 1-6 and 8-11, the average size of the copper crystal grains in the ND direction exceeded 2 μm. As a result, unevenness occurred after chemical polishing in all the comparative examples.

100:軟性銅箔積層フィルム
110:非伝導性高分子基材
120:タイコート層
130:銅層
131:銅シード層
132:銅メッキ層
140:銅パターン層
DESCRIPTION OF SYMBOLS 100: Soft copper foil laminated film 110: Nonelectroconductive polymer base material 120: Tie coat layer 130: Copper layer 131: Copper seed layer 132: Copper plating layer 140: Copper pattern layer

Claims (10)

第1面およびその反対側の第2面を有する非伝導性高分子基材(nonconductive polymer substrate)、
前記非伝導性高分子基材の前記第1面上の第1タイコート層(tiecoat layer)、および
前記第1タイコート層上の第1銅層(copper layer)を含み、
前記第1銅層の厚さを1〜2μm減少させる化学的研磨を遂行する場合、前記研磨された第1銅層は0.1〜0.15μmの表面粗さ(Rz)および2μm以下のND(Normal Direction)方向の銅結晶粒平均大きさを有することを特徴とする、軟性銅箔積層フィルム。
A non-conductive polymer substrate having a first side and a second side opposite thereto,
A first tie coat layer on the first surface of the non-conductive polymer substrate; and a first copper layer on the first tie coat layer;
When performing chemical polishing to reduce the thickness of the first copper layer by 1 to 2 μm, the polished first copper layer has a surface roughness (Rz) of 0.1 to 0.15 μm and an ND of 2 μm or less. A soft copper foil laminated film having an average size of copper crystal grains in the (Normal Direction) direction.
前記非伝導性高分子基材はポリイミドを含み、10〜40μmの厚さを有することを特徴とする、請求項1に記載の軟性銅箔積層フィルム。   The flexible copper foil laminated film according to claim 1, wherein the non-conductive polymer substrate includes polyimide and has a thickness of 10 to 40 μm. 前記第1タイコート層はニッケル(Ni)、クロム(Cr)、モリブデン(Mo)、ニオブ(Nb)、鉄(Fe)またはこれらのうち2以上の混合物を含み、150〜300Åの厚さを有することを特徴とする、請求項1に記載の軟性銅箔積層フィルム。   The first tie coat layer includes nickel (Ni), chromium (Cr), molybdenum (Mo), niobium (Nb), iron (Fe), or a mixture of two or more thereof, and has a thickness of 150 to 300 mm. The flexible copper foil laminated film according to claim 1, wherein 前記第1タイコート層はニッケルおよびクロムを含み、
前記第1タイコート層内の前記クロムの含量は5〜25重量%であることを特徴とする、請求項3に記載の軟性銅箔積層フィルム。
The first tie coat layer includes nickel and chromium;
The soft copper foil laminate film according to claim 3, wherein the chromium content in the first tie coat layer is 5 to 25 wt%.
前記第1銅層は、
前記第1タイコート層上の第1銅シード層、
前記第1銅シード層上の第1銅メッキ層を含み、
前記第1銅シード層は500〜1,500Åの厚さを有し、
前記第1銅メッキ層は1.8〜2.4μmの厚さを有する、請求項1に記載の軟性銅箔積層フィルム。
The first copper layer is
A first copper seed layer on the first tie coat layer;
Including a first copper plating layer on the first copper seed layer;
The first copper seed layer has a thickness of 500 to 1,500 mm,
The flexible copper foil laminated film according to claim 1, wherein the first copper plating layer has a thickness of 1.8 to 2.4 μm.
前記非伝導性高分子基材の前記第2面上の第2タイコート層、および
前記第2タイコート層上の第2銅層をさらに含み、
前記第2銅層の厚さを1〜2μm減少させる化学的研磨を遂行する場合、前記研磨された第2銅層は0.1〜0.15μmの表面粗さ(Rz)および2μm以下のND方向の銅結晶粒平均大きさを有するようになる、請求項1に記載の軟性銅箔積層フィルム。
A second tie coat layer on the second surface of the non-conductive polymer substrate; and a second copper layer on the second tie coat layer;
When performing chemical polishing for reducing the thickness of the second copper layer by 1 to 2 μm, the polished second copper layer has a surface roughness (Rz) of 0.1 to 0.15 μm and an ND of 2 μm or less. The flexible copper foil laminated film according to claim 1, which has an average size of copper crystal grains in a direction.
非伝導性高分子基材を準備する段階、
前記非伝導性高分子基材の少なくとも一面上にタイコート層を形成する段階、
スパッタリング工程を通じて前記タイコート層上に銅シード層を形成する段階、および
前記銅シード層上に銅メッキ層を形成する段階を含み、
前記タイコート層および前記銅シード層が形成されている前記非伝導性高分子基材を複数のメッキ槽を順次通過させる段階的電解メッキ(multistage electrolytic plating)を通じて前記銅メッキ層が形成され、
前記メッキ槽のそれぞれから加えられる電流密度は0.5〜3ASDであり、
前記メッキ槽から加えられる電流密度のうち最大電流密度は2.8〜3ASDであり、
前記メッキ槽内の電解液の温度は34〜36℃に維持されることを特徴とする、軟性銅箔積層フィルムの製造方法。
Providing a non-conductive polymer substrate;
Forming a tie coat layer on at least one surface of the non-conductive polymer substrate;
Forming a copper seed layer on the tie coat layer through a sputtering process; and forming a copper plating layer on the copper seed layer;
The copper plating layer is formed through stepwise electrolytic plating in which the non-conductive polymer substrate on which the tie coat layer and the copper seed layer are formed is sequentially passed through a plurality of plating tanks.
The current density applied from each of the plating tanks is 0.5-3 ASD,
Of the current densities applied from the plating tank, the maximum current density is 2.8-3 ASD,
The method for producing a flexible copper foil laminated film, wherein the temperature of the electrolytic solution in the plating tank is maintained at 34 to 36 ° C.
前記製造方法は、前記タイコート層を形成する前に、
前記非伝導性高分子基材から水分および残留ガスを除去する段階、および
引き続き、前記非伝導性高分子基材の少なくとも一面をプラズマで処理する段階をさらに含み、
前記タイコート層はスパッタリング工程を通じて形成され、ニッケル(Ni)、クロム(Cr)、モリブデン(Mo)、ニオブ(Nb)、鉄(Fe)またはこれらのうち2以上の混合物を含み、150〜300Åの厚さを有することを特徴とする、請求項7に記載の軟性銅箔積層フィルムの製造方法。
In the manufacturing method, before forming the tie coat layer,
Removing water and residual gas from the non-conductive polymer substrate, and subsequently treating at least one surface of the non-conductive polymer substrate with plasma,
The tie coat layer is formed through a sputtering process, and includes nickel (Ni), chromium (Cr), molybdenum (Mo), niobium (Nb), iron (Fe), or a mixture of two or more thereof. It has thickness, The manufacturing method of the flexible copper foil laminated | multilayer film of Claim 7 characterized by the above-mentioned.
前記タイコート層はニッケルおよびクロムを含み、
前記タイコート層内の前記クロムの含量は5〜25重量%であることを特徴とする、請求項8に記載の軟性銅箔積層フィルムの製造方法。
The tie coat layer includes nickel and chromium;
The method for producing a flexible copper foil laminated film according to claim 8, wherein the chromium content in the tie coat layer is 5 to 25 wt%.
前記段階的電解メッキを遂行する時に実施される順序により各段階別に電流密度が増加し、
前記メッキ槽内の電解液のそれぞれは30〜40g/Lの銅、170〜180g/Lの硫酸、および45〜55ppmのClを含むことを特徴とする、請求項7に記載の軟性銅箔積層フィルムの製造方法。
The current density is increased for each step according to the order performed when performing the stepwise electrolytic plating,
8. The flexible copper foil laminate according to claim 7, wherein each of the electrolytes in the plating tank contains 30 to 40 g / L of copper, 170 to 180 g / L of sulfuric acid, and 45 to 55 ppm of Cl. 9. A method for producing a film.
JP2017137054A 2016-08-11 2017-07-13 Soft copper foil laminate film and manufacturing method therefor, capable of preventing circuit disconnection/short circuit Pending JP2018026546A (en)

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