JP2017525239A5 - - Google Patents

Download PDF

Info

Publication number
JP2017525239A5
JP2017525239A5 JP2016574266A JP2016574266A JP2017525239A5 JP 2017525239 A5 JP2017525239 A5 JP 2017525239A5 JP 2016574266 A JP2016574266 A JP 2016574266A JP 2016574266 A JP2016574266 A JP 2016574266A JP 2017525239 A5 JP2017525239 A5 JP 2017525239A5
Authority
JP
Japan
Prior art keywords
wires
wire
delay
delay element
signal propagation
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP2016574266A
Other languages
English (en)
Japanese (ja)
Other versions
JP6556762B2 (ja
JP2017525239A (ja
Filing date
Publication date
Priority claimed from US14/315,142 external-priority patent/US9319218B2/en
Application filed filed Critical
Publication of JP2017525239A publication Critical patent/JP2017525239A/ja
Publication of JP2017525239A5 publication Critical patent/JP2017525239A5/ja
Application granted granted Critical
Publication of JP6556762B2 publication Critical patent/JP6556762B2/ja
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

JP2016574266A 2014-06-25 2015-06-23 ワイヤペア間の整合された伝搬遅延を伴うマルチワイヤシグナリング Active JP6556762B2 (ja)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US14/315,142 2014-06-25
US14/315,142 US9319218B2 (en) 2014-06-25 2014-06-25 Multi-wire signaling with matched propagation delay among wire pairs
PCT/US2015/037132 WO2015200292A1 (en) 2014-06-25 2015-06-23 Multi-wire signaling with matched propagation delay among wire pairs

Publications (3)

Publication Number Publication Date
JP2017525239A JP2017525239A (ja) 2017-08-31
JP2017525239A5 true JP2017525239A5 (enExample) 2018-07-19
JP6556762B2 JP6556762B2 (ja) 2019-08-07

Family

ID=53610995

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2016574266A Active JP6556762B2 (ja) 2014-06-25 2015-06-23 ワイヤペア間の整合された伝搬遅延を伴うマルチワイヤシグナリング

Country Status (5)

Country Link
US (1) US9319218B2 (enExample)
EP (1) EP3162012B1 (enExample)
JP (1) JP6556762B2 (enExample)
CN (1) CN106464298B (enExample)
WO (1) WO2015200292A1 (enExample)

Families Citing this family (25)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US9521058B2 (en) 2014-06-25 2016-12-13 Qualcomm Incorporated Multi-wire signaling with matched propagation delay among wire pairs
US9112550B1 (en) 2014-06-25 2015-08-18 Kandou Labs, SA Multilevel driver for high speed chip-to-chip communications
US9432082B2 (en) 2014-07-17 2016-08-30 Kandou Labs, S.A. Bus reversable orthogonal differential vector signaling codes
US9882653B2 (en) * 2015-04-10 2018-01-30 Arista Networks, Inc. System and method of de-skewing electrical signals
KR20170007969A (ko) * 2015-07-13 2017-01-23 에스케이하이닉스 주식회사 고속 통신을 위한 인터페이스 회로 및 이를 포함하는 시스템
US9812057B2 (en) * 2015-08-05 2017-11-07 Qualcomm Incorporated Termination circuit to reduce attenuation of signal between signal producing circuit and display device
TWI787166B (zh) * 2016-03-01 2022-12-21 日商新力股份有限公司 信號之發送裝置、信號之發送方法及通信系統
US20170289410A1 (en) * 2016-03-30 2017-10-05 Intel Corporation Device, system and method to mitigate loss of signal integrity in a communication of image information
WO2017180281A1 (en) * 2016-04-12 2017-10-19 Qualcomm Incorporated Multi-wire signaling with matched propagation delay among wire pairs
CN109313622B (zh) * 2016-04-28 2022-04-15 康杜实验室公司 用于密集路由线组的向量信令码
US10153591B2 (en) 2016-04-28 2018-12-11 Kandou Labs, S.A. Skew-resistant multi-wire channel
US10419246B2 (en) * 2016-08-31 2019-09-17 Qualcomm Incorporated C-PHY training pattern for adaptive equalization, adaptive edge tracking and delay calibration
US10389513B2 (en) * 2017-01-26 2019-08-20 Hewlett Packard Enterprise Development Lp Dynamic adjustment of wait time values
US10819499B2 (en) * 2017-02-28 2020-10-27 Kandou Labs, S.A. Method for measuring and correcting multiwire skew
US10284361B2 (en) * 2017-05-05 2019-05-07 Mediatek Inc. Channel skew calibration method and associated receiver and system
TWI645297B (zh) * 2017-05-26 2018-12-21 聚晶半導體股份有限公司 資料傳輸系統
US10686583B2 (en) 2017-07-04 2020-06-16 Kandou Labs, S.A. Method for measuring and correcting multi-wire skew
KR102423987B1 (ko) 2017-09-21 2022-07-22 삼성전자주식회사 터미네이션 회로 및 인터페이스 장치
US10243614B1 (en) 2018-01-26 2019-03-26 Kandou Labs, S.A. Method and system for calibrating multi-wire skew
KR102389071B1 (ko) 2018-06-11 2022-04-22 칸도우 랩스 에스에이 직교 차동 벡터 시그널링 코드들에 대한 스큐 검출 및 보정
KR20210088807A (ko) 2020-01-06 2021-07-15 삼성전자주식회사 전자 장치 및 전자 장치의 동작 방법
US11463233B2 (en) 2020-05-21 2022-10-04 Qualcomm Incorporated Unit interval jitter improvement in a C-PHY interface
JP7449785B2 (ja) * 2020-06-17 2024-03-14 日立Astemo株式会社 電子制御装置、判定方法
US11764733B2 (en) * 2021-09-23 2023-09-19 Qualcomm Incorporated C-PHY receiver with self-regulated common mode servo loop
CN117408219B (zh) * 2023-12-14 2024-03-26 西安智多晶微电子有限公司 一种DDR信号Rtt端接PCB板级布局布线约束方法及电子设备

Family Cites Families (28)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4556850A (en) * 1982-11-01 1985-12-03 United Technologies Corporation Serial to parallel data conversion circuit
JP2892732B2 (ja) * 1990-01-12 1999-05-17 株式会社日立製作所 集積回路装置
US6005895A (en) 1996-12-20 1999-12-21 Rambus Inc. Apparatus and method for multilevel signaling
JP3209720B2 (ja) * 1997-08-04 2001-09-17 松下電器産業株式会社 複数伝送線路間の遅延時間の調整装置及び調整方法
US7035269B2 (en) * 2000-02-02 2006-04-25 Mcgill University Method and apparatus for distributed synchronous clocking
US6680636B1 (en) * 2000-03-31 2004-01-20 Silicon Graphics, Inc. Method and system for clock cycle measurement and delay offset
US6621369B2 (en) * 2001-11-30 2003-09-16 Nokia Corporation Method and system for determining transmission path delay
JP2003316736A (ja) * 2002-04-19 2003-11-07 Oki Electric Ind Co Ltd Ｕｓｂ回路およびデータ構造
US7020792B2 (en) * 2002-04-30 2006-03-28 Intel Corporation Method and apparatus for time domain equalization
TW592402U (en) * 2002-12-25 2004-06-11 Lorom Ind Co Ltd Cable distribution plate
JP2004327797A (ja) * 2003-04-25 2004-11-18 Toshiba Corp 半導体集積回路装置及び半導体集積回路装置を用いたシステム
EP1608112B1 (en) * 2004-06-14 2011-02-23 Broadcom Corporation Differential delay compensation and measurement in bonded systems
JP4543981B2 (ja) * 2005-03-22 2010-09-15 日本電気株式会社 時間差調整回路及び方法
JP2007116263A (ja) * 2005-10-18 2007-05-10 Orion Denki Kk 電子装置及びデータ通信制御方法
CN101162922A (zh) 2006-10-13 2008-04-16 国际商业机器公司 用于补偿多个通信通道的延时的方法和装置
US8064535B2 (en) 2007-03-02 2011-11-22 Qualcomm Incorporated Three phase and polarity encoded serial interface
US9231790B2 (en) 2007-03-02 2016-01-05 Qualcomm Incorporated N-phase phase and polarity encoded serial interface
US9711041B2 (en) 2012-03-16 2017-07-18 Qualcomm Incorporated N-phase polarity data transfer
US9112815B2 (en) 2012-06-15 2015-08-18 Qualcomm Incorporated Three-phase-polarity safe reverse link shutdown
US20080273486A1 (en) * 2007-04-13 2008-11-06 Hart Communication Foundation Wireless Protocol Adapter
JP2008294795A (ja) * 2007-05-25 2008-12-04 Panasonic Corp 差動伝送回路
US7859356B2 (en) 2008-03-21 2010-12-28 Qualcomm Incorporated Transmission line system having high common mode impedance
EP2339476B1 (en) * 2009-12-07 2012-08-15 STMicroelectronics (Research & Development) Limited Interface connecting dies in an IC package
JP5036843B2 (ja) * 2010-04-09 2012-09-26 富士通コンポーネント株式会社 自動調整システム、自動調整装置及び自動調整方法
US20140112401A1 (en) 2012-06-15 2014-04-24 Qualcomm Incorporated 3dynamic configuration of an n-phase polarity data communications link
US8996740B2 (en) 2012-06-29 2015-03-31 Qualcomm Incorporated N-phase polarity output pin mode multiplexer
US9008215B2 (en) 2012-06-29 2015-04-14 North Carolina State University Methods, systems, and computer program products for asymmetric multimode interconnect
US20150012718A1 (en) * 2013-07-04 2015-01-08 Atul Gupta System for compensating for dynamic skew in memory devices

Similar Documents

Publication Publication Date Title
JP2017525239A5 (enExample)
JP2015527797A5 (enExample)
JP2015198365A5 (enExample)
JP2016219090A5 (enExample)
JP2017511247A5 (enExample)
JP2013102553A5 (enExample)
MX2018013838A (es) Aparatos y métodos para detectar la temperatura a lo largo de un sondeo utilizando módulos sensores de temperatura conectados por una matriz.
JP2017533457A5 (enExample)
EP3488436A4 (en) EMISSION CONTROL CIRCUIT, DISPLAY DEVICE THEREFOR AND CONTROL METHOD THEREFOR
RU2021108046A (ru) Способы и устройства для сигнализации индекса порта для сигнала обратной связи информации о состоянии канала (csi) без индикатора матрицы прекодера (pmi)
EP3291215A4 (en) Scanning driving circuit and driving method therefor, array substrate and display apparatus
MX2016016653A (es) Aparato interruptor electrico, y puente y metodo asociado para el mismo.
JP2019512675A5 (enExample)
WO2015153790A8 (en) Low power software defined radio (sdr)
WO2016115056A3 (en) A novel high speed signal routing topology for better signal quality
JP2016167808A5 (enExample)
JP2016510195A5 (enExample)
JP2016541063A5 (enExample)
MX2016011262A (es) Aparatos, métodos, y sistemas para sistemas de comunicación de red multimedia de solución de problemas.
JP2019212294A5 (enExample)
WO2015061345A3 (en) Directionally controllable parametric emitter
JP2017208710A5 (enExample)
JP2012000954A5 (enExample)
IT201900016193A1 (it) Dispositivo di potenza, sistema includente il dispositivo di potenza, metodo di fabbricazione del dispositivo di potenza e metodo di controllo del dispositivo di potenza
JP2014178433A5 (enExample)