JP2017523640A - 低電力および高性能レシーバに関するオフセット較正 - Google Patents

低電力および高性能レシーバに関するオフセット較正 Download PDF

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Publication number
JP2017523640A
JP2017523640A JP2016570081A JP2016570081A JP2017523640A JP 2017523640 A JP2017523640 A JP 2017523640A JP 2016570081 A JP2016570081 A JP 2016570081A JP 2016570081 A JP2016570081 A JP 2016570081A JP 2017523640 A JP2017523640 A JP 2017523640A
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voltage
latch
offset
output
input
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JP2016570081A
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Japanese (ja)
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JP2017523640A5 (OSRAM
Inventor
ミンハン・チェン
ケネス・ルイス・アルクディア
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クアルコム，インコーポレイテッド
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Publication of JP2017523640A publication Critical patent/JP2017523640A/ja
Publication of JP2017523640A5 publication Critical patent/JP2017523640A5/ja
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    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K5/00—Manipulating of pulses not covered by one of the other main groups of this subclass
    • H03K5/003—Changing the DC level
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04B—TRANSMISSION
    • H04B1/00—Details of transmission systems, not covered by a single one of groups H04B3/00 - H04B13/00; Details of transmission systems not characterised by the medium used for transmission
    • H04B1/06—Receivers
    • H04B1/16—Circuits
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L25/00—Baseband systems
    • H04L25/02—Details ; arrangements for supplying electrical power along data transmission lines
    • H04L25/0264—Arrangements for coupling to transmission lines
    • H04L25/0272—Arrangements for coupling to multiple lines, e.g. for differential transmission
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L25/00—Baseband systems
    • H04L25/02—Details ; arrangements for supplying electrical power along data transmission lines
    • H04L25/0264—Arrangements for coupling to transmission lines
    • H04L25/0292—Arrangements specific to the receiver end
    • H04L25/0296—Arrangements to ensure DC-balance
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L25/00—Baseband systems
    • H04L25/02—Details ; arrangements for supplying electrical power along data transmission lines
    • H04L25/03—Shaping networks in transmitter or receiver, e.g. adaptive shaping networks
    • H04L25/03006—Arrangements for removing intersymbol interference
    • H04L25/03012—Arrangements for removing intersymbol interference operating in the time domain
    • H04L25/03019—Arrangements for removing intersymbol interference operating in the time domain adaptive, i.e. capable of adjustment during data reception
    • H04L25/03057—Arrangements for removing intersymbol interference operating in the time domain adaptive, i.e. capable of adjustment during data reception with a recursive structure
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L25/00—Baseband systems
    • H04L25/02—Details ; arrangements for supplying electrical power along data transmission lines
    • H04L25/06—DC level restoring means; Bias distortion correction ; Decision circuits providing symbol by symbol detection
    • H04L25/061—DC level restoring means; Bias distortion correction ; Decision circuits providing symbol by symbol detection providing hard decisions only; arrangements for tracking or suppressing unwanted low frequency components, e.g. removal of DC offset

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  • Engineering & Computer Science (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Signal Processing (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Nonlinear Science (AREA)
  • Amplifiers (AREA)
  • Analogue/Digital Conversion (AREA)
  • Dc Digital Transmission (AREA)
JP2016570081A 2014-06-06 2015-05-11 低電力および高性能レシーバに関するオフセット較正 Pending JP2017523640A (ja)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US14/298,718 US9385695B2 (en) 2014-06-06 2014-06-06 Offset calibration for low power and high performance receiver
US14/298,718 2014-06-06
PCT/US2015/030209 WO2015187307A1 (en) 2014-06-06 2015-05-11 Offset calibration for low power and high performance receiver

Publications (2)

Publication Number Publication Date
JP2017523640A true JP2017523640A (ja) 2017-08-17
JP2017523640A5 JP2017523640A5 (OSRAM) 2018-06-14

Family

ID=53396546

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2016570081A Pending JP2017523640A (ja) 2014-06-06 2015-05-11 低電力および高性能レシーバに関するオフセット較正

Country Status (6)

Country Link
US (2) US9385695B2 (OSRAM)
EP (1) EP3152878A1 (OSRAM)
JP (1) JP2017523640A (OSRAM)
KR (1) KR20170016841A (OSRAM)
CN (1) CN106464237B (OSRAM)
WO (1) WO2015187307A1 (OSRAM)

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US10341145B2 (en) * 2015-03-03 2019-07-02 Intel Corporation Low power high speed receiver with reduced decision feedback equalizer samplers
US9722828B2 (en) * 2015-09-23 2017-08-01 Qualcomm Incorporated Switch capacitor decision feedback equalizer with internal charge summation
US10572416B1 (en) * 2016-03-28 2020-02-25 Aquantia Corporation Efficient signaling scheme for high-speed ultra short reach interfaces
US10181969B2 (en) * 2016-12-08 2019-01-15 Intel Corporation High performance receiver with single calibration voltage
US10348482B1 (en) * 2017-05-22 2019-07-09 Juniper Networks, Inc Apparatus, system, and method for mitigating crosstalk among SerDes devices
US10079698B1 (en) * 2017-05-31 2018-09-18 Qualcomm Incorporated Apparatus and method for calibrating a receiver with a decision feedback equalizer (DFE)
US11855056B1 (en) 2019-03-15 2023-12-26 Eliyan Corporation Low cost solution for 2.5D and 3D packaging using USR chiplets
US11469729B2 (en) * 2019-06-11 2022-10-11 Mediatek Singapore Pte. Ltd. Hybrid receiver front-end
KR102658272B1 (ko) * 2020-05-21 2024-04-17 에스케이하이닉스 주식회사 신호 수신 회로 및 신호 수신 회로의 오프셋 측정 방법
CN111769889A (zh) * 2020-06-18 2020-10-13 上海闻泰信息技术有限公司 射频功率校正方法、装置、测试设备和存储介质
US11483184B2 (en) 2020-12-11 2022-10-25 Intel Corporation Multi pulse amplitude modulation signaling decision feedback equalizer having power differentiating modes and tap-weight re-configuration
US11855043B1 (en) 2021-05-06 2023-12-26 Eliyan Corporation Complex system-in-package architectures leveraging high-bandwidth long-reach die-to-die connectivity over package substrates
US12438095B1 (en) 2021-05-06 2025-10-07 Eliyan Corp. Complex system-in-package architectures leveraging high-bandwidth long-reach die-to-die connectivity over package substrates
US12204794B1 (en) 2021-05-18 2025-01-21 Eliyan Corporation Architecture for DRAM control optimization using simultaneous bidirectional memory interfaces
KR102865021B1 (ko) * 2021-05-24 2025-09-29 삼성전자주식회사 실시간으로 전압 오프셋을 제거하는 수신기 및 그것의 동작 방법
EP4175239A1 (en) * 2021-10-26 2023-05-03 Samsung Electronics Co., Ltd. Continuous time linear equalizer and device including the same
US12190038B1 (en) 2021-11-25 2025-01-07 Eliyan Corporation Multi-chip module (MCM) with multi-port unified memory
US11842986B1 (en) 2021-11-25 2023-12-12 Eliyan Corporation Multi-chip module (MCM) with interface adapter circuitry
US11841815B1 (en) 2021-12-31 2023-12-12 Eliyan Corporation Chiplet gearbox for low-cost multi-chip module applications
US12080379B2 (en) 2022-01-13 2024-09-03 Samsung Electronics Co., Ltd. Semiconductor device
US12248419B1 (en) 2022-05-26 2025-03-11 Eliyan Corporation Interface conversion circuitry for universal chiplet interconnect express (UCIe)
US12395386B2 (en) * 2022-10-20 2025-08-19 Samsung Electronics Co., Ltd. Electronic device and offset calibration method
US12058874B1 (en) 2022-12-27 2024-08-06 Eliyan Corporation Universal network-attached memory architecture
US12362760B2 (en) * 2023-01-23 2025-07-15 Texas Instruments Incorporated Indirect comparator offset estimation
US12182040B1 (en) 2023-06-05 2024-12-31 Eliyan Corporation Multi-chip module (MCM) with scalable high bandwidth memory
KR20250011019A (ko) 2023-07-13 2025-01-21 삼성전자주식회사 전자 장치 및 그것을 포함하는 통신 시스템
US12204482B1 (en) 2023-10-09 2025-01-21 Eliyan Corporation Memory chiplet with efficient mapping of memory-centric interface to die-to-die (D2D) unit interface modules
US12248413B1 (en) 2023-10-11 2025-03-11 Eliyan Corporation Universal memory interface utilizing die-to-die (D2D) interfaces between chiplets
US20250267047A1 (en) * 2024-02-20 2025-08-21 Qualcomm Incorporated Sampler input calibration in a serdes receiver using a self-generated reference voltage

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US20090146722A1 (en) * 2007-12-10 2009-06-11 International Business Machines Corporation Systems and Arrangements to Provide Input Offset Voltage Compensation
US8385496B1 (en) * 2010-10-21 2013-02-26 Altera Corporation Apparatus and methods of receiver offset calibration

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JP2001103098A (ja) * 1999-09-28 2001-04-13 Fujitsu Ltd レシーバ、トランシーバ回路および信号伝送システム
US20090146722A1 (en) * 2007-12-10 2009-06-11 International Business Machines Corporation Systems and Arrangements to Provide Input Offset Voltage Compensation
US8385496B1 (en) * 2010-10-21 2013-02-26 Altera Corporation Apparatus and methods of receiver offset calibration

Also Published As

Publication number Publication date
EP3152878A1 (en) 2017-04-12
US20150358005A1 (en) 2015-12-10
KR20170016841A (ko) 2017-02-14
CN106464237B (zh) 2019-04-23
US9722823B2 (en) 2017-08-01
US20160294583A1 (en) 2016-10-06
WO2015187307A1 (en) 2015-12-10
CN106464237A (zh) 2017-02-22
US9385695B2 (en) 2016-07-05

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