JP2017511971A - 封止層を横切るサイドバリア層を有するビアを備える集積デバイス - Google Patents

封止層を横切るサイドバリア層を有するビアを備える集積デバイス Download PDF

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Publication number
JP2017511971A
JP2017511971A JP2016550191A JP2016550191A JP2017511971A JP 2017511971 A JP2017511971 A JP 2017511971A JP 2016550191 A JP2016550191 A JP 2016550191A JP 2016550191 A JP2016550191 A JP 2016550191A JP 2017511971 A JP2017511971 A JP 2017511971A
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layer
implementations
substrate
integrated device
coupled
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Japanese (ja)
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JP2017511971A5 (enExample
Inventor
ジェ・シク・リー
ホン・ボク・ウィ
ドン・ウク・キム
シーチュン・グ
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クアルコム，インコーポレイテッド
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Publication of JP2017511971A publication Critical patent/JP2017511971A/ja
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Ceased legal-status Critical Current

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    • H10W20/20—
    • H10W20/056—
    • H10W20/081—
    • H10W70/635—
    • H10W72/00—
    • H10W74/01—
    • H10W90/00—
    • H10W70/60—
    • H10W90/722—
    • H10W90/724—

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Manufacturing & Machinery (AREA)
  • Production Of Multi-Layered Print Wiring Board (AREA)
  • Micromachines (AREA)
JP2016550191A 2014-02-13 2015-02-11 封止層を横切るサイドバリア層を有するビアを備える集積デバイス Ceased JP2017511971A (ja)

Applications Claiming Priority (5)

Application Number Priority Date Filing Date Title
US201461939523P 2014-02-13 2014-02-13
US61/939,523 2014-02-13
US14/274,517 2014-05-09
US14/274,517 US9466554B2 (en) 2014-02-13 2014-05-09 Integrated device comprising via with side barrier layer traversing encapsulation layer
PCT/US2015/015421 WO2015123301A1 (en) 2014-02-13 2015-02-11 Integrated device comprising via with side barrier layer traversing encapsulation layer

Publications (2)

Publication Number Publication Date
JP2017511971A true JP2017511971A (ja) 2017-04-27
JP2017511971A5 JP2017511971A5 (enExample) 2018-02-08

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JP2016550191A Ceased JP2017511971A (ja) 2014-02-13 2015-02-11 封止層を横切るサイドバリア層を有するビアを備える集積デバイス

Country Status (5)

Country Link
US (1) US9466554B2 (enExample)
EP (1) EP3105787B1 (enExample)
JP (1) JP2017511971A (enExample)
CN (1) CN105981166B (enExample)
WO (1) WO2015123301A1 (enExample)

Families Citing this family (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US9343417B2 (en) 2013-09-18 2016-05-17 Taiwan Semiconductor Manufacturing Company, Ltd. Hollow metal pillar packaging scheme
US9385110B2 (en) 2014-06-18 2016-07-05 Taiwan Semiconductor Manufacturing Company, Ltd. Semiconductor device and method
US9355963B2 (en) * 2014-09-26 2016-05-31 Qualcomm Incorporated Semiconductor package interconnections and method of making the same
TWI559829B (zh) * 2014-10-22 2016-11-21 矽品精密工業股份有限公司 封裝結構及其製法
US10651160B2 (en) 2017-03-20 2020-05-12 Qualcomm Incorporated Low profile integrated package
CN114093770A (zh) * 2021-10-27 2022-02-25 珠海越亚半导体股份有限公司 埋嵌封装结构及其制作方法

Citations (7)

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WO2010041630A1 (ja) * 2008-10-10 2010-04-15 日本電気株式会社 半導体装置及びその製造方法
US20100155920A1 (en) * 2008-12-24 2010-06-24 Samsung Electronics Co., Ltd. Stacked semiconductor package, semiconductor package module and method of manufacturing the stacked semiconductor package
JP2011238674A (ja) * 2010-05-07 2011-11-24 Seiko Epson Corp 配線基板、圧電発振器、ジャイロセンサー、配線基板の製造方法
JP2012119688A (ja) * 2010-12-02 2012-06-21 Samsung Electronics Co Ltd 積層パッケージ構造物、パッケージオンパッケージ素子、およびパッケージオンパッケージ素子製造方法
JP2012129262A (ja) * 2010-12-13 2012-07-05 Sumitomo Bakelite Co Ltd 半導体素子封止体の製造方法および半導体パッケージの製造方法
US20120168944A1 (en) * 2010-12-30 2012-07-05 Stmicroelectronics Pte Ltd. Through hole via filling using electroless plating
JP2013535834A (ja) * 2010-07-23 2013-09-12 テッセラ，インコーポレイテッド 組立て後に平坦化される超小型電子素子

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US6586682B2 (en) 2000-02-23 2003-07-01 Kulicke & Soffa Holdings, Inc. Printed wiring board with controlled line impedance
GB0330010D0 (en) * 2003-12-24 2004-01-28 Cavendish Kinetics Ltd Method for containing a device and a corresponding device
JP2005235860A (ja) * 2004-02-17 2005-09-02 Sanyo Electric Co Ltd 半導体装置及びその製造方法
US8239162B2 (en) * 2006-04-13 2012-08-07 Tanenhaus & Associates, Inc. Miniaturized inertial measurement unit and associated methods
US8021981B2 (en) 2006-08-30 2011-09-20 Micron Technology, Inc. Redistribution layers for microfeature workpieces, and associated systems and methods
DE102007020266B3 (de) * 2007-04-30 2008-11-13 Advanced Micro Devices, Inc., Sunnyvale Halbleiterstruktur mit einem elektrisch leitfähigen Strukturelement und Verfahren zu ihrer Herstellung
JP5596919B2 (ja) * 2008-11-26 2014-09-24 キヤノン株式会社 半導体装置の製造方法
US7799602B2 (en) 2008-12-10 2010-09-21 Stats Chippac, Ltd. Semiconductor device and method of forming a shielding layer over a semiconductor die after forming a build-up interconnect structure
JP2010157690A (ja) 2008-12-29 2010-07-15 Ibiden Co Ltd 電子部品実装用基板及び電子部品実装用基板の製造方法
US8476770B2 (en) * 2011-07-07 2013-07-02 Taiwan Semiconductor Manufacturing Company, Ltd. Apparatus and methods for forming through vias
US9040346B2 (en) 2012-05-03 2015-05-26 Infineon Technologies Ag Semiconductor package and methods of formation thereof
US8981559B2 (en) 2012-06-25 2015-03-17 Taiwan Semiconductor Manufacturing Company, Ltd. Package on package devices and methods of packaging semiconductor dies

Patent Citations (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2010041630A1 (ja) * 2008-10-10 2010-04-15 日本電気株式会社 半導体装置及びその製造方法
US20100155920A1 (en) * 2008-12-24 2010-06-24 Samsung Electronics Co., Ltd. Stacked semiconductor package, semiconductor package module and method of manufacturing the stacked semiconductor package
JP2011238674A (ja) * 2010-05-07 2011-11-24 Seiko Epson Corp 配線基板、圧電発振器、ジャイロセンサー、配線基板の製造方法
JP2013535834A (ja) * 2010-07-23 2013-09-12 テッセラ，インコーポレイテッド 組立て後に平坦化される超小型電子素子
JP2012119688A (ja) * 2010-12-02 2012-06-21 Samsung Electronics Co Ltd 積層パッケージ構造物、パッケージオンパッケージ素子、およびパッケージオンパッケージ素子製造方法
JP2012129262A (ja) * 2010-12-13 2012-07-05 Sumitomo Bakelite Co Ltd 半導体素子封止体の製造方法および半導体パッケージの製造方法
US20120168944A1 (en) * 2010-12-30 2012-07-05 Stmicroelectronics Pte Ltd. Through hole via filling using electroless plating

Also Published As

Publication number Publication date
EP3105787B1 (en) 2021-08-25
WO2015123301A1 (en) 2015-08-20
EP3105787A1 (en) 2016-12-21
US9466554B2 (en) 2016-10-11
CN105981166B (zh) 2019-04-16
US20150228556A1 (en) 2015-08-13
CN105981166A (zh) 2016-09-28

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