JP2017509158A - SiGeC層をエッチストップとする接合型半導体構造 - Google Patents
SiGeC層をエッチストップとする接合型半導体構造 Download PDFInfo
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 72
- 229910003811 SiGeC Inorganic materials 0.000 title claims abstract 19
- 239000000758 substrate Substances 0.000 claims abstract description 27
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims abstract description 13
- 229910052710 silicon Inorganic materials 0.000 claims abstract description 13
- 239000010703 silicon Substances 0.000 claims abstract description 13
- 230000001939 inductive effect Effects 0.000 claims abstract description 6
- 238000000034 method Methods 0.000 claims description 33
- 239000000463 material Substances 0.000 claims description 12
- 235000012431 wafers Nutrition 0.000 abstract description 87
- 230000008569 process Effects 0.000 description 23
- 238000012545 processing Methods 0.000 description 12
- 238000004519 manufacturing process Methods 0.000 description 6
- 230000008901 benefit Effects 0.000 description 5
- 238000012546 transfer Methods 0.000 description 5
- AXQKVSDUCKWEKE-UHFFFAOYSA-N [C].[Ge].[Si] Chemical compound [C].[Ge].[Si] AXQKVSDUCKWEKE-UHFFFAOYSA-N 0.000 description 3
- 239000002019 doping agent Substances 0.000 description 3
- 238000012986 modification Methods 0.000 description 3
- 230000004048 modification Effects 0.000 description 3
- 239000012212 insulator Substances 0.000 description 2
- 230000004075 alteration Effects 0.000 description 1
- 239000000969 carrier Substances 0.000 description 1
- 239000002800 charge carrier Substances 0.000 description 1
- 230000006378 damage Effects 0.000 description 1
- 238000011161 development Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000005530 etching Methods 0.000 description 1
- 239000012467 final product Substances 0.000 description 1
- 230000004927 fusion Effects 0.000 description 1
- 238000000227 grinding Methods 0.000 description 1
- 238000002513 implantation Methods 0.000 description 1
- 238000005468 ion implantation Methods 0.000 description 1
- 238000002955 isolation Methods 0.000 description 1
- 230000003071 parasitic effect Effects 0.000 description 1
- 238000005498 polishing Methods 0.000 description 1
- 238000001039 wet etching Methods 0.000 description 1
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Abstract
Description
本出願は、参照によりその全体が本明細書に組み込まれる、2014年3月24日出願の米国特許出願第14/223,060号の優先権を主張する。
101 第1のウエハ
102 第2のウエハ
103 ボンディング層
104 トラップリッチ層
105 基板層
106 活性層
107 能動デバイス
108 絶縁層
109 ソース
110 ドレイン
111 チャネル
112 ゲート
200 バルク半導体基板
201 シリコンゲルマニウムカーボン(SiGeC)層、SiGeC層
202 半導体層
Claims (20)
- 第1の接合材料を含む第1のウエハを形成するステップと、
基板と、SiGeC層と、活性層と、第2の接合材料とを含む第2のウエハを形成するステップであって、前記活性層は前記SiGeC層と前記第2の接合材料の間にあるステップと、
前記第1および第2の接合材料において前記第2のウエハを前記第1のウエハに接合するステップと、
前記SiGeC層をエッチストップとして使用して前記基板を除去するステップと
を備える方法。 - 前記SiGeC層は少なくとも前記活性層の一部に歪みを誘起する、
請求項1に記載の方法。 - 前記SiGeC層を除去するステップをさらに含む、
請求項1に記載の方法。 - 前記第2のウエハを前記形成するステップは、前記第2のウエハを前記第1のウエハに接合するステップより前に前記SiGeC層および前記活性層を形成するステップを含む、
請求項1に記載の方法。 - 前記第2のウエハはバルクシリコンウエハである、
請求項1に記載の方法。 - 前記活性層はゲートおよびチャネルを含み、
前記第2のウエハを前記第1のウエハに前記接合するステップは、前記ゲートを前記チャネルと前記第1のウエハの間にあらしめる、
請求項1に記載の方法。 - 前記第1のウエハを前記形成するステップは、前記第1のウエハの中にトラップリッチ層を形成するステップを含む、
請求項1に記載の方法。 - 第1のウエハと、
前記第1のウエハの表面にある第1の接合材料と、
前記第1のウエハに接合される第2のウエハと、
前記第2のウエハ内にある活性層と、
前記第2のウエハの表面にあり、かつ前記第1の接合材料に接合されている第2の接合材料と
を含む半導体構造であって、
SiGeC層をエッチストップとして用いて、前記第1のウエハとは反対側の前記活性層上にある前記第2のウエハから基板が除去されている、
半導体構造。 - 前記SiGeC層を歪み誘起層としてもさらに含む、
請求項8に記載の半導体構造。 - 前記SiGeC層が除去されている、
請求項8に記載の半導体構造。 - 前記SiGeC層および前記活性層は、前記第1のウエハを前記第2のウエハに接合するよりも前に、前記第2のウエハ内に形成される、
請求項8に記載の半導体構造。 - 前記第2のウエハは内部に前記活性層および前記SiGeC層が形成される前のバルクシリコンウエハである、
請求項8に記載の半導体構造。 - 前記活性層はゲートおよびチャネルを含み、前記ゲートは前記チャネルと前記第1のウエハの間にある、
請求項8に記載の半導体構造。 - 前記第1のウエハ内にトラップリッチ層をさらに含む、
請求項8に記載の半導体構造。 - ハンドルウエハと、
前記ハンドルウエハ内にある第1の接合材料と、
前記ハンドルウエハに接合されるバルクシリコンウエハと、
前記バルクシリコンウエハ内にある活性層と、
前記バルクシリコンウエハ内にあり、かつ前記第1の接合材料に接合されている第2の接合材料と、
前記ハンドルウエハとは反対側の前記活性層上にある前記バルクシリコンウエハ内にあるSiGeC層と
を含む半導体構造であって、
前記SiGeC層をエッチストップとして用いて、前記バルクシリコンウエハから基板が除去されており、
前記ハンドルウエハは前記半導体構造に構造強度を与える、
半導体構造。 - 前記SiGeC層を歪み誘起層としてもさらに含む、
請求項15に記載の半導体構造。 - 前記SiGeC層が除去されている、
請求項15に記載の半導体構造。 - 前記SiGeC層および前記活性層は、前記ハンドルウエハを前記バルクシリコンウエハに接合するよりも前に、前記バルクシリコンウエハ内に形成される、
請求項15に記載の半導体構造。 - 前記活性層はゲートおよびチャネルを含み、前記ゲートは前記チャネルと前記ハンドルウエハの間にある、
請求項15に記載の半導体構造。 - 前記ハンドルウエハ内にトラップリッチ層をさらに含む、
請求項15に記載の半導体構造。
Applications Claiming Priority (3)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US14/223,060 | 2014-03-24 | ||
US14/223,060 US9105689B1 (en) | 2014-03-24 | 2014-03-24 | Bonded semiconductor structure with SiGeC layer as etch stop |
PCT/US2015/021243 WO2015148212A1 (en) | 2014-03-24 | 2015-03-18 | BONDED SEMICONDUCTOR STRUCTURE WITH SiGeC LAYER AS ETCH STOP |
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Publication Number | Publication Date |
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JP2017509158A true JP2017509158A (ja) | 2017-03-30 |
JP6360194B2 JP6360194B2 (ja) | 2018-07-18 |
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ID=53763327
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Application Number | Title | Priority Date | Filing Date |
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JP2016558195A Expired - Fee Related JP6360194B2 (ja) | 2014-03-24 | 2015-03-18 | SiGeC層をエッチストップとする接合型半導体構造 |
Country Status (7)
Country | Link |
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US (1) | US9105689B1 (ja) |
EP (1) | EP3123496A4 (ja) |
JP (1) | JP6360194B2 (ja) |
KR (2) | KR20180049273A (ja) |
CN (1) | CN106104749A (ja) |
TW (1) | TWI641023B (ja) |
WO (1) | WO2015148212A1 (ja) |
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US11869591B2 (en) | 2016-10-10 | 2024-01-09 | Monolithic 3D Inc. | 3D memory devices and structures with control circuits |
US11251149B2 (en) | 2016-10-10 | 2022-02-15 | Monolithic 3D Inc. | 3D memory device and structure |
US11711928B2 (en) | 2016-10-10 | 2023-07-25 | Monolithic 3D Inc. | 3D memory devices and structures with control circuits |
US10249538B1 (en) | 2017-10-03 | 2019-04-02 | Globalfoundries Inc. | Method of forming vertical field effect transistors with different gate lengths and a resulting structure |
WO2020120414A1 (en) | 2018-12-10 | 2020-06-18 | Rockley Photonics Limited | Optoelectronic device and method of manufacture thereof |
US11018156B2 (en) | 2019-04-08 | 2021-05-25 | Monolithic 3D Inc. | 3D memory semiconductor devices and structures |
US11158652B1 (en) | 2019-04-08 | 2021-10-26 | Monolithic 3D Inc. | 3D memory semiconductor devices and structures |
US10892016B1 (en) | 2019-04-08 | 2021-01-12 | Monolithic 3D Inc. | 3D memory semiconductor devices and structures |
US11763864B2 (en) | 2019-04-08 | 2023-09-19 | Monolithic 3D Inc. | 3D memory semiconductor devices and structures with bit-line pillars |
US11296106B2 (en) | 2019-04-08 | 2022-04-05 | Monolithic 3D Inc. | 3D memory semiconductor devices and structures |
KR20200133092A (ko) | 2019-05-16 | 2020-11-26 | 삼성전자주식회사 | 반도체 소자 |
US20220093466A1 (en) * | 2020-09-24 | 2022-03-24 | Tokyo Electron Limited | Epitaxial high-k etch stop layer for backside reveal integration |
FR3121280B1 (fr) * | 2021-03-29 | 2023-12-22 | Commissariat Energie Atomique | Transistor à effet de champ à structure verticale |
Citations (11)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5906708A (en) * | 1994-11-10 | 1999-05-25 | Lawrence Semiconductor Research Laboratory, Inc. | Silicon-germanium-carbon compositions in selective etch processes |
US6323108B1 (en) * | 1999-07-27 | 2001-11-27 | The United States Of America As Represented By The Secretary Of The Navy | Fabrication ultra-thin bonded semiconductor layers |
US6815278B1 (en) * | 2003-08-25 | 2004-11-09 | International Business Machines Corporation | Ultra-thin silicon-on-insulator and strained-silicon-direct-on-insulator with hybrid crystal orientations |
JP2004336048A (ja) * | 2003-05-01 | 2004-11-25 | Internatl Business Mach Corp <Ibm> | Mosfetデバイス及び該デバイスを備える電子システム |
US20060172505A1 (en) * | 2005-01-31 | 2006-08-03 | Koester Steven J | Structure and method of integrating compound and elemental semiconductors for high-performace CMOS |
US20060199353A1 (en) * | 2002-07-12 | 2006-09-07 | The Government Of The Usa, As Represented By The Secretary Of The Navy Naval Research Laboratory | Wafer bonding of thinned electronic materials and circuits to high performance substrate |
JP2007500434A (ja) * | 2003-07-30 | 2007-01-11 | エス.オー.アイ.テック、シリコン、オン、インシュレター、テクノロジーズ | 高温応力に耐性のある応力付加絶縁体上半導体構造 |
US7268063B1 (en) * | 2004-06-01 | 2007-09-11 | University Of Central Florida | Process for fabricating semiconductor component |
US20080213973A1 (en) * | 2005-06-07 | 2008-09-04 | Freescale Semiconductor, Inc. | Method of fabricating a substrate for a planar, double-gated, transistor process |
JP2012518290A (ja) * | 2009-02-19 | 2012-08-09 | アイキューイー シリコン コンパウンズ リミテッド | 半導体材料の薄層の形成 |
JP2014504457A (ja) * | 2010-12-24 | 2014-02-20 | アイ・オゥ・セミコンダクター・インコーポレイテッド | 半導体デバイスのためのトラップリッチ層 |
Family Cites Families (8)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US6410371B1 (en) * | 2001-02-26 | 2002-06-25 | Advanced Micro Devices, Inc. | Method of fabrication of semiconductor-on-insulator (SOI) wafer having a Si/SiGe/Si active layer |
US20030227057A1 (en) | 2002-06-07 | 2003-12-11 | Lochtefeld Anthony J. | Strained-semiconductor-on-insulator device structures |
US7132321B2 (en) | 2002-10-24 | 2006-11-07 | The United States Of America As Represented By The Secretary Of The Navy | Vertical conducting power semiconductor devices implemented by deep etch |
KR100619549B1 (ko) | 2005-09-13 | 2006-09-01 | (주)한비젼 | 다층 기판을 이용한 이미지 센서의 포토 다이오드 제조방법및 그 콘택방법 및 그 구조 |
US8598006B2 (en) * | 2010-03-16 | 2013-12-03 | International Business Machines Corporation | Strain preserving ion implantation methods |
US8466054B2 (en) | 2010-12-13 | 2013-06-18 | Io Semiconductor, Inc. | Thermal conduction paths for semiconductor structures |
US8481405B2 (en) * | 2010-12-24 | 2013-07-09 | Io Semiconductor, Inc. | Trap rich layer with through-silicon-vias in semiconductor devices |
WO2013019250A1 (en) | 2011-08-02 | 2013-02-07 | The Silanna Group Pty Ltd | A photovoltaic device and a process for producing a photovoltaic device |
-
2014
- 2014-03-24 US US14/223,060 patent/US9105689B1/en active Active
-
2015
- 2015-03-11 TW TW104107775A patent/TWI641023B/zh not_active IP Right Cessation
- 2015-03-18 WO PCT/US2015/021243 patent/WO2015148212A1/en active Application Filing
- 2015-03-18 JP JP2016558195A patent/JP6360194B2/ja not_active Expired - Fee Related
- 2015-03-18 EP EP15768063.8A patent/EP3123496A4/en not_active Withdrawn
- 2015-03-18 KR KR1020187012773A patent/KR20180049273A/ko active Application Filing
- 2015-03-18 KR KR1020167026022A patent/KR20160116011A/ko active Application Filing
- 2015-03-18 CN CN201580015187.5A patent/CN106104749A/zh active Pending
Patent Citations (11)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5906708A (en) * | 1994-11-10 | 1999-05-25 | Lawrence Semiconductor Research Laboratory, Inc. | Silicon-germanium-carbon compositions in selective etch processes |
US6323108B1 (en) * | 1999-07-27 | 2001-11-27 | The United States Of America As Represented By The Secretary Of The Navy | Fabrication ultra-thin bonded semiconductor layers |
US20060199353A1 (en) * | 2002-07-12 | 2006-09-07 | The Government Of The Usa, As Represented By The Secretary Of The Navy Naval Research Laboratory | Wafer bonding of thinned electronic materials and circuits to high performance substrate |
JP2004336048A (ja) * | 2003-05-01 | 2004-11-25 | Internatl Business Mach Corp <Ibm> | Mosfetデバイス及び該デバイスを備える電子システム |
JP2007500434A (ja) * | 2003-07-30 | 2007-01-11 | エス.オー.アイ.テック、シリコン、オン、インシュレター、テクノロジーズ | 高温応力に耐性のある応力付加絶縁体上半導体構造 |
US6815278B1 (en) * | 2003-08-25 | 2004-11-09 | International Business Machines Corporation | Ultra-thin silicon-on-insulator and strained-silicon-direct-on-insulator with hybrid crystal orientations |
US7268063B1 (en) * | 2004-06-01 | 2007-09-11 | University Of Central Florida | Process for fabricating semiconductor component |
US20060172505A1 (en) * | 2005-01-31 | 2006-08-03 | Koester Steven J | Structure and method of integrating compound and elemental semiconductors for high-performace CMOS |
US20080213973A1 (en) * | 2005-06-07 | 2008-09-04 | Freescale Semiconductor, Inc. | Method of fabricating a substrate for a planar, double-gated, transistor process |
JP2012518290A (ja) * | 2009-02-19 | 2012-08-09 | アイキューイー シリコン コンパウンズ リミテッド | 半導体材料の薄層の形成 |
JP2014504457A (ja) * | 2010-12-24 | 2014-02-20 | アイ・オゥ・セミコンダクター・インコーポレイテッド | 半導体デバイスのためのトラップリッチ層 |
Non-Patent Citations (1)
Title |
---|
D. J. GODBEY、外5名: "Fabrication of Bond and Etch-Back Silicon on Insulator Using a Strained Si0.7Ge0.3 Layer as an Etch", JOURNAL OF THE ELECTROCHEMICAL SOCIETY [ONLINE], vol. 第137巻,第10号, JPN6017009000, 31 December 1990 (1990-12-31), pages p.3219−3223 * |
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EP3123496A1 (en) | 2017-02-01 |
EP3123496A4 (en) | 2017-11-08 |
CN106104749A (zh) | 2016-11-09 |
WO2015148212A1 (en) | 2015-10-01 |
US9105689B1 (en) | 2015-08-11 |
TWI641023B (zh) | 2018-11-11 |
KR20180049273A (ko) | 2018-05-10 |
JP6360194B2 (ja) | 2018-07-18 |
KR20160116011A (ko) | 2016-10-06 |
TW201543539A (zh) | 2015-11-16 |
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