TW201543539A - 具有作爲蝕刻止檔之ＳｉＧｅＣ層之接合之半導體結構 - Google Patents

具有作爲蝕刻止檔之ＳｉＧｅＣ層之接合之半導體結構 Download PDF

Info

Publication number
TW201543539A
TW201543539A TW104107775A TW104107775A TW201543539A TW 201543539 A TW201543539 A TW 201543539A TW 104107775 A TW104107775 A TW 104107775A TW 104107775 A TW104107775 A TW 104107775A TW 201543539 A TW201543539 A TW 201543539A
Authority
TW
Taiwan
Prior art keywords
wafer
layer
semiconductor structure
sigec
active layer
Prior art date
Application number
TW104107775A
Other languages
English (en)
Other versions
TWI641023B (zh
Inventor
Stephen A Fanelli
Original Assignee
Silanna Semiconductor Usa Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Silanna Semiconductor Usa Inc filed Critical Silanna Semiconductor Usa Inc
Publication of TW201543539A publication Critical patent/TW201543539A/zh
Application granted granted Critical
Publication of TWI641023B publication Critical patent/TWI641023B/zh

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/7624—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology
    • H01L21/76251—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology using bonding techniques
    • H01L21/76256—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology using bonding techniques using silicon etch back techniques, e.g. BESOI, ELTRAN
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H01L21/28008—Making conductor-insulator-semiconductor electrodes
    • H01L21/28255—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor belonging to Group IV and not being elemental silicon, e.g. Ge, SiGe, SiGeC
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76829—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1218—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition or structure of the substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1259—Multistep manufacturing methods
    • H01L27/1262—Multistep manufacturing methods with a particular formation, treatment or coating of the substrate
    • H01L27/1266—Multistep manufacturing methods with a particular formation, treatment or coating of the substrate the substrate on which the devices are formed not being the final device substrate, e.g. using a temporary substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
    • H01L29/0642—Isolation within the component, i.e. internal isolation
    • H01L29/0649—Dielectric regions, e.g. SiO2 regions, air gaps
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/7842—Field effect transistors with field effect produced by an insulated gate means for exerting mechanical stress on the crystal lattice of the channel region, e.g. using a flexible substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
    • H01L29/78603—Thin film transistors, i.e. transistors with a channel being at least partly a thin film characterised by the insulating substrate or support

Landscapes

  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • General Physics & Mathematics (AREA)
  • Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Manufacturing & Machinery (AREA)
  • Ceramic Engineering (AREA)
  • Chemical & Material Sciences (AREA)
  • Crystallography & Structural Chemistry (AREA)
  • Thin Film Transistor (AREA)
  • Element Separation (AREA)

Abstract

本發明揭示一種半導體結構，其利用接合在一起之一第一晶圓(例如，一處置晶圓)及一第二晶圓(例如，一塊體矽晶圓)形成。該第二晶圓包含一作用層，其在一些實施例中於該兩個晶圓接合在一起之前形成。使用作為一蝕刻止擋之一SiGeC層在與該第一晶圓相對之該作用層之一側上從該第二晶圓移除一基板。在一些實施例中，接著移除該SiGeC層；但在一些其他實施例中，其保持為一應力引發層。

Description

具有作為蝕刻止擋之SiGeC層之接合之半導體結構 【相關申請交叉參考】
本申請案主張2014年3月24日申請之美國專利申請案第14/223,060號之優先權，該案之全部內容以引用的方式併入本文中。
層轉移或晶圓接合技術可用於形成具有一塊體基板層、一埋入氧化物(BOX)層及一半導體層之一絕緣體上半導體(SOI)晶圓之層。接著具有主動裝置及導電互連件之積體電路(IC)可形成至半導體層中及半導體層上。
一替代層轉移程序可以一SOI晶圓(具有已形成之一主動裝置層)開始，將SOI晶圓翻轉，將SOI晶圓接合至一處置晶圓且接著移除塊體基板及BOX。以此方式，主動裝置層轉移至處置晶圓。此外，處置晶圓可能先前已經歷其他處理，使得所得接合之半導體結構可具有難以在受到所有必要之處理步驟之一單個晶圓中達成之期望特征。例如，處置晶圓可具有擁有一富阱層之一基板，使得所得半導體結構具有介於主動裝置層與基板之間之富阱層。但是，若已使用一單個晶圓且富阱層已在主動裝置層之前形成於晶圓中，則用於形成主動裝置層之處理技術可能已使富阱層降級。因此，在此實例中，涉及分離地處理 晶圓之層轉移程序實現一更佳之最終產品。
在一些方面或對於一些應用，SOI技術之發展表示優於傳統塊體半導體程序之演進。但是，SOI晶圓一般比簡單之塊體半導體晶圓更複雜及昂貴。增加之費用之部分係歸因於在主動裝置製造可開始之前製造SOI晶圓所需之額外處理步驟。
在一些實施例中，一半導體結構利用接合在一起之一第一晶圓(例如，一處置晶圓)及一第二晶圓(例如，一塊體矽晶圓)形成。該第二晶圓包含一基板、一SiGeC(矽-鍺-碳)層及一作用層。使用作為一蝕刻止擋之該SiGeC層在與該第一晶圓相對之該作用層之一側上從該第二晶圓移除該基板。
在一些實施例中，接著移除該SiGeC層；但在一些其他實施例中，其保持為一應力引發層。在一些實施例中，該作用層及該SiGeC層在該兩個晶圓接合在一起之前形成。在一些實施例中，該作用層包含一閘極及一通道，且在該第二晶圓至該第一晶圓之該接合之後，該閘極係介於該通道與該第一晶圓之間。在一些實施例中，該第一晶圓包含一富阱層。
100‧‧‧半導體結構
101‧‧‧第一晶圓
102‧‧‧第二晶圓
103‧‧‧接合層
104‧‧‧富阱層
105‧‧‧基板層
106‧‧‧作用層
107‧‧‧主動裝置
108‧‧‧絕緣體層
109‧‧‧源極
110‧‧‧汲極
111‧‧‧通道
112‧‧‧閘極
200‧‧‧基板
201‧‧‧矽-鍺-碳(SiGeC)層
202‧‧‧半導體層
圖1係根據本發明之一實施例之一半導體結構之一簡化截面圖。
圖2及圖3係可用於形成根據本發明之一實施例之圖1中所示之半導體結構的一第一晶圓之不同製造階段之簡化截面圖。
圖4係可用於形成根據本發明之一實施例之圖1中所示之半導體結構的一第二晶圓之一簡化截面圖。
圖5、圖6及圖7係根據本發明之一實施例之圖1中所示之半導體結構的不同製造階段之簡化截面圖。
現將詳細參考揭示之本發明之實施例，其等一或多個實例繪示於附圖中。各實例藉由本技術之解釋來提供，而非作為對本技術之限制。事實上，熟悉此項技術者將了解可在不脫離於本技術之精神及範疇下在本技術中實現修改及變動。例如，繪示或描述為一實施例之部分之特征可與另一實施例一起使用以產生又一實施例。因此，意欲本標的覆蓋隨附申請專利範圍及其等等效例之範疇內之所有此等修改及變動。
根據本發明之一實施例，在圖1中展示一半導體結構100。半導體結構100可併入於一整體IC晶片(未展示)中。半導體結構100一般包含已接合在一起之一第一晶圓101及一第二晶圓102之一剩餘部分。在一些實施例中，第一晶圓101係一處置晶圓，其為半導體結構100提供結構強度。在一些實施例中，第二晶圓102係一塊體半導體晶圓，而非一絕緣體上半導體(SOI)晶圓。因為第二晶圓102可為一塊體半導體晶圓，所以CMOS處理之前之第二晶圓102之最初成本一般小於一SOI晶圓之成本。此外，因為一SOI晶圓之標準基板及埋入氧化物(BOX)將必須移除以形成與第二晶圓102之剩餘部分相當之一結構，所以無必要以一SOI晶圓開始來形成半導體結構100。因此，本發明之一優點係一較便宜之塊體半導體晶圓可用於第二晶圓102。將在以下描述中了解額外優點。
第一晶圓101一般包含一接合層103、一富阱層104及一基板層105。額外組件亦可併入於第一晶圓101中，但為了簡單起見並未展示。
第二晶圓102之剩餘部分一般包含至少一作用層106。作用層106一般將主動裝置107及一絕緣體層108包含於其中。主動裝置107一般包含一源極109、一汲極110、一通道111及一閘極112。在一些實施例中，作用層106亦包含一接合層。或者，絕緣體層108(或外表面處之其至少一薄部分)可用作接合層。額外組件亦可併入於作用層106中，但為了簡單起見並未展示。
因為富阱層104使富阱層104中之電荷載子之載子壽命明顯降級，所以第一晶圓101中之富阱層104有效地對抗寄生表面導電。因為載子不能行進地較遠，所以基板層105之有效電阻保留且由作用層106所見之電容並非取決於作用層106中之信號。用於形成半導體結構100之下文描述之程序一般保留富阱層104之功效且最小化半導體結構100係一部分之整體IC晶片之完整性之破壞。
本文參考圖2至圖7描述根據本發明之一實施例之用於形成半導體結構100之一程序。如圖2中所示，第二晶圓102一般以一塊體半導體(例如，矽等等)基板200開始。一矽-鍺-碳(SiGeC)層201及一半導體層202形成至塊體半導體基板200中或塊體半導體基板200上。SiGeC層201可磊晶地生長於塊體半導體基板200上或離子植入至塊體半導體基板200中或由任何其他適當程序形成。半導體層202可磊晶地生長於SiGeC層201上。若SiGeC層201由離子植入形成且植入足夠深，則半導體層202可為植入之SiGeC層201上之塊體半導體基板200之一部分(或可由上述形成)。
主動裝置107及絕緣體層108如圖3中所示由CMOS處理形成至半導體層202中及半導體層202上。以此方式，作用層106形成於SiGeC層201上，其中通道 111介於閘極112與SiGeC層201之間。此外，在一些實施例中，拋光絕緣體層108之表面或一接合層(未展示)形成至絕緣體層108上而期望與第一晶圓101之稍後融合接合。
在(例如)與用於形成第二晶圓102之一般在圖2及圖3中所示之程序之任何部分同時之一分離程序中，第一晶圓101如圖4中所示般形成。富阱層104及接合層103可以任何適當方式，例如，藉由美國專利案第8,466,036號中所描述之任何適當之一或多個程序形成，該案宛如完全在本文中提出般以引用的方式併入本文中。
第二晶圓102如圖5中所示般翻轉且接合至第一晶圓101。因此，兩個晶圓101及102面對面接合，即其中第二晶圓102之前部或頂部表面處之絕緣體層108接合至第一晶圓101之前部或頂部表面處之接合層103。因此，閘極112介於通道111與第一晶圓101之間。
塊體半導體基板200一般從第二晶圓102移除。此移除可在一兩步驟程序中完成。首先，如圖6中所示，藉由研磨移除塊體半導體基板200之大多數。接著，如圖7中所示，(例如)利用對SiGeC層201具選擇性之一濕式蝕刻移除剩餘半導體材料。因此，SiGeC層201用作一蝕刻止擋層。當到達SiGeC層201時，可減少蝕刻速率而容許塊體半導體基板200之所有半導體材料之一完整或均勻移除。
接著可(例如)藉由另一濕式蝕刻移除SiGeC層201以形成如圖1中所示之半導體結構100。或者，SiGeC層201可保持為在通道111中引發應力之一應力引發層。作為一應力層，SiGeC層201將提供增加通道111中之遷移率及改進整體IC之效能之優點。將不能用一些其他類型 之蝕刻止擋層(例如，一P+蝕刻止擋層)達成應力引發層之優點。
半導體結構100及形成其之程序一般可使作用層106形成為一較薄層。此程序與使用一SOI晶圓，而非第二晶圓102之一程序相對照。在此情形中，SOI晶圓之BOX可用作一蝕刻止擋層以移除下伏基板。所得基板亦將可能具有一較薄作用層。但是，本發明利用一較便宜之塊體半導體晶圓完成此。此外，上文描述之程序與使用一不同類型之蝕刻止擋(諸如一P+蝕刻止擋層)之一程序相對照。在此情形中，P+蝕刻止擋層中之摻雜物將對CMOS處理中使用之高溫具更小之容許度。因此，P+摻雜物可能在隨後CMOS處理期間在半導體晶圓內擴散，藉此將摻雜物添加至源極109、汲極110及通道111且嚴重地改變其等特性。為了利用一P+蝕刻止擋層避免此問題，P+蝕刻止擋層將必須深得多地形成至塊體半導體基板200中或半導體層202將必須厚得多。無論如何，對於本發明不能儘可能薄地形成作用層106。
在一些實施例中，可利用一拋光止擋程序較薄地製成作用層106。此程序可使用一選擇性CMP以在第二晶圓102上圖案化之STI(淺溝渠隔離)區域上止擋。
本發明之另一優點與層轉移程序相關。用於蝕刻止擋層之一常見應用係層轉移以在CMOS處理之前產生一SOI晶圓。但是，若SiGeC蝕刻止擋層用於在CMOS處理之前產生一SOI晶圓，則對於隨後處理轉移膜必須拋光成(例如，CMP等等)光滑。此程序將具挑戰性且可能因CMP程序導致一非均勻性主動裝置層。另一方面，在本發明之一些實施例中，SiGeC層201首先在第二晶圓102中處理且接著層轉移至一處置層(例如，第一晶圓101)。 換言之，CMOS處理利用磊晶或植入之SiGeC層201完成且接著在程序結束時(即，在製造主動裝置107之後)層轉移至一處置晶圓。不需要拋光在圖3之階段存在於第二晶圓102上之粗糙表面，此係因為在此表面上將不製造其他主動裝置。
雖然本發明之實施例已主要關於其特定實施例討論，但是其他變動係可行的。可使用描述之結構或程序之多種組態來替代本文呈現之組態或除了本文呈現之組態之外可使用描述之結構或程序之多種組態。例如，鈍化及絕緣之額外層可在適當情況下安置於描述之層之間。
熟悉此項技術者將明白以上描述僅藉由實例且並非易欲限制本發明。本揭示內容中之任何內容不應指示本發明限於一單一晶圓上實施之系統。本揭示內容中之任何內容不應指示本發明限於要求一特定形式之半導體處理或積體電路之系統。本揭示內容中之任何內容不應將本發明限於基於矽之半導體裝置。一般而言，呈現之任何圖僅易欲指示一可能性組態且許多變動係可行的。熟悉此項技術者亦將明白與本發明一致之方法及系統適合在涵蓋半導體結構之較寬範圍之應用中使用。
雖然已詳細關於本發明之特定實施例描述本說明書，但是熟悉此項技術者在獲得上述理解之後應明白可易於設想此等實施例之變更、變動及等效例。本發明之此等及其他修改及變動可由熟悉此項技術者在不脫離於隨附申請專利範圍中更特定提出之本發明之精神及範疇下實踐。
101‧‧‧第一晶圓
102‧‧‧第二晶圓
103‧‧‧接合層
104‧‧‧富阱層
105‧‧‧基板層
106‧‧‧作用層
107‧‧‧主動裝置
108‧‧‧絕緣體層
109‧‧‧源極
110‧‧‧汲極
111‧‧‧通道
112‧‧‧閘極
201‧‧‧矽-鍺-碳(SiGeC)層
202‧‧‧半導體層

Claims (20)

  1. 一種方法，其包括：形成一第一晶圓，其具有一第一接合材料；形成一第二晶圓，其具有一基板、一SiGeC層、一作用層及一第二接合材料，該作用層介於該SiGeC層與該第二接合材料之間；在該第一接合材料及該第二接合材料處將該第二晶圓接合至該第一晶圓；及使用作為一蝕刻止擋之該SiGeC層移除該基板。
  2. 如請求項1之方法，其中：該SiGeC層在該作用層之至少一部分中引發一應力。
  3. 如請求項1之方法，其進一步包括：移除該SiGeC層。
  4. 如請求項1之方法，其中：該第二晶圓之該形成包含在該第二晶圓至該第一晶圓之該接合之前形成該SiGeC層及該作用層。
  5. 如請求項1之方法，其中：該第二晶圓係一塊體矽晶圓。
  6. 如請求項1之方法，其中：該作用層包含一閘極及一通道；且該第二晶圓至該第一晶圓之該接合使得該閘極介於該通道與該第一晶圓之間。
  7. 如請求項1之方法，其中：該第一晶圓之該形成包含在其中形成一富阱層。
  8. 一種半導體結構，其包括：一第一晶圓；一第一接合材料，其處於該第一晶圓之一表面處；一第二晶圓，其接合至該第一晶圓；一作用層，其在該第二晶圓內；及一第二接合材料，其處於該第二晶圓之一表面處且接合至該第一接合材料； 其中已使用作為一蝕刻止擋之一SiGeC層在與該第一晶圓相對之該作用層之一側上從該第二晶圓移除一基板。
  9. 如請求項8之半導體結構，其進一步包括：該SiGeC層亦作為一應力引發層。
  10. 如請求項8之半導體結構，其中：該SiGeC層已移除。
  11. 如請求項8之半導體結構，其中：該SiGeC層及該作用層在將該第一晶圓接合至該第二晶圓之前形成於該第二晶圓內。
  12. 如請求項8之半導體結構，其中：該第二晶圓在該作用層及該SiGeC層於其中之形成之前係一塊體矽晶圓。
  13. 如請求項8之半導體結構，其中：該作用層包含一閘極及一通道，該閘極介於該通道與該第一晶圓之間。
  14. 如請求項8之半導體結構，其進一步包括：一富阱層，其在該第一晶圓內。
  15. 一種半導體結構，其包括：一處置晶圓；一第一接合材料，其在該處置晶圓內；一塊體矽晶圓，其接合至該處置晶圓；一作用層，其在該塊體矽晶圓內；一第二接合材料，其在該塊體矽晶圓內且接合至該第一接合材料；及一SiGeC層，其在與該處置晶圓相對之該作用層之一側上於該塊體矽晶圓內；其中已使用作為一蝕刻止擋之該SiGeC層從該塊體矽晶圓移除一基板；及其中該處置晶圓為該半導體結構提供結構強度。
  16. 如請求項15之半導體結構，其進一步包括：該SiGeC層亦作為一應力引發層。
  17. 如請求項15之半導體結構，其中：該SiGeC層已移除。
  18. 如請求項15之半導體結構，其中：該SiGeC層及該作用層在將該處置晶圓接合至該塊體矽晶圓之前形成於該塊體矽晶圓內。
  19. 如請求項15之半導體結構，其中：該作用層包含一閘極及一通道，該閘極介於該通道與該處置晶圓之間。
  20. 如請求項15之半導體結構，其進一步包括：一富阱層，其在該處置晶圓內。
TW104107775A 2014-03-24 2015-03-11 具有作爲蝕刻止擋之ＳｉＧｅＣ層之接合之半導體結構 TWI641023B (zh)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US14/223,060 US9105689B1 (en) 2014-03-24 2014-03-24 Bonded semiconductor structure with SiGeC layer as etch stop
US14/223,060 2014-03-24

Publications (2)

Publication Number Publication Date
TW201543539A true TW201543539A (zh) 2015-11-16
TWI641023B TWI641023B (zh) 2018-11-11

Family

ID=53763327

Family Applications (1)

Application Number Title Priority Date Filing Date
TW104107775A TWI641023B (zh) 2014-03-24 2015-03-11 具有作爲蝕刻止擋之ＳｉＧｅＣ層之接合之半導體結構

Country Status (7)

Country Link
US (1) US9105689B1 (zh)
EP (1) EP3123496A4 (zh)
JP (1) JP6360194B2 (zh)
KR (2) KR20160116011A (zh)
CN (1) CN106104749A (zh)
TW (1) TWI641023B (zh)
WO (1) WO2015148212A1 (zh)

Families Citing this family (123)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US11984445B2 (en) 2009-10-12 2024-05-14 Monolithic 3D Inc. 3D semiconductor devices and structures with metal layers
US11018133B2 (en) 2009-10-12 2021-05-25 Monolithic 3D Inc. 3D integrated circuit
US11374118B2 (en) 2009-10-12 2022-06-28 Monolithic 3D Inc. Method to form a 3D integrated circuit
US10910364B2 (en) 2009-10-12 2021-02-02 Monolitaic 3D Inc. 3D semiconductor device
US11482440B2 (en) 2010-12-16 2022-10-25 Monolithic 3D Inc. 3D semiconductor device and structure with a built-in test circuit for repairing faulty circuits
US11018191B1 (en) 2010-10-11 2021-05-25 Monolithic 3D Inc. 3D semiconductor device and structure
US11227897B2 (en) 2010-10-11 2022-01-18 Monolithic 3D Inc. Method for producing a 3D semiconductor memory device and structure
US11257867B1 (en) 2010-10-11 2022-02-22 Monolithic 3D Inc. 3D semiconductor device and structure with oxide bonds
US11158674B2 (en) 2010-10-11 2021-10-26 Monolithic 3D Inc. Method to produce a 3D semiconductor device and structure
US11315980B1 (en) 2010-10-11 2022-04-26 Monolithic 3D Inc. 3D semiconductor device and structure with transistors
US11600667B1 (en) 2010-10-11 2023-03-07 Monolithic 3D Inc. Method to produce 3D semiconductor devices and structures with memory
US10896931B1 (en) 2010-10-11 2021-01-19 Monolithic 3D Inc. 3D semiconductor device and structure
US11469271B2 (en) 2010-10-11 2022-10-11 Monolithic 3D Inc. Method to produce 3D semiconductor devices and structures with memory
US11024673B1 (en) 2010-10-11 2021-06-01 Monolithic 3D Inc. 3D semiconductor device and structure
US11063071B1 (en) 2010-10-13 2021-07-13 Monolithic 3D Inc. Multilevel semiconductor device and structure with waveguides
US11327227B2 (en) 2010-10-13 2022-05-10 Monolithic 3D Inc. Multilevel semiconductor device and structure with electromagnetic modulators
US10998374B1 (en) 2010-10-13 2021-05-04 Monolithic 3D Inc. Multilevel semiconductor device and structure
US11855100B2 (en) 2010-10-13 2023-12-26 Monolithic 3D Inc. Multilevel semiconductor device and structure with oxide bonding
US11869915B2 (en) 2010-10-13 2024-01-09 Monolithic 3D Inc. Multilevel semiconductor device and structure with image sensors and wafer bonding
US11605663B2 (en) 2010-10-13 2023-03-14 Monolithic 3D Inc. Multilevel semiconductor device and structure with image sensors and wafer bonding
US11694922B2 (en) 2010-10-13 2023-07-04 Monolithic 3D Inc. Multilevel semiconductor device and structure with oxide bonding
US11855114B2 (en) 2010-10-13 2023-12-26 Monolithic 3D Inc. Multilevel semiconductor device and structure with image sensors and wafer bonding
US11984438B2 (en) 2010-10-13 2024-05-14 Monolithic 3D Inc. Multilevel semiconductor device and structure with oxide bonding
US11133344B2 (en) 2010-10-13 2021-09-28 Monolithic 3D Inc. Multilevel semiconductor device and structure with image sensors
US11043523B1 (en) 2010-10-13 2021-06-22 Monolithic 3D Inc. Multilevel semiconductor device and structure with image sensors
US11164898B2 (en) 2010-10-13 2021-11-02 Monolithic 3D Inc. Multilevel semiconductor device and structure
US11163112B2 (en) 2010-10-13 2021-11-02 Monolithic 3D Inc. Multilevel semiconductor device and structure with electromagnetic modulators
US10978501B1 (en) 2010-10-13 2021-04-13 Monolithic 3D Inc. Multilevel semiconductor device and structure with waveguides
US10943934B2 (en) 2010-10-13 2021-03-09 Monolithic 3D Inc. Multilevel semiconductor device and structure
US11929372B2 (en) 2010-10-13 2024-03-12 Monolithic 3D Inc. Multilevel semiconductor device and structure with image sensors and wafer bonding
US10833108B2 (en) 2010-10-13 2020-11-10 Monolithic 3D Inc. 3D microdisplay device and structure
US11437368B2 (en) 2010-10-13 2022-09-06 Monolithic 3D Inc. Multilevel semiconductor device and structure with oxide bonding
US11404466B2 (en) 2010-10-13 2022-08-02 Monolithic 3D Inc. Multilevel semiconductor device and structure with image sensors
US11355381B2 (en) 2010-11-18 2022-06-07 Monolithic 3D Inc. 3D semiconductor memory device and structure
US11610802B2 (en) 2010-11-18 2023-03-21 Monolithic 3D Inc. Method for producing a 3D semiconductor device and structure with single crystal transistors and metal gate electrodes
US11443971B2 (en) 2010-11-18 2022-09-13 Monolithic 3D Inc. 3D semiconductor device and structure with memory
US11901210B2 (en) 2010-11-18 2024-02-13 Monolithic 3D Inc. 3D semiconductor device and structure with memory
US11355380B2 (en) 2010-11-18 2022-06-07 Monolithic 3D Inc. Methods for producing 3D semiconductor memory device and structure utilizing alignment marks
US11018042B1 (en) 2010-11-18 2021-05-25 Monolithic 3D Inc. 3D semiconductor memory device and structure
US11804396B2 (en) 2010-11-18 2023-10-31 Monolithic 3D Inc. Methods for producing a 3D semiconductor device and structure with memory cells and multiple metal layers
US11482438B2 (en) 2010-11-18 2022-10-25 Monolithic 3D Inc. Methods for producing a 3D semiconductor memory device and structure
US11862503B2 (en) 2010-11-18 2024-01-02 Monolithic 3D Inc. Method for producing a 3D semiconductor device and structure with memory cells and multiple metal layers
US11004719B1 (en) 2010-11-18 2021-05-11 Monolithic 3D Inc. Methods for producing a 3D semiconductor memory device and structure
US11495484B2 (en) 2010-11-18 2022-11-08 Monolithic 3D Inc. 3D semiconductor devices and structures with at least two single-crystal layers
US11031275B2 (en) 2010-11-18 2021-06-08 Monolithic 3D Inc. 3D semiconductor device and structure with memory
US11735462B2 (en) 2010-11-18 2023-08-22 Monolithic 3D Inc. 3D semiconductor device and structure with single-crystal layers
US11164770B1 (en) 2010-11-18 2021-11-02 Monolithic 3D Inc. Method for producing a 3D semiconductor memory device and structure
US11094576B1 (en) 2010-11-18 2021-08-17 Monolithic 3D Inc. Methods for producing a 3D semiconductor memory device and structure
US11854857B1 (en) 2010-11-18 2023-12-26 Monolithic 3D Inc. Methods for producing a 3D semiconductor device and structure with memory cells and multiple metal layers
US11107721B2 (en) 2010-11-18 2021-08-31 Monolithic 3D Inc. 3D semiconductor device and structure with NAND logic
US11521888B2 (en) 2010-11-18 2022-12-06 Monolithic 3D Inc. 3D semiconductor device and structure with high-k metal gate transistors
US11508605B2 (en) 2010-11-18 2022-11-22 Monolithic 3D Inc. 3D semiconductor memory device and structure
US11615977B2 (en) 2010-11-18 2023-03-28 Monolithic 3D Inc. 3D semiconductor memory device and structure
US11923230B1 (en) 2010-11-18 2024-03-05 Monolithic 3D Inc. 3D semiconductor device and structure with bonding
US11569117B2 (en) 2010-11-18 2023-01-31 Monolithic 3D Inc. 3D semiconductor device and structure with single-crystal layers
US11784082B2 (en) 2010-11-18 2023-10-10 Monolithic 3D Inc. 3D semiconductor device and structure with bonding
US11211279B2 (en) 2010-11-18 2021-12-28 Monolithic 3D Inc. Method for processing a 3D integrated circuit and structure
US11482439B2 (en) 2010-11-18 2022-10-25 Monolithic 3D Inc. Methods for producing a 3D semiconductor memory device comprising charge trap junction-less transistors
US11164811B2 (en) 2012-04-09 2021-11-02 Monolithic 3D Inc. 3D semiconductor device with isolation layers and oxide-to-oxide bonding
US11735501B1 (en) 2012-04-09 2023-08-22 Monolithic 3D Inc. 3D semiconductor device and structure with metal layers and a connective path
US11694944B1 (en) 2012-04-09 2023-07-04 Monolithic 3D Inc. 3D semiconductor device and structure with metal layers and a connective path
US11476181B1 (en) 2012-04-09 2022-10-18 Monolithic 3D Inc. 3D semiconductor device and structure with metal layers
US11881443B2 (en) 2012-04-09 2024-01-23 Monolithic 3D Inc. 3D semiconductor device and structure with metal layers and a connective path
US11616004B1 (en) 2012-04-09 2023-03-28 Monolithic 3D Inc. 3D semiconductor device and structure with metal layers and a connective path
US11594473B2 (en) 2012-04-09 2023-02-28 Monolithic 3D Inc. 3D semiconductor device and structure with metal layers and a connective path
US11410912B2 (en) 2012-04-09 2022-08-09 Monolithic 3D Inc. 3D semiconductor device with vias and isolation layers
US11088050B2 (en) 2012-04-09 2021-08-10 Monolithic 3D Inc. 3D semiconductor device with isolation layers
US11967583B2 (en) 2012-12-22 2024-04-23 Monolithic 3D Inc. 3D semiconductor device and structure with metal layers
US11784169B2 (en) 2012-12-22 2023-10-10 Monolithic 3D Inc. 3D semiconductor device and structure with metal layers
US11961827B1 (en) 2012-12-22 2024-04-16 Monolithic 3D Inc. 3D semiconductor device and structure with metal layers
US11063024B1 (en) 2012-12-22 2021-07-13 Monlithic 3D Inc. Method to form a 3D semiconductor device and structure
US11217565B2 (en) 2012-12-22 2022-01-04 Monolithic 3D Inc. Method to form a 3D semiconductor device and structure
US11916045B2 (en) 2012-12-22 2024-02-27 Monolithic 3D Inc. 3D semiconductor device and structure with metal layers
US11309292B2 (en) 2012-12-22 2022-04-19 Monolithic 3D Inc. 3D semiconductor device and structure with metal layers
US11018116B2 (en) 2012-12-22 2021-05-25 Monolithic 3D Inc. Method to form a 3D semiconductor device and structure
US10903089B1 (en) 2012-12-29 2021-01-26 Monolithic 3D Inc. 3D semiconductor device and structure
US11430668B2 (en) 2012-12-29 2022-08-30 Monolithic 3D Inc. 3D semiconductor device and structure with bonding
US11177140B2 (en) 2012-12-29 2021-11-16 Monolithic 3D Inc. 3D semiconductor device and structure
US11004694B1 (en) 2012-12-29 2021-05-11 Monolithic 3D Inc. 3D semiconductor device and structure
US11430667B2 (en) 2012-12-29 2022-08-30 Monolithic 3D Inc. 3D semiconductor device and structure with bonding
US11087995B1 (en) 2012-12-29 2021-08-10 Monolithic 3D Inc. 3D semiconductor device and structure
US11935949B1 (en) 2013-03-11 2024-03-19 Monolithic 3D Inc. 3D semiconductor device and structure with metal layers and memory cells
US11869965B2 (en) 2013-03-11 2024-01-09 Monolithic 3D Inc. 3D semiconductor device and structure with metal layers and memory cells
US8902663B1 (en) 2013-03-11 2014-12-02 Monolithic 3D Inc. Method of maintaining a memory state
US11088130B2 (en) 2014-01-28 2021-08-10 Monolithic 3D Inc. 3D semiconductor device and structure
US10840239B2 (en) 2014-08-26 2020-11-17 Monolithic 3D Inc. 3D semiconductor device and structure
US11923374B2 (en) 2013-03-12 2024-03-05 Monolithic 3D Inc. 3D semiconductor device and structure with metal layers
US11398569B2 (en) 2013-03-12 2022-07-26 Monolithic 3D Inc. 3D semiconductor device and structure
US11574109B1 (en) 2013-04-15 2023-02-07 Monolithic 3D Inc Automation methods for 3D integrated circuits and devices
US11341309B1 (en) 2013-04-15 2022-05-24 Monolithic 3D Inc. Automation for monolithic 3D devices
US11270055B1 (en) 2013-04-15 2022-03-08 Monolithic 3D Inc. Automation for monolithic 3D devices
US11720736B2 (en) 2013-04-15 2023-08-08 Monolithic 3D Inc. Automation methods for 3D integrated circuits and devices
US11487928B2 (en) 2013-04-15 2022-11-01 Monolithic 3D Inc. Automation for monolithic 3D devices
US11031394B1 (en) 2014-01-28 2021-06-08 Monolithic 3D Inc. 3D semiconductor device and structure
US11107808B1 (en) 2014-01-28 2021-08-31 Monolithic 3D Inc. 3D semiconductor device and structure
US11011507B1 (en) 2015-04-19 2021-05-18 Monolithic 3D Inc. 3D semiconductor device and structure
US10825779B2 (en) 2015-04-19 2020-11-03 Monolithic 3D Inc. 3D semiconductor device and structure
US11056468B1 (en) 2015-04-19 2021-07-06 Monolithic 3D Inc. 3D semiconductor device and structure
US11956952B2 (en) 2015-08-23 2024-04-09 Monolithic 3D Inc. Semiconductor memory device and structure
US11937422B2 (en) 2015-11-07 2024-03-19 Monolithic 3D Inc. Semiconductor memory device and structure
US11978731B2 (en) 2015-09-21 2024-05-07 Monolithic 3D Inc. Method to produce a multi-level semiconductor memory device and structure
US11114427B2 (en) 2015-11-07 2021-09-07 Monolithic 3D Inc. 3D semiconductor processor and memory device and structure
US11114464B2 (en) 2015-10-24 2021-09-07 Monolithic 3D Inc. 3D semiconductor device and structure
US11991884B1 (en) 2015-10-24 2024-05-21 Monolithic 3D Inc. 3D semiconductor device and structure with logic and memory
US12016181B2 (en) 2015-10-24 2024-06-18 Monolithic 3D Inc. 3D semiconductor device and structure with logic and memory
US11296115B1 (en) 2015-10-24 2022-04-05 Monolithic 3D Inc. 3D semiconductor device and structure
US10847540B2 (en) 2015-10-24 2020-11-24 Monolithic 3D Inc. 3D semiconductor memory device and structure
US11711928B2 (en) 2016-10-10 2023-07-25 Monolithic 3D Inc. 3D memory devices and structures with control circuits
US11251149B2 (en) 2016-10-10 2022-02-15 Monolithic 3D Inc. 3D memory device and structure
US11930648B1 (en) 2016-10-10 2024-03-12 Monolithic 3D Inc. 3D memory devices and structures with metal layers
US11329059B1 (en) 2016-10-10 2022-05-10 Monolithic 3D Inc. 3D memory devices and structures with thinned single crystal substrates
US11869591B2 (en) 2016-10-10 2024-01-09 Monolithic 3D Inc. 3D memory devices and structures with control circuits
US11812620B2 (en) 2016-10-10 2023-11-07 Monolithic 3D Inc. 3D DRAM memory devices and structures with control circuits
US10249538B1 (en) 2017-10-03 2019-04-02 Globalfoundries Inc. Method of forming vertical field effect transistors with different gate lengths and a resulting structure
GB2594408B (en) 2018-12-10 2022-12-07 Rockley Photonics Ltd Optoelectronic device and method of manufacture thereof
US11158652B1 (en) 2019-04-08 2021-10-26 Monolithic 3D Inc. 3D memory semiconductor devices and structures
US10892016B1 (en) 2019-04-08 2021-01-12 Monolithic 3D Inc. 3D memory semiconductor devices and structures
US11296106B2 (en) 2019-04-08 2022-04-05 Monolithic 3D Inc. 3D memory semiconductor devices and structures
US11018156B2 (en) 2019-04-08 2021-05-25 Monolithic 3D Inc. 3D memory semiconductor devices and structures
US11763864B2 (en) 2019-04-08 2023-09-19 Monolithic 3D Inc. 3D memory semiconductor devices and structures with bit-line pillars
KR20200133092A (ko) 2019-05-16 2020-11-26 삼성전자주식회사 반도체 소자
WO2022066689A1 (en) * 2020-09-24 2022-03-31 Tokyo Electron Limited Epitaxial high-k etch stop layer for backside reveal integration
FR3121280B1 (fr) * 2021-03-29 2023-12-22 Commissariat Energie Atomique Transistor à effet de champ à structure verticale

Family Cites Families (19)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0799495A4 (en) 1994-11-10 1999-11-03 Lawrence Semiconductor Researc SILICON-GERMANIUM-CARBON COMPOSITIONS AND RELATED PROCESSES
US6323108B1 (en) 1999-07-27 2001-11-27 The United States Of America As Represented By The Secretary Of The Navy Fabrication ultra-thin bonded semiconductor layers
US6410371B1 (en) * 2001-02-26 2002-06-25 Advanced Micro Devices, Inc. Method of fabrication of semiconductor-on-insulator (SOI) wafer having a Si/SiGe/Si active layer
US20030227057A1 (en) 2002-06-07 2003-12-11 Lochtefeld Anthony J. Strained-semiconductor-on-insulator device structures
US7535100B2 (en) 2002-07-12 2009-05-19 The United States Of America As Represented By The Secretary Of The Navy Wafer bonding of thinned electronic materials and circuits to high performance substrates
US7132321B2 (en) 2002-10-24 2006-11-07 The United States Of America As Represented By The Secretary Of The Navy Vertical conducting power semiconductor devices implemented by deep etch
US6909186B2 (en) * 2003-05-01 2005-06-21 International Business Machines Corporation High performance FET devices and methods therefor
FR2858460B1 (fr) * 2003-07-30 2005-10-14 Soitec Silicon On Insulator Structure semiconducteur-sur-isolant contrainte ayant une tenue des contraintes aux hautes temperatures
US6815278B1 (en) 2003-08-25 2004-11-09 International Business Machines Corporation Ultra-thin silicon-on-insulator and strained-silicon-direct-on-insulator with hybrid crystal orientations
US7268063B1 (en) 2004-06-01 2007-09-11 University Of Central Florida Process for fabricating semiconductor component
US7282425B2 (en) * 2005-01-31 2007-10-16 International Business Machines Corporation Structure and method of integrating compound and elemental semiconductors for high-performance CMOS
US7387946B2 (en) * 2005-06-07 2008-06-17 Freescale Semiconductor, Inc. Method of fabricating a substrate for a planar, double-gated, transistor process
KR100653848B1 (ko) 2005-09-13 2006-12-05 (주)한비젼 3차원 적층형 이미지 센서 및 그의 제조방법
GB2467935B (en) * 2009-02-19 2013-10-30 Iqe Silicon Compounds Ltd Formation of thin layers of GaAs and germanium materials
US8598006B2 (en) * 2010-03-16 2013-12-03 International Business Machines Corporation Strain preserving ion implantation methods
US8466054B2 (en) 2010-12-13 2013-06-18 Io Semiconductor, Inc. Thermal conduction paths for semiconductor structures
US8481405B2 (en) * 2010-12-24 2013-07-09 Io Semiconductor, Inc. Trap rich layer with through-silicon-vias in semiconductor devices
EP3734645A1 (en) 2010-12-24 2020-11-04 QUALCOMM Incorporated Trap rich layer for semiconductor devices
WO2013019250A1 (en) 2011-08-02 2013-02-07 The Silanna Group Pty Ltd A photovoltaic device and a process for producing a photovoltaic device

Also Published As

Publication number Publication date
JP2017509158A (ja) 2017-03-30
CN106104749A (zh) 2016-11-09
KR20160116011A (ko) 2016-10-06
JP6360194B2 (ja) 2018-07-18
EP3123496A4 (en) 2017-11-08
KR20180049273A (ko) 2018-05-10
US9105689B1 (en) 2015-08-11
TWI641023B (zh) 2018-11-11
WO2015148212A1 (en) 2015-10-01
EP3123496A1 (en) 2017-02-01

Similar Documents

Publication Publication Date Title
TWI641023B (zh) 具有作爲蝕刻止擋之ＳｉＧｅＣ層之接合之半導體結構
US9269608B2 (en) Bonded semiconductor structure with SiGeC/SiGeBC layer as etch stop
US8124470B1 (en) Strained thin body semiconductor-on-insulator substrate and device
JP6432090B2 (ja) 異なる歪み状態を有するトランジスタチャネルを含む半導体層を製作する方法及び関連半導体層
CN109155278B (zh) 制造应变绝缘体上半导体衬底的方法
US9142673B2 (en) Devices and methods of forming bulk FinFETS with lateral seg for source and drain on dielectrics
CN109155277B (zh) 制造应变绝缘体上半导体衬底的方法
US8274115B2 (en) Hybrid orientation substrate with stress layer
JP2009152394A (ja) 半導体装置及びその製造方法
US9754968B2 (en) Structure and method to form III-V, Ge and SiGe fins on insulator
US20180204776A1 (en) Backside processed semiconductor device
JP2015517216A (ja) Ｃｍｏｓと非シリコン素子とのモノリシック一体化
JP4328708B2 (ja) Ｃｍｏｓデバイスの製造方法及びｃｍｏｓデバイスを備える構造
US20140097467A1 (en) Compressively strained soi substrate
CN105845615B (zh) 一种半导体器件的制造方法和电子装置
US9472671B1 (en) Method and structure for forming dually strained silicon

Legal Events

Date Code Title Description
MM4A Annulment or lapse of patent due to non-payment of fees