JP2017228734A5 - - Google Patents
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- JP2017228734A5 JP2017228734A5 JP2016125670A JP2016125670A JP2017228734A5 JP 2017228734 A5 JP2017228734 A5 JP 2017228734A5 JP 2016125670 A JP2016125670 A JP 2016125670A JP 2016125670 A JP2016125670 A JP 2016125670A JP 2017228734 A5 JP2017228734 A5 JP 2017228734A5
- Authority
- JP
- Japan
- Prior art keywords
- wiring
- layer
- insulating layer
- wiring structure
- wiring layer
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
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Priority Applications (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2016125670A JP6612189B2 (ja) | 2016-06-24 | 2016-06-24 | 配線基板、半導体装置、および、配線基板の製造方法 |
| US15/624,080 US10074601B2 (en) | 2016-06-24 | 2017-06-15 | Wiring substrate and semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2016125670A JP6612189B2 (ja) | 2016-06-24 | 2016-06-24 | 配線基板、半導体装置、および、配線基板の製造方法 |
Publications (3)
| Publication Number | Publication Date |
|---|---|
| JP2017228734A JP2017228734A (ja) | 2017-12-28 |
| JP2017228734A5 true JP2017228734A5 (OSRAM) | 2019-02-14 |
| JP6612189B2 JP6612189B2 (ja) | 2019-11-27 |
Family
ID=60677844
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP2016125670A Active JP6612189B2 (ja) | 2016-06-24 | 2016-06-24 | 配線基板、半導体装置、および、配線基板の製造方法 |
Country Status (2)
| Country | Link |
|---|---|
| US (1) | US10074601B2 (OSRAM) |
| JP (1) | JP6612189B2 (OSRAM) |
Families Citing this family (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US10264664B1 (en) | 2015-06-04 | 2019-04-16 | Vlt, Inc. | Method of electrically interconnecting circuit assemblies |
| US10785871B1 (en) * | 2018-12-12 | 2020-09-22 | Vlt, Inc. | Panel molded electronic assemblies with integral terminals |
| US10879157B2 (en) * | 2018-11-16 | 2020-12-29 | Xilinx, Inc. | High density substrate and stacked silicon package assembly having the same |
| JP7509395B2 (ja) * | 2019-10-30 | 2024-07-02 | 株式会社ライジングテクノロジーズ | 配線基板 |
| TWI764404B (zh) | 2020-08-24 | 2022-05-11 | 錼創顯示科技股份有限公司 | 拼接式微型發光二極體顯示面板 |
| US20230420353A1 (en) * | 2022-06-23 | 2023-12-28 | Intel Corporation | Asymmetrical dielectric-to-metal adhesion architecture for electronic packages |
| JP2024086199A (ja) * | 2022-12-16 | 2024-06-27 | イビデン株式会社 | 配線基板およびその製造方法 |
Family Cites Families (12)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5916453A (en) * | 1996-09-20 | 1999-06-29 | Fujitsu Limited | Methods of planarizing structures on wafers and substrates by polishing |
| JPH10322024A (ja) * | 1997-05-16 | 1998-12-04 | Hitachi Ltd | 非貫通ビアホールを有するビルドアップ多層プリント配線板及びその製造方法 |
| JP3976954B2 (ja) * | 1999-08-27 | 2007-09-19 | 新光電気工業株式会社 | 多層配線基板の製造方法及び半導体装置 |
| US7565738B2 (en) * | 2004-05-31 | 2009-07-28 | Sanyo Electric Co., Ltd. | Method for manufacturing circuit device |
| JP2006019361A (ja) * | 2004-06-30 | 2006-01-19 | Sanyo Electric Co Ltd | 回路装置およびその製造方法 |
| KR100613375B1 (ko) * | 2004-08-13 | 2006-08-17 | 동부일렉트로닉스 주식회사 | 반도체 소자의 구리 배선 및 그 형성 방법 |
| US20070281464A1 (en) * | 2006-06-01 | 2007-12-06 | Shih-Ping Hsu | Multi-layer circuit board with fine pitches and fabricating method thereof |
| CN103843471A (zh) * | 2012-04-26 | 2014-06-04 | 日本特殊陶业株式会社 | 多层布线基板及其制造方法 |
| JP6169955B2 (ja) | 2013-04-17 | 2017-07-26 | 新光電気工業株式会社 | 配線基板及びその製造方法 |
| US9000302B2 (en) * | 2013-04-17 | 2015-04-07 | Shinko Electric Industries Co., Ltd. | Wiring board |
| JP6133227B2 (ja) * | 2014-03-27 | 2017-05-24 | 新光電気工業株式会社 | 配線基板及びその製造方法 |
| JP2015222753A (ja) * | 2014-05-22 | 2015-12-10 | イビデン株式会社 | プリント配線板及びその製造方法 |
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2016
- 2016-06-24 JP JP2016125670A patent/JP6612189B2/ja active Active
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2017
- 2017-06-15 US US15/624,080 patent/US10074601B2/en active Active