JP2017175116A - 基板処理の方法 - Google Patents
基板処理の方法 Download PDFInfo
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- JP2017175116A JP2017175116A JP2017015672A JP2017015672A JP2017175116A JP 2017175116 A JP2017175116 A JP 2017175116A JP 2017015672 A JP2017015672 A JP 2017015672A JP 2017015672 A JP2017015672 A JP 2017015672A JP 2017175116 A JP2017175116 A JP 2017175116A
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- 239000000758 substrate Substances 0.000 title claims abstract description 278
- 238000000034 method Methods 0.000 title claims abstract description 67
- 238000005498 polishing Methods 0.000 claims abstract description 91
- 230000000903 blocking effect Effects 0.000 claims description 25
- 239000000463 material Substances 0.000 claims description 23
- 239000011521 glass Substances 0.000 claims description 19
- 239000013078 crystal Substances 0.000 claims description 16
- 238000005530 etching Methods 0.000 claims description 9
- 150000001875 compounds Chemical class 0.000 claims description 8
- 235000012431 wafers Nutrition 0.000 description 111
- 230000003287 optical effect Effects 0.000 description 110
- 238000007517 polishing process Methods 0.000 description 33
- 238000005520 cutting process Methods 0.000 description 24
- 238000003384 imaging method Methods 0.000 description 14
- 238000003672 processing method Methods 0.000 description 13
- 239000004065 semiconductor Substances 0.000 description 10
- 239000002390 adhesive tape Substances 0.000 description 6
- 239000011248 coating agent Substances 0.000 description 6
- 238000000576 coating method Methods 0.000 description 6
- 238000000227 grinding Methods 0.000 description 6
- 229910052594 sapphire Inorganic materials 0.000 description 6
- 239000010980 sapphire Substances 0.000 description 6
- HBMJWWWQQXIZIP-UHFFFAOYSA-N silicon carbide Chemical compound [Si+]#[C-] HBMJWWWQQXIZIP-UHFFFAOYSA-N 0.000 description 5
- WSMQKESQZFQMFW-UHFFFAOYSA-N 5-methyl-pyrazole-3-carboxylic acid Chemical compound CC1=CC(C(O)=O)=NN1 WSMQKESQZFQMFW-UHFFFAOYSA-N 0.000 description 4
- JBRZTFJDHDCESZ-UHFFFAOYSA-N AsGa Chemical compound [As]#[Ga] JBRZTFJDHDCESZ-UHFFFAOYSA-N 0.000 description 4
- 229910052581 Si3N4 Inorganic materials 0.000 description 4
- 238000013459 approach Methods 0.000 description 4
- 230000015572 biosynthetic process Effects 0.000 description 4
- GQYHUHYESMUTHG-UHFFFAOYSA-N lithium niobate Chemical compound [Li+].[O-][Nb](=O)=O GQYHUHYESMUTHG-UHFFFAOYSA-N 0.000 description 4
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 4
- JMASRVWKEDWRBT-UHFFFAOYSA-N Gallium nitride Chemical compound [Ga]#N JMASRVWKEDWRBT-UHFFFAOYSA-N 0.000 description 3
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 3
- 239000000919 ceramic Substances 0.000 description 3
- 238000004519 manufacturing process Methods 0.000 description 3
- TWNQGVIAIRXVLR-UHFFFAOYSA-N oxo(oxoalumanyloxy)alumane Chemical compound O=[Al]O[Al]=O TWNQGVIAIRXVLR-UHFFFAOYSA-N 0.000 description 3
- 229910052710 silicon Inorganic materials 0.000 description 3
- 239000010703 silicon Substances 0.000 description 3
- PIGFYZPCRLYGLF-UHFFFAOYSA-N Aluminum nitride Chemical compound [Al]#N PIGFYZPCRLYGLF-UHFFFAOYSA-N 0.000 description 2
- 229910001218 Gallium arsenide Inorganic materials 0.000 description 2
- GPXJNWSHGFTCBW-UHFFFAOYSA-N Indium phosphide Chemical compound [In]#P GPXJNWSHGFTCBW-UHFFFAOYSA-N 0.000 description 2
- 229910004298 SiO 2 Inorganic materials 0.000 description 2
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 2
- MCMNRKCIXSYSNV-UHFFFAOYSA-N Zirconium dioxide Chemical compound O=[Zr]=O MCMNRKCIXSYSNV-UHFFFAOYSA-N 0.000 description 2
- 238000010586 diagram Methods 0.000 description 2
- HZXMRANICFIONG-UHFFFAOYSA-N gallium phosphide Chemical compound [Ga]#P HZXMRANICFIONG-UHFFFAOYSA-N 0.000 description 2
- RPQDHPTXJYYUPQ-UHFFFAOYSA-N indium arsenide Chemical compound [In]#[As] RPQDHPTXJYYUPQ-UHFFFAOYSA-N 0.000 description 2
- 238000003331 infrared imaging Methods 0.000 description 2
- 238000000608 laser ablation Methods 0.000 description 2
- 238000003698 laser cutting Methods 0.000 description 2
- HFGPZNIAWCZYJU-UHFFFAOYSA-N lead zirconate titanate Chemical compound [O-2].[O-2].[O-2].[O-2].[O-2].[Ti+4].[Zr+4].[Pb+2] HFGPZNIAWCZYJU-UHFFFAOYSA-N 0.000 description 2
- 229910052451 lead zirconate titanate Inorganic materials 0.000 description 2
- 229910052751 metal Inorganic materials 0.000 description 2
- 239000002184 metal Substances 0.000 description 2
- 230000004048 modification Effects 0.000 description 2
- 238000012986 modification Methods 0.000 description 2
- 150000004767 nitrides Chemical class 0.000 description 2
- 230000010355 oscillation Effects 0.000 description 2
- 229910052814 silicon oxide Inorganic materials 0.000 description 2
- PNEYBMLMFCGWSK-UHFFFAOYSA-N Alumina Chemical compound [O-2].[O-2].[O-2].[Al+3].[Al+3] PNEYBMLMFCGWSK-UHFFFAOYSA-N 0.000 description 1
- 229910000673 Indium arsenide Inorganic materials 0.000 description 1
- 229910052785 arsenic Inorganic materials 0.000 description 1
- RQNWIZPPADIBDY-UHFFFAOYSA-N arsenic atom Chemical compound [As] RQNWIZPPADIBDY-UHFFFAOYSA-N 0.000 description 1
- 230000015556 catabolic process Effects 0.000 description 1
- 230000007423 decrease Effects 0.000 description 1
- 238000006731 degradation reaction Methods 0.000 description 1
- 230000001419 dependent effect Effects 0.000 description 1
- 238000001312 dry etching Methods 0.000 description 1
- 230000005611 electricity Effects 0.000 description 1
- 229910052738 indium Inorganic materials 0.000 description 1
- APFVFJFRJDLVQX-UHFFFAOYSA-N indium atom Chemical compound [In] APFVFJFRJDLVQX-UHFFFAOYSA-N 0.000 description 1
- 239000011159 matrix material Substances 0.000 description 1
- 238000005192 partition Methods 0.000 description 1
- 238000001020 plasma etching Methods 0.000 description 1
- 239000004417 polycarbonate Substances 0.000 description 1
- 229920000515 polycarbonate Polymers 0.000 description 1
- 229910010271 silicon carbide Inorganic materials 0.000 description 1
- 239000000126 substance Substances 0.000 description 1
- 230000003746 surface roughness Effects 0.000 description 1
- 238000001039 wet etching Methods 0.000 description 1
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Abstract
【解決手段】本方法は、基板内に複数の穴領域23を形成するために、第2表面に沿った複数の位置において、第2表面の側から、基板に対してパルス状のレーザービームを適用する工程を備えている。各穴領域は、第2表面から第1表面に向かって延びている。各穴領域は、改変領域と改変領域内にて第2表面に開放した間隙を有している。本方法は、基板の厚みを調整するために、複数の穴領域が形成された基板の第2表面を研磨する工程を、更に備えている。
【選択図】図4
Description
パルス状のレーザービームは、分割線とは実質的に反対側の第2表面の領域における複数の位置にて、隣接する当該位置の間の距離、つまり隣接する位置の中心間の距離が、3μmから50μmの範囲、好ましくは5μmから40μmの範囲、より好ましくは8μmから30μmの範囲、であるように、基板に適用されて良い。複数の穴領域は、分割線の実質的に反対側の第2表面の領域において、隣接する穴領域の中心間の距離が、3μmから50μmの範囲、好ましくは5μmから40μmの範囲、より好ましくは8μmから30μmの範囲、であるように、形成されて良い。特に好ましくは、隣接する穴領域の中心間の距離は、8μmから10μmの範囲内である。
Claims (14)
- 複数のデバイス(21)が内部に形成されたデバイス領域(20)を有する第1表面(2a)と、この第1表面(2a)に対向する第2表面(2b)と、を有する基板の処理の方法であって、
前記基板(2)内に複数の穴領域(23)を形成するために、前記第2表面(2b)に沿った複数の位置において、当該第2表面(2b)の側から、前記基板(2)に対してパルス状のレーザービーム(LB)を適用する工程と、
前記基板の厚みを調節するために、前記複数の穴領域(23)が形成された前記基板(2)の前記第2表面(2b)を研磨する工程と、
を備え、
各穴領域(23)は、前記第2表面(2b)から前記第1表面(2a)に向かって延びており、
各穴領域(23)は、改変領域(232)と、当該改変領域(232)内にて前記第2表面(2b)に開放した空間(231)と、を有している
ことを特徴とする方法。 - 前記パルス状のレーザービーム(LB)は、当該パルス状のレーザービーム(LB)の焦点(P)が前記第2表面(2b)上に位置付けられる、という条件で、または、前記第2表面(2b)から前記第1表面(2a)に向かう方向において当該第2表面(2b)からある距離に位置付けられる、という条件で、前記基板(2)に適用される
ことを特徴とする請求項1に記載の方法。 - 前記パルス状のレーザービーム(LB)は、当該パルス状のレーザービーム(LB)の焦点(P)が前記第2表面(2b)上に位置付けられる、という条件で、または、前記第2表面(2b)から前記第1表面(2a)に向かう方向とは逆方向において当該第2表面(2b)からある距離に位置付けられる、という条件で、前記基板(2)に適用される
ことを特徴とする請求項1に記載の方法。 - 前記基板(2)は、単結晶基板、ガラス基板、化合物基板または多結晶基板である
ことを特徴とする請求項1乃至3のいずれか一項に記載の方法。 - 前記改変領域(232)は、アモルファス領域またはクラックが形成された領域である
ことを特徴とする請求項1乃至4のいずれか一項に記載の方法。 - 前記穴領域(23)は、前記第2表面(2b)から前記第1表面(2a)に向かう方向に、前記基板(2)の厚みの一部のみに沿って延在するように、形成されている
ことを特徴とする請求項1乃至5のいずれか一項に記載の方法。 - 前記第2表面(2b)は、当該第2表面(2b)から前記第1表面(2a)に向かう方向に、前記穴領域(23)の延び全体に沿って、研磨される
ことを特徴とする請求項1乃至6のいずれか一項に記載の方法。 - 前記穴領域(23)は、前記第2表面(2b)の全体にわたって形成されている
ことを特徴とする請求項1乃至7のいずれか一項に記載の方法。 - 前記第1表面(2a)上には複数の分割線(22)が存在しており、当該分割線(22)は、前記複数のデバイス(21)を区画しており、
前記穴領域(23)は、前記分割線(22)と実質的に対向する前記第2表面(2b)の領域内のみに、形成されている
ことを特徴とする請求項1乃至7のいずれか一項に記載の方法。 - 前記第1表面(2a)上には少なくとも1つのビームブロック層(24)が存在しており、
前記少なくとも1つのビームブロック層(24)は、前記第1表面(2a)から前記第2表面(2b)に向かう方向において、前記デバイス(21)の下方に配置されており、
前記少なくとも1つのビームブロック層(24)は、前記パルス状のレーザービーム(LB)を透過しない
ことを特徴とする請求項1乃至9のいずれか一項に記載の方法。 - 前記少なくとも1つのビームブロック層(24)は、少なくとも前記デバイス領域(20)の全体にわたって、延在している
ことを特徴とする請求項10に記載の方法。 - 前記第1表面(2a)上に複数の個別のビームブロック層(24)が存在しており、
各ビームブロック層(24)は、前記第1表面(2a)から前記第2表面(2b)に向かう方向において、それぞれのデバイス(21)の下方に配置されている
ことを特徴とする請求項10に記載の方法。 - 前記第2表面の研磨工程の後で、当該第2表面(2b)を磨き上げる工程、及び/または、エッチングする工程、を更に備えた
ことを特徴とする請求項1乃至12のいずれか一項に記載の方法。 - 前記基板(2)は、前記パルス状のレーザービーム(LB)に対して透過性を有する材料から作られている
ことを特徴とする請求項1乃至13のいずれか一項に記載の方法。
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