JP2017102923A5 - - Google Patents

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JP2017102923A5
JP2017102923A5 JP2016229897A JP2016229897A JP2017102923A5 JP 2017102923 A5 JP2017102923 A5 JP 2017102923A5 JP 2016229897 A JP2016229897 A JP 2016229897A JP 2016229897 A JP2016229897 A JP 2016229897A JP 2017102923 A5 JP2017102923 A5 JP 2017102923A5
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JP
Japan
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accelerator
array
dram
logic
virtual machine
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JP2016229897A
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English (en)
Japanese (ja)
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JP2017102923A (ja
JP6738262B2 (ja
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Priority claimed from US15/086,010 external-priority patent/US10013212B2/en
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JP2016229897A 2015-11-30 2016-11-28 加速器コントローラ及びその加速器ロジックローディング方法 Active JP6738262B2 (ja)

Applications Claiming Priority (4)

Application Number Priority Date Filing Date Title
US201562261306P 2015-11-30 2015-11-30
US62/261306 2015-11-30
US15/086,010 US10013212B2 (en) 2015-11-30 2016-03-30 System architecture with memory channel DRAM FPGA module
US15/086010 2016-03-30

Publications (3)

Publication Number Publication Date
JP2017102923A JP2017102923A (ja) 2017-06-08
JP2017102923A5 true JP2017102923A5 (cg-RX-API-DMAC7.html) 2019-12-05
JP6738262B2 JP6738262B2 (ja) 2020-08-12

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JP2016229897A Active JP6738262B2 (ja) 2015-11-30 2016-11-28 加速器コントローラ及びその加速器ロジックローディング方法

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US (1) US10013212B2 (cg-RX-API-DMAC7.html)
JP (1) JP6738262B2 (cg-RX-API-DMAC7.html)
KR (1) KR102380776B1 (cg-RX-API-DMAC7.html)
CN (1) CN106814662B (cg-RX-API-DMAC7.html)
TW (1) TWI706256B (cg-RX-API-DMAC7.html)

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