CN109952565A - 内存访问技术 - Google Patents

内存访问技术 Download PDF

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Publication number
CN109952565A
CN109952565A CN201680090713.9A CN201680090713A CN109952565A CN 109952565 A CN109952565 A CN 109952565A CN 201680090713 A CN201680090713 A CN 201680090713A CN 109952565 A CN109952565 A CN 109952565A
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China
Prior art keywords
memory
access
access request
cache lines
controller hub
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CN201680090713.9A
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CN109952565B (zh
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肖世海
邹乔莎
杨伟
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Huawei Technologies Co Ltd
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Huawei Technologies Co Ltd
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    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
    • G06F12/0888—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches using selective caching, e.g. bypass
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
    • G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
    • G06F3/0601—Interfaces specially adapted for storage systems
    • G06F3/0628—Interfaces specially adapted for storage systems making use of a particular technique
    • G06F3/0655—Vertical data movement, i.e. input-output transfer; data movement between one or more hosts and one or more storage devices
    • G06F3/0659—Command handling arrangements, e.g. command buffers, queues, command scheduling
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
    • G06F12/0877—Cache access modes
    • G06F12/0879—Burst mode
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
    • G06F12/0891—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches using clearing, invalidating or resetting means
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
    • G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
    • G06F3/0601—Interfaces specially adapted for storage systems
    • G06F3/0602—Interfaces specially adapted for storage systems specifically adapted to achieve a particular effect
    • G06F3/0604—Improving or facilitating administration, e.g. storage management
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
    • G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
    • G06F3/0601—Interfaces specially adapted for storage systems
    • G06F3/0628—Interfaces specially adapted for storage systems making use of a particular technique
    • G06F3/0638—Organizing or formatting or addressing of data
    • G06F3/064—Management of blocks
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
    • G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
    • G06F3/0601—Interfaces specially adapted for storage systems
    • G06F3/0668—Interfaces specially adapted for storage systems adopting a particular infrastructure
    • G06F3/0671—In-line storage system
    • G06F3/0673—Single storage device
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
    • G06F12/0893—Caches characterised by their organisation or structure
    • G06F12/0895—Caches characterised by their organisation or structure of parts of caches, e.g. directory or tag array
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2212/00—Indexing scheme relating to accessing, addressing or allocation within memory systems or architectures
    • G06F2212/10—Providing a specific technical effect
    • G06F2212/1016—Performance improvement
    • G06F2212/1024—Latency reduction
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2212/00—Indexing scheme relating to accessing, addressing or allocation within memory systems or architectures
    • G06F2212/20—Employing a main memory using a specific memory technology
    • G06F2212/202—Non-volatile memory
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2212/00—Indexing scheme relating to accessing, addressing or allocation within memory systems or architectures
    • G06F2212/60—Details of cache memory
    • G06F2212/608—Details relating to cache mapping

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  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Human Computer Interaction (AREA)
  • Memory System Of A Hierarchy Structure (AREA)

Abstract

一种内存访问技术，应用于包括第一级存储器、第二级存储器和内存控制器的计算机系统中。第一级存储器用于缓存所述第二级存储器中的数据。所述内存访问技术中，对于访问与第一级存储器中的第一缓存行具有映射关系的不同内存块的多个访问请求，内存控制器可以将该多个访问请求的标签集中在一起与所述第一缓存行的标签进行比较，以判断所述多个访问请求是否命中所述第一级存储器。在处理所述多个访问请求的过程中，内存控制器只需要从所述第一级存储器中读取一次所述第一缓存行的标签，从而减少了从所述第一级存储器中读取所述第一缓存行的标签的次数，缩短了内存访问延时，提高了内存访问效率。

Description

PCT国内申请，说明书已公开。

Claims (21)

  1. PCT国内申请，权利要求书已公开。
CN201680090713.9A 2016-11-16 2016-11-16 内存访问技术 Active CN109952565B (zh)

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EP (1) EP3534265A4 (zh)
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CN111143244A (zh) * 2019-12-30 2020-05-12 海光信息技术有限公司 计算机设备的内存访问方法和计算机设备
CN111241009A (zh) * 2019-12-31 2020-06-05 西安翔腾微电子科技有限公司 一种数据反馈方法及装置
CN111259384A (zh) * 2020-01-17 2020-06-09 中国科学院计算技术研究所 一种基于缓存随机无效的处理器瞬态攻击防御方法
CN114930306A (zh) * 2020-03-23 2022-08-19 华为技术有限公司 带宽均衡方法和装置
CN116561020A (zh) * 2023-05-15 2023-08-08 合芯科技(苏州)有限公司 一种混合缓存粒度下的请求处理方法、设备及存储介质
CN117331853A (zh) * 2023-10-11 2024-01-02 上海合芯数字科技有限公司 缓存处理方法、装置、电子设备及介质

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CN101201800A (zh) * 2007-12-21 2008-06-18 福建星网锐捷网络有限公司 数据处理方法和装置
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CN105786400A (zh) * 2014-12-25 2016-07-20 研祥智能科技股份有限公司 一种异构混合内存组件、系统及存储方法
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* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN111143244A (zh) * 2019-12-30 2020-05-12 海光信息技术有限公司 计算机设备的内存访问方法和计算机设备
CN111241009A (zh) * 2019-12-31 2020-06-05 西安翔腾微电子科技有限公司 一种数据反馈方法及装置
CN111241009B (zh) * 2019-12-31 2023-05-16 西安翔腾微电子科技有限公司 一种数据反馈方法及装置
CN111259384A (zh) * 2020-01-17 2020-06-09 中国科学院计算技术研究所 一种基于缓存随机无效的处理器瞬态攻击防御方法
CN111259384B (zh) * 2020-01-17 2022-06-14 中国科学院计算技术研究所 一种基于缓存随机无效的处理器瞬态攻击防御方法
CN114930306A (zh) * 2020-03-23 2022-08-19 华为技术有限公司 带宽均衡方法和装置
CN116561020A (zh) * 2023-05-15 2023-08-08 合芯科技(苏州)有限公司 一种混合缓存粒度下的请求处理方法、设备及存储介质
CN116561020B (zh) * 2023-05-15 2024-04-09 合芯科技(苏州)有限公司 一种混合缓存粒度下的请求处理方法、设备及存储介质
CN117331853A (zh) * 2023-10-11 2024-01-02 上海合芯数字科技有限公司 缓存处理方法、装置、电子设备及介质
CN117331853B (zh) * 2023-10-11 2024-04-16 上海合芯数字科技有限公司 缓存处理方法、装置、电子设备及介质

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Publication number Publication date
EP3534265A1 (en) 2019-09-04
WO2018090255A1 (zh) 2018-05-24
EP3534265A4 (en) 2019-10-30
US11210020B2 (en) 2021-12-28
CN109952565B (zh) 2021-10-22
US20190272122A1 (en) 2019-09-05

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