JP6738262B2 - 加速器コントローラ及びその加速器ロジックローディング方法 - Google Patents

加速器コントローラ及びその加速器ロジックローディング方法 Download PDF

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JP6738262B2
JP6738262B2 JP2016229897A JP2016229897A JP6738262B2 JP 6738262 B2 JP6738262 B2 JP 6738262B2 JP 2016229897 A JP2016229897 A JP 2016229897A JP 2016229897 A JP2016229897 A JP 2016229897A JP 6738262 B2 JP6738262 B2 JP 6738262B2
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dram
accelerator
array
logic
memory
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JP2017102923A (ja
JP2017102923A5 (cg-RX-API-DMAC7.html
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宏 忠 ズン，
宏 忠 ズン，
牧 天 張，
牧 天 張，
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Samsung Electronics Co Ltd
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    • G—PHYSICS
    • G05—CONTROLLING; REGULATING
    • G05B—CONTROL OR REGULATING SYSTEMS IN GENERAL; FUNCTIONAL ELEMENTS OF SUCH SYSTEMS; MONITORING OR TESTING ARRANGEMENTS FOR SUCH SYSTEMS OR ELEMENTS
    • G05B19/00—Programme-control systems
    • G05B19/02—Programme-control systems electric
    • G05B19/04—Programme control other than numerical control, i.e. in sequence controllers or logic controllers
    • G05B19/042—Programme control other than numerical control, i.e. in sequence controllers or logic controllers using digital processors
    • G05B19/0423—Input/output
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
    • G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
    • G06F3/0601—Interfaces specially adapted for storage systems
    • G06F3/0628—Interfaces specially adapted for storage systems making use of a particular technique
    • G06F3/0662—Virtualisation aspects
    • G06F3/0665—Virtualisation aspects at area level, e.g. provisioning of virtual or logical volumes
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/44—Arrangements for executing specific programs
    • G06F9/455—Emulation; Interpretation; Software simulation, e.g. virtualisation or emulation of application or operating system execution engines
    • G06F9/45533—Hypervisors; Virtual machine monitors
    • G06F9/45558—Hypervisor-specific management and integration aspects
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/10—Address translation
    • G06F12/1009—Address translation using page tables, e.g. page table structures
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
    • G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
    • G06F3/0601—Interfaces specially adapted for storage systems
    • G06F3/0602—Interfaces specially adapted for storage systems specifically adapted to achieve a particular effect
    • G06F3/061—Improving I/O performance
    • G06F3/0613—Improving I/O performance in relation to throughput
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
    • G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
    • G06F3/0601—Interfaces specially adapted for storage systems
    • G06F3/0668—Interfaces specially adapted for storage systems adopting a particular infrastructure
    • G06F3/0671—In-line storage system
    • G06F3/0683—Plurality of storage devices
    • G06F3/0689—Disk arrays, e.g. RAID, JBOD
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/30003—Arrangements for executing specific machine instructions
    • G06F9/3004—Arrangements for executing specific machine instructions to perform operations on memory
    • G06F9/30043—LOAD or STORE instructions; Clear instruction
    • G—PHYSICS
    • G05—CONTROLLING; REGULATING
    • G05B—CONTROL OR REGULATING SYSTEMS IN GENERAL; FUNCTIONAL ELEMENTS OF SUCH SYSTEMS; MONITORING OR TESTING ARRANGEMENTS FOR SUCH SYSTEMS OR ELEMENTS
    • G05B2219/00—Program-control systems
    • G05B2219/20—Pc systems
    • G05B2219/25—Pc structure of the system
    • G05B2219/25257—Microcontroller
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/44—Arrangements for executing specific programs
    • G06F9/455—Emulation; Interpretation; Software simulation, e.g. virtualisation or emulation of application or operating system execution engines
    • G06F9/45533—Hypervisors; Virtual machine monitors
    • G06F9/45558—Hypervisor-specific management and integration aspects
    • G06F2009/45583—Memory management, e.g. access or allocation
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2212/00—Indexing scheme relating to accessing, addressing or allocation within memory systems or architectures
    • G06F2212/10—Providing a specific technical effect
    • G06F2212/1016—Performance improvement
    • G06F2212/1024—Latency reduction
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2212/00—Indexing scheme relating to accessing, addressing or allocation within memory systems or architectures
    • G06F2212/15—Use in a specific computing environment
    • G06F2212/152—Virtualized environment, e.g. logically partitioned system
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2212/00—Indexing scheme relating to accessing, addressing or allocation within memory systems or architectures
    • G06F2212/62—Details of cache specific to multiprocessor cache arrangements
    • G06F2212/621—Coherency control relating to peripheral accessing, e.g. from DMA or I/O device

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  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • Software Systems (AREA)
  • Human Computer Interaction (AREA)
  • Automation & Control Theory (AREA)
  • Logic Circuits (AREA)
  • Stored Programmes (AREA)
  • Memory System (AREA)
JP2016229897A 2015-11-30 2016-11-28 加速器コントローラ及びその加速器ロジックローディング方法 Active JP6738262B2 (ja)

Applications Claiming Priority (4)

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US201562261306P 2015-11-30 2015-11-30
US62/261306 2015-11-30
US15/086010 2016-03-30
US15/086,010 US10013212B2 (en) 2015-11-30 2016-03-30 System architecture with memory channel DRAM FPGA module

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JP2017102923A JP2017102923A (ja) 2017-06-08
JP2017102923A5 JP2017102923A5 (cg-RX-API-DMAC7.html) 2019-12-05
JP6738262B2 true JP6738262B2 (ja) 2020-08-12

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CN (1) CN106814662B (cg-RX-API-DMAC7.html)
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Families Citing this family (20)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US10338135B2 (en) 2016-09-28 2019-07-02 Amazon Technologies, Inc. Extracting debug information from FPGAs in multi-tenant environments
US11099894B2 (en) * 2016-09-28 2021-08-24 Amazon Technologies, Inc. Intermediate host integrated circuit between virtual machine instance and customer programmable logic
US10162921B2 (en) 2016-09-29 2018-12-25 Amazon Technologies, Inc. Logic repository service
US10250572B2 (en) 2016-09-29 2019-04-02 Amazon Technologies, Inc. Logic repository service using encrypted configuration data
US10423438B2 (en) 2016-09-30 2019-09-24 Amazon Technologies, Inc. Virtual machines controlling separate subsets of programmable hardware
US10642492B2 (en) 2016-09-30 2020-05-05 Amazon Technologies, Inc. Controlling access to previously-stored logic in a reconfigurable logic device
US11115293B2 (en) 2016-11-17 2021-09-07 Amazon Technologies, Inc. Networked programmable logic service provider
US10747565B2 (en) * 2017-04-18 2020-08-18 Amazon Technologies, Inc. Virtualization of control and status signals
US10503551B2 (en) * 2017-06-07 2019-12-10 Dell Products L.P. Coordinating FPGA services using cascaded FPGA service managers
US11169834B2 (en) * 2017-09-28 2021-11-09 Intel Corporation Dynamic platform feature tuning based on virtual machine runtime requirements
CN108897706B (zh) * 2018-05-10 2021-07-23 北京融芯微科技有限公司 一种加速器接口
KR102615443B1 (ko) * 2018-05-25 2023-12-20 에스케이하이닉스 주식회사 머신 러닝 장치 및 이를 이용한 머신 러닝 시스템
US10884949B2 (en) * 2019-04-05 2021-01-05 International Business Machines Corporation On-chip logic accelerator
CN112506087B (zh) * 2019-09-16 2024-07-23 阿里巴巴集团控股有限公司 Fpga加速系统和方法、电子设备以及计算机可读存储介质
US11403111B2 (en) 2020-07-17 2022-08-02 Micron Technology, Inc. Reconfigurable processing-in-memory logic using look-up tables
JP7619015B2 (ja) * 2020-11-18 2025-01-22 大日本印刷株式会社 インプリント装置、インプリント方法及び凹凸構造体の製造方法
CN112580285A (zh) * 2020-12-14 2021-03-30 深圳宏芯宇电子股份有限公司 嵌入式服务器子系统及其配置方法
US11355170B1 (en) 2020-12-16 2022-06-07 Micron Technology, Inc. Reconfigurable processing-in-memory logic
CN112947282B (zh) * 2021-03-08 2023-06-20 电子科技大学 一种应用于电源门控fpga结构中的新型隔离单元
KR20230016110A (ko) 2021-07-23 2023-02-01 삼성전자주식회사 메모리 모듈, 이를 포함하는 시스템, 및 메모리 모듈의 동작 방법

Family Cites Families (25)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP3106998B2 (ja) * 1997-04-11 2000-11-06 日本電気株式会社 メモリ付加型プログラマブルロジックｌｓｉ
JP3738802B2 (ja) * 1998-02-10 2006-01-25 富士ゼロックス株式会社 情報処理システム
JP3809727B2 (ja) * 1998-06-17 2006-08-16 富士ゼロックス株式会社 情報処理システム、回路情報管理方法および回路情報記憶装置
US9195784B2 (en) 1998-08-31 2015-11-24 Cadence Design Systems, Inc. Common shared memory in a verification system
US7206899B2 (en) * 2003-12-29 2007-04-17 Intel Corporation Method, system, and program for managing data transfer and construction
US20060129762A1 (en) * 2004-12-10 2006-06-15 Via Technologies, Inc. Accessible buffer for use in parallel with a filling cacheline
DE112006002300B4 (de) 2005-09-02 2013-12-19 Google, Inc. Vorrichtung zum Stapeln von DRAMs
US20070129926A1 (en) * 2005-12-01 2007-06-07 Verheyen Henry T Hardware acceleration system for simulation of logic and memory
JP4191219B2 (ja) * 2006-10-30 2008-12-03 エルピーダメモリ株式会社 メモリ回路、半導体装置及びメモリ回路の制御方法
CN101354677B (zh) * 2008-09-11 2014-12-03 青岛海信移动通信技术股份有限公司 一种应用程序运行状态的检测方法及装置
CN101477831A (zh) * 2009-01-22 2009-07-08 上海广电（集团）有限公司中央研究院 一种基于fpga器件的dram控制器
CN101924550A (zh) * 2009-06-11 2010-12-22 复旦大学 一种采用增益单元eDRAM的查找表
US8910153B2 (en) * 2009-07-13 2014-12-09 Hewlett-Packard Development Company, L. P. Managing virtualized accelerators using admission control, load balancing and scheduling
CN101717817B (zh) * 2009-07-17 2011-11-23 中国人民解放军国防科学技术大学 对基于随机上下文无关文法的rna二级结构预测进行加速的方法
US8589851B2 (en) * 2009-12-15 2013-11-19 Memoir Systems, Inc. Intelligent memory system compiler
JP2012084220A (ja) * 2011-10-25 2012-04-26 Fujitsu Semiconductor Ltd メモリシステム
WO2013081629A1 (en) * 2011-12-02 2013-06-06 Empire Technology Development. Llc Integrated circuits as a service
US9396020B2 (en) * 2012-03-30 2016-07-19 Intel Corporation Context switching mechanism for a processing core having a general purpose CPU core and a tightly coupled accelerator
EP3654178B1 (en) * 2012-03-30 2023-07-12 Intel Corporation Mechanism for issuing requests to an accelerator from multiple threads
US9697147B2 (en) * 2012-08-06 2017-07-04 Advanced Micro Devices, Inc. Stacked memory device with metadata management
US8984368B2 (en) * 2012-10-11 2015-03-17 Advanced Micro Devices, Inc. High reliability memory controller
US8880809B2 (en) 2012-10-29 2014-11-04 Advanced Micro Devices Inc. Memory controller with inter-core interference detection
US9098402B2 (en) * 2012-12-21 2015-08-04 Intel Corporation Techniques to configure a solid state drive to operate in a storage mode or a memory mode
US9274951B2 (en) * 2013-05-31 2016-03-01 Altera Corporation Cache memory controller for accelerated data transfer
US9954533B2 (en) * 2014-12-16 2018-04-24 Samsung Electronics Co., Ltd. DRAM-based reconfigurable logic

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Publication number Publication date
US20170153854A1 (en) 2017-06-01
CN106814662A (zh) 2017-06-09
KR20170063334A (ko) 2017-06-08
JP2017102923A (ja) 2017-06-08
CN106814662B (zh) 2019-06-25
US10013212B2 (en) 2018-07-03
TW201723865A (zh) 2017-07-01
TWI706256B (zh) 2020-10-01
KR102380776B1 (ko) 2022-04-01

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