JP2017098499A - Mim capacitor and method for manufacturing the same - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a semiconductor device capable of reducing an occupied area of an MIM capacitor, and a method for manufacturing the same.SOLUTION: A first conductive film 2 is formed on a substrate 1. A first insulating film 3 is formed on the first conductive film 2. A second conductive film 4 is formed on the first insulating film 3. The second conductive film 4 is connected to the first conductive film 2, and includes an opening 5. A trench structure 6 is formed in the first insulating film 3. The trench structure 6 is connected to the opening 5, and wider than the opening 5. A first dielectric film 7 and a third conductive film 8 are formed in this order on a floor and a sidewall of the trench structure 6, and on an inner wall including a ceiling.SELECTED DRAWING: Figure 1

Description

  The present invention relates to an MIM capacitor capable of reducing an occupied area and a method for manufacturing the same.

  An MIM (Metal Insulator Metal) capacitor is used as one of constituent elements of a semiconductor device such as an MMIC (Microwave Monolithic IC) (see, for example, Patent Document 1).

JP 2003-303896 A

  MIM capacitors usually occupy 20 to 30% in a semiconductor device and occupy a large area. For this reason, the MIM capacitor is an obstacle to reducing the area of the semiconductor device. Since the reduction of the area of the semiconductor device greatly contributes to the reduction of the manufacturing cost, it is important to reduce the area occupied by the MIM capacitor in the semiconductor device.

  The present invention has been made to solve the above-described problems, and an object of the present invention is to obtain an MIM capacitor capable of reducing an occupied area and a method for manufacturing the same.

  The MIM capacitor according to the present invention includes a substrate, a first conductive film formed on the substrate, a first insulating film formed on the first conductive film, and on the first insulating film. A second conductive film connected to the first conductive film and having an opening; and a digging structure formed in the first insulating film, connected to the opening, and wider than the opening. And a first dielectric film and a third conductive film formed in order on the inner wall including the floor, side walls, and ceiling of the digging structure.

  In the present invention, the MIM capacitor is constituted by the first dielectric film and the third conductive film formed on the inner wall of the digging structure and the first and second conductive films around the first dielectric film and the third conductive film. Thus, the surface area of the MIM capacitor is expanded by effectively utilizing the area of the inner wall of the digging structure. Thereby, the area occupied by the MIM capacitor in the semiconductor device can be reduced.

It is sectional drawing which shows the MIM capacitor which concerns on Embodiment 1 of this invention. It is sectional drawing which shows the manufacturing method of the MIM capacitor which concerns on Embodiment 1 of this invention. It is sectional drawing which shows the manufacturing method of the MIM capacitor which concerns on Embodiment 1 of this invention. It is sectional drawing which shows the manufacturing method of the MIM capacitor which concerns on Embodiment 1 of this invention. It is sectional drawing which shows the manufacturing method of the MIM capacitor which concerns on Embodiment 1 of this invention. It is sectional drawing which shows the manufacturing method of the MIM capacitor which concerns on Embodiment 1 of this invention. It is sectional drawing which shows the manufacturing method of the MIM capacitor which concerns on Embodiment 1 of this invention. It is sectional drawing which shows the manufacturing method of the MIM capacitor which concerns on Embodiment 1 of this invention. It is sectional drawing which shows the manufacturing method of the MIM capacitor which concerns on Embodiment 1 of this invention. It is sectional drawing which shows the manufacturing method of the MIM capacitor which concerns on Embodiment 1 of this invention. It is sectional drawing which shows the MIM capacitor which concerns on Embodiment 2 of this invention. It is sectional drawing which shows the MIM capacitor which concerns on Embodiment 3 of this invention. It is sectional drawing which shows the MIM capacitor which concerns on Embodiment 4 of this invention. It is sectional drawing which shows the MIM capacitor which concerns on Embodiment 5 of this invention. It is sectional drawing which shows the manufacturing method of the MIM capacitor which concerns on Embodiment 5 of this invention. It is sectional drawing which shows the manufacturing method of the MIM capacitor which concerns on Embodiment 5 of this invention.

  A semiconductor device and a manufacturing method thereof according to an embodiment of the present invention will be described with reference to the drawings. The same or corresponding components are denoted by the same reference numerals, and repeated description may be omitted.

Embodiment 1 FIG.
FIG. 1 is a cross-sectional view showing an MIM capacitor according to Embodiment 1 of the present invention. A conductive film 2 is formed on the semi-insulating substrate 1. An insulating film 3 is formed on the conductive film 2. A conductive film 4 is formed on the insulating film 3. The conductive film 4 is connected to the conductive film 2 and has an opening 5.

  A digging structure 6 is formed in the insulating film 3. The digging structure 6 is connected to the opening 5 and is wider than the opening 5. A dielectric film 7 and a conductive film 8 are sequentially formed on the inner wall including the floor, side walls, and ceiling of the digging structure 6. The dielectric film 7 and the conductive film 8 are also formed on the conductive film 4. A dielectric film 9 is formed so as to cover them. The lower electrode 10 is connected to the conductive films 2 and 4, and the upper electrode 11 is connected to the conductive film 8.

  Next, a method for manufacturing the MIM capacitor according to the present embodiment will be described. 2 to 11 are cross-sectional views showing a method for manufacturing the MIM capacitor according to the first embodiment of the present invention. First, as shown in FIG. 2, a conductive film 2 is formed on a semi-insulating substrate 1 by vapor deposition or sputtering, and patterned by lift-off.

  Next, as shown in FIG. 3, an insulating film 3 is formed on the conductive film 2 by a CVD (Chemical Vapor Deposition) method or a sputtering method. Next, as shown in FIG. 4, a contact hole 12 is formed in the insulating film 3 by a dry etcher or the like.

  Next, as shown in FIG. 5, a conductive film 4 is formed on the insulating film 3 and in the contact hole 12 by vapor deposition or sputtering. The conductive film 4 is connected to the conductive film 2 through the contact hole 12. The conductive film 4 is patterned by a lift method to form an opening 5.

  Next, as shown in FIG. 6, a portion other than the periphery of the opening 5 is covered with a resist 13. Then, the insulating film 3 is side-etched from the opening 5 by wet etching using a chemical solution such as hydrofluoric acid or buffered hydrofluoric acid, so that the digging structure 6 wider than the opening 5 is formed. Thereafter, the resist 13 is removed. In FIG. 6, the side etching is stopped halfway, but the insulating film 3 may be completely etched.

  Next, as shown in FIG. 7, the dielectric film 7 and the conductive film 8 are sequentially deposited on the inner wall including the floor, the side wall, and the ceiling of the digging structure 6, the side wall of the opening 5, and the conductive film 4. It is formed by the Atomic Layer Deposition method. Next, as shown in FIG. 8, the dielectric film 7 and the conductive film 8 on the conductive film 4 are patterned by a dry etcher or the like.

  Next, as shown in FIG. 9, a dielectric film 9 is formed on the entire surface including the inside of the digging structure 6 by the ALD method. This dielectric film 9 is also used as a protective film inside the digging structure 6. If protection inside the digging structure 6 is unnecessary, the dielectric film 9 may be formed by CVD or sputtering. Next, as shown in FIG. 10, a contact hole 14 is formed in the dielectric film 9 by a dry etcher or the like.

  Next, as shown in FIG. 1, a conductive film is formed by a vapor deposition method or a sputtering method, and patterned by a lift-off method, thereby forming a lower electrode 10 and an upper electrode 11 drawn to the upper surface side of the substrate. The MIM capacitor according to the present embodiment is manufactured through the above steps.

  As described above, in this embodiment, the dielectric film 7 and the conductive film 8 formed on the inner wall of the digging structure 6 and the surrounding conductive films 2 and 4 constitute an MIM capacitor. Thus, the surface area of the MIM capacitor is increased by effectively using the area of the inner wall of the digging structure 6. Thereby, the area occupied by the MIM capacitor in the semiconductor device can be reduced.

  The dielectric film 7 and the conductive film 8 are also formed on the conductive film 4. These conductive film 4, dielectric film 7 and conductive film 8 constitute an MIM capacitor. In this way, the surface area of the MIM capacitor is further expanded by using the region other than the digging structure 6.

  In addition, since the opening 5 connected to the digging structure 6 is narrow, a general thin film cannot be formed on the inner wall of the digging structure 6 by a general sputtering method, CVD method, or vapor deposition method. In particular, the thickness of the conductive film 4 is fatal because it directly affects the MIM capacitance value. Therefore, the dielectric film 7 and the conductive film 8 can be formed on the inner wall of the digging structure 6 by using the ALD method which is a film forming method with extremely good coverage.

Embodiment 2. FIG.
FIG. 11 is a cross-sectional view showing an MIM capacitor according to Embodiment 2 of the present invention. In addition to the configuration of the first embodiment, a conductive film 8, a dielectric film 9, and a lower electrode 10 are stacked above the conductive film 4. These layers constitute an MIM capacitor. Thereby, the surface area of the MIM capacitor is further expanded as compared with the first embodiment.

Embodiment 3 FIG.
FIG. 12 is a sectional view showing an MIM capacitor according to the third embodiment of the present invention. Although the semi-insulating substrate 1 is used in the first and second embodiments, the semiconductor substrate 15 is used in the present embodiment. An insulating film 16 is formed between the semiconductor substrate 15 and the conductive film 2 by CVD or sputtering. Since the insulating film 16 increases the insulation from the semiconductor substrate 15, leakage current through the substrate can be suppressed.

Embodiment 4 FIG.
FIG. 13 is a cross-sectional view showing an MIM capacitor according to Embodiment 4 of the present invention. In the present embodiment, two digging structures 6 are formed. Other configurations are the same as those of the first embodiment. Not only this but the digging structure 6 should just be formed in multiple numbers in the structure of Embodiment 1-3. Thereby, since the amount of side etching of each digging structure 6 can be reduced, the influence of the deflection of the conductive film 8 on the ceiling side of the digging structure 6 can be reduced.

Embodiment 5. FIG.
FIG. 14 is a cross-sectional view showing an MIM capacitor according to the fifth embodiment of the present invention. A digging structure 18 is formed in the semi-insulating substrate 17. The digging structure 18 has an opening on the upper surface of the semi-insulating substrate 17, and the width inside the semi-insulating substrate 17 is wider than the opening. A conductive film 19, a dielectric film 20 and a conductive film 21 are sequentially formed on the inner wall of the digging structure 18.

  The conductive film 19, the dielectric film 20, and the conductive film 21 are also formed on the upper surface of the semi-insulating substrate 17. An insulating film 22 is formed on the upper surface of the semiconductor substrate 15 so as to cover them. An upper electrode 23 is formed on the insulating film 22 and penetrates the insulating film 22 and is connected to the conductive film 21. A lower electrode 24 is formed on the lower surface of the semiconductor substrate 15. The digging structure 18 penetrates the semi-insulating substrate 17. The conductive film 19 is connected to the lower electrode 24.

  Next, a method for manufacturing the MIM capacitor according to the present embodiment will be described. 15 and 16 are cross-sectional views illustrating the method for manufacturing the MIM capacitor according to the fifth embodiment of the present invention.

  First, as shown in FIG. 15, the lower electrode 24 is formed on the lower surface of the semi-insulating substrate 17. Then, a resist 25 is applied on the upper surface of the semi-insulating substrate 17, and an opening 26 is formed in the resist 25 by photolithography or the like. Then, the semi-insulating substrate 17 is side-etched from the opening 26 of the resist 25 by dry etching or wet etching, and the digging structure is wider inside the semi-insulating substrate 17 than the opening on the upper surface of the semi-insulating substrate 17. 18 is formed. Chemical solutions for wet etching are tartaric acid: hydrogen peroxide mixture, phosphoric acid: hydrogen peroxide mixture, citric acid: hydrogen peroxide mixture, sulfuric acid: hydrogen peroxide mixture, hydrofluoric acid, and the like. For dry etching, RIE (Reactive Ion Etching), ICP-RIE (Inductive Coupled Plasma-RIE), or the like is used.

  Next, as illustrated in FIG. 16, a conductive film 19, a dielectric film 20, and a conductive film 21 are sequentially formed on the inner wall of the digging structure 18 by the ALD method. Thereafter, an insulating film 22 is formed on the upper surface of the semi-insulating substrate 17 by CVD or sputtering. An upper electrode 23 is formed on the insulating film 22. The MIM capacitor according to the present embodiment is manufactured through the above steps.

  Even when the digging structure 18 is formed in the semi-insulating substrate 17 as in the present embodiment, the area occupied by the MIM capacitor in the semiconductor device can be reduced as in the first embodiment.

  The conductive film 19, the dielectric film 20, and the conductive film 21 formed on the upper surface of the semi-insulating substrate 17 constitute an MIM capacitor. As described above, the surface area of the MIM capacitor is further expanded by using the region other than the digging structure 18.

  Further, since the lower electrode 24 is formed on the lower surface of the semiconductor substrate 15, heat dissipation is improved. Further, since the lower electrode 24 can be directly connected to the back surface ground, there is an advantage on the electric circuit that the inductor component is small.

  In the first to fifth embodiments, the materials of the semi-insulating substrates 1 and 17 and the semiconductor substrate 15 are silicon (Si), gallium arsenide (GaAs), indium phosphide (InP), gallium nitride (GaN), and silicon carbide. (SiC).

  The conductive films 2, 4, 8, 19, and 21, the lower electrodes 10 and 24, and the upper electrodes 11 and 23 are made of titanium (Ti), gold (Au), platinum (Pt), aluminum (Al), copper (Cu ), Molybdenum (Mo), tantalum (Ta), niobium (Nb), nickel (Ni), tungsten (W), ruthenium (Ru), cobalt (Co), etc., or a laminated structure thereof.

  The insulating films 3, 16, 22 and the dielectric films 7, 9, 20 are made of silicon nitride (SiN), silicon nitride oxide (SiON), silicon oxide (SiO), aluminum oxide (AlO), aluminum nitride (AlN), Tantalum oxide (TaO), zirconium oxide (ZrO), hafnium oxide (HfO), strontium titanate (STO), barium strontium titanate (BST), etc., or a laminated structure thereof.

1,17 semi-insulating substrate, 2, 4, 8, 19, 21 conductive film, 3, 16, 22 insulating film,
5, 26 opening, 6, 18 digging structure, 7, 9, 20 dielectric film, 10, 24 lower electrode, 11, 23 upper electrode, 15 semiconductor substrate, 25 resist

Claims (10)

A substrate,
A first conductive film formed on the substrate;
A first insulating film formed on the first conductive film;
A second conductive film formed on the first insulating film, connected to the first conductive film and having an opening;
A digging structure formed in the first insulating film, connected to the opening, and wider than the opening;
An MIM capacitor comprising: a first dielectric film and a third conductive film formed in order on an inner wall including a floor, a side wall, and a ceiling of the digging structure.   2. The MIM capacitor according to claim 1, wherein the first dielectric film and the third conductive film are also formed on the second conductive film. A third dielectric film formed on the third conductive film;
3. A fourth conductive film formed on the third dielectric film above the second conductive film and connected to the first and second conductive films, further comprising: a fourth conductive film connected to the first and second conductive films. The MIM capacitor described in 1. A second insulating film formed between the substrate and the first conductive film;
The MIM capacitor according to claim 1, wherein the substrate is a semiconductor substrate.   The MIM capacitor according to claim 1, wherein a plurality of the digging structures are formed. A semi-insulating substrate;
A digging structure formed in the semi-insulating substrate, having an opening on the upper surface of the semi-insulating substrate, and wider than the opening in the semi-insulating substrate;
A first conductive film formed on the inner wall of the digging structure;
An MIM capacitor comprising a dielectric film and a second conductive film formed in order on the first conductive film.   The MIM capacitor according to claim 6, wherein the first conductive film, the dielectric film, and the second conductive film are also formed on the upper surface of the semi-insulating substrate. A lower electrode formed on the lower surface of the semi-insulating substrate;
The digging structure penetrates the semi-insulating substrate;
The MIM capacitor according to claim 6, wherein the first conductive film is connected to the lower electrode. Forming a first conductive film on the substrate;
Forming an insulating film on the first conductive film;
Forming a second conductive film connected to the first conductive film on the insulating film, and forming an opening in the second conductive film;
Side-etching the insulating film from the opening to form a digging structure wider than the opening;
And a step of sequentially forming a dielectric film and a third conductive film on an inner wall including a floor, a side wall, and a ceiling of the digging structure by an atomic layer deposition method. Applying a resist to the upper surface of the semi-insulating substrate and forming an opening in the resist;
Side-etching the semi-insulating substrate from the opening of the resist to form a digging structure having a width wider than the opening of the upper surface of the semi-insulating substrate inside the semi-insulating substrate;
And a step of sequentially forming a first conductive film, a dielectric film, and a second conductive film on the inner wall of the digging structure by an atomic layer deposition method.

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