CN108123040B - MIM capacitor and manufacturing method thereof - Google Patents
MIM capacitor and manufacturing method thereof Download PDFInfo
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- CN108123040B CN108123040B CN201711354002.0A CN201711354002A CN108123040B CN 108123040 B CN108123040 B CN 108123040B CN 201711354002 A CN201711354002 A CN 201711354002A CN 108123040 B CN108123040 B CN 108123040B
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L28/00—Passive two-terminal components without a potential-jump or surface barrier for integrated circuits; Details thereof; Multistep manufacturing processes therefor
- H01L28/40—Capacitors
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L28/00—Passive two-terminal components without a potential-jump or surface barrier for integrated circuits; Details thereof; Multistep manufacturing processes therefor
- H01L28/40—Capacitors
- H01L28/60—Electrodes
- H01L28/75—Electrodes comprising two or more layers, e.g. comprising a barrier layer and a metal layer
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L28/00—Passive two-terminal components without a potential-jump or surface barrier for integrated circuits; Details thereof; Multistep manufacturing processes therefor
- H01L28/40—Capacitors
- H01L28/60—Electrodes
- H01L28/82—Electrodes with an enlarged surface, e.g. formed by texturisation
- H01L28/86—Electrodes with an enlarged surface, e.g. formed by texturisation having horizontal extensions
- H01L28/87—Electrodes with an enlarged surface, e.g. formed by texturisation having horizontal extensions made by depositing layers, e.g. by depositing alternating conductive and insulating layers
Abstract
An MIM capacitor comprises a substrate, an insulating layer and a conductive material layer sequentially formed on the substrate, a first electrode, a first dielectric, a second electrode and an isolation layer sequentially formed on the conductive material layer, a third electrode formed on the isolation layer, a connecting element penetrating through the isolation layer and electrically connecting the second electrode and the third electrode, an opening penetrating through the third electrode and the isolation layer, the second dielectric arranged on the third electrode and on the second electrode at the opening, a fourth electrode formed on the second dielectric, a passivation layer formed on the conductive material layer and the fourth electrode, a first contact hole penetrating through the passivation layer and corresponding to the conductive material layer, a second contact hole penetrating through the passivation layer and corresponding to the fourth electrode, a first lead structure electrically connected with the conductive material layer through the first contact hole, a third contact hole formed on the passivation layer and corresponding to the third electrode or the second electrode, a first lead structure formed on the passivation layer and corresponding to the third electrode or, And a second lead structure electrically connected with the third electrode or the second electrode through the third contact hole.
Description
[ technical field ] A method for producing a semiconductor device
The invention relates to the technical field of capacitors, in particular to an MIM capacitor and a manufacturing method thereof
[ background of the invention ]
In very large scale integrated circuits, capacitors are one of the commonly used passive devices, which are usually integrated into active devices such as bipolar transistors or complementary metal oxide semiconductor transistors. The present technology for manufacturing a Capacitor can be divided into two technologies, i.e., a technology using polysilicon as an electrode and a technology using Metal as an electrode, wherein the polysilicon as the electrode has a carrier shortage problem, so that when the voltage at two ends of the Capacitor changes, the capacitance changes accordingly, and thus the Capacitor using polysilicon as the electrode cannot maintain the linear requirement of the present logic circuit, but the Capacitor using Metal as the electrode has no such problem, and the Capacitor is generally called a Metal-Insulator-Metal Capacitor (MIM) Capacitor.
The conventional MIM capacitor generally includes a lower electrode structure, an upper electrode structure, and a dielectric material formed between the lower electrode structure and the upper electrode structure, however, how to increase the density of the MIM capacitor is an important issue in the industry.
[ summary of the invention ]
One of the objectives of the present invention is to provide a high-density MIM capacitor and a method for fabricating the same.
An MIM capacitor comprising a substrate, an insulating layer formed on the substrate, a conductive material layer formed on the insulating layer, a first electrode formed on the conductive material layer, a first dielectric layer formed on the first electrode, a second electrode formed on the first dielectric layer, an isolation layer formed on the second electrode, a third electrode formed on the isolation layer, a connecting element penetrating the isolation layer to electrically connect the second electrode with the third electrode, an opening penetrating the third electrode with the isolation layer, a second dielectric layer disposed on the third electrode and on the second electrode at the opening, a fourth electrode formed on the second dielectric layer, a passivation layer formed on the conductive material layer and the fourth electrode, a first contact hole penetrating the passivation layer and corresponding to the conductive material layer, a first conductive material layer formed on the first contact hole, a second conductive material layer formed on the second contact hole, and a second conductive material layer formed on the second contact hole, The second contact hole penetrates through the passivation layer and corresponds to the fourth electrode, the first lead structure is electrically connected with the conductive material layer through the first contact hole, the third contact hole is formed in the passivation layer and corresponds to the third electrode or the second electrode, and the second lead structure is electrically connected with the third electrode or the second electrode through the third contact hole.
In one embodiment, the third contact hole includes a first portion extending from a surface of the passivation layer away from the conductive material layer toward the conductive material layer, and a second portion having one end connected to the first portion and the other end extending in a direction parallel to the conductive material layer and connected to one end of the third electrode or the second electrode.
In one embodiment, the second portion is connected to one end of the third electrode, and the second lead structure is connected to one end of the third electrode via the third contact hole.
In one embodiment, the connecting element is a tungsten plug.
In one embodiment, the opening divides the isolation layer and the third electrode into at least two independent portions, and the number of the connecting elements corresponding to each portion of the isolation layer and the third electrode is at least two.
In one embodiment, the material of the isolation layer is a borophosphosilicate glass material or a phosphosilicate glass material.
in one embodiment, the spacer layer has a thickness in a range between 3500 angstroms and 5000 angstroms.
In one embodiment, the first electrode, the second electrode, the third electrode and the fourth electrode each include two layers of titanium nitride and a tungsten buffer layer sandwiched between the two layers of titanium nitride, and the isolation layer is formed on the upper layer of titanium nitride of the second electrode.
A manufacturing method of an MIM capacitor comprises the following steps:
Providing a substrate, sequentially forming an insulating layer and a conductive material layer on the substrate, and sequentially forming a first electrode, a first dielectric layer and a second electrode on the conductive material layer;
Forming an isolation layer on the second electrode;
Forming a third electrode on the isolation layer;
Forming an opening penetrating through the third electrode and the isolation layer;
Forming a second dielectric layer and a fourth electrode on the third electrode and the second electrode at the opening in sequence;
forming a connection element that electrically connects the second electrode and the third electrode through the isolation layer;
a passivation layer formed on the conductive material layer and the fourth electrode;
forming a first contact hole penetrating the passivation layer and corresponding to the conductive material layer, forming a second contact hole penetrating the passivation layer and corresponding to the fourth electrode, and forming a third contact hole in the passivation layer corresponding to the third electrode or the second electrode;
Forming a first lead structure electrically connected to the conductive material layer through the first contact hole, and forming a second lead structure electrically connected to the third electrode or the second electrode through the third contact hole.
In one embodiment, the isolation layer is a borophosphosilicate glass material layer or a phosphosilicate glass material layer formed on the second electrode by APCVD.
Compared with the prior art, in the MIM capacitor and the manufacturing method thereof, the upper electrode structure and the lower electrode structure respectively comprise at least two layers of electrodes, and the dielectric layers between the upper electrode structure and the lower electrode structure comprise the first dielectric layer and the second dielectric layer on two sides, so that the density of the MIM capacitor is effectively increased. Furthermore, by means of the arrangement of the isolation layer, parasitic capacitance between some electrodes can be prevented, and the situation that the first dielectric layer or the second dielectric layer is easy to crack, leak electricity and the like due to overlarge stress of the titanium nitride material of the second electrode and the third electrode can be prevented, so that the reliability of the MIM capacitor is improved.
[ description of the drawings ]
In order to more clearly illustrate the technical solutions in the embodiments of the present invention, the drawings used in the description of the embodiments will be briefly introduced below, and it is apparent that the drawings in the following description are only some embodiments of the present invention, and it is obvious for those skilled in the art that other drawings can be obtained based on these drawings without inventive efforts.
Fig. 1 is a schematic cross-sectional view of a MIM capacitor according to a preferred embodiment of the present invention.
Fig. 2 is a schematic plan view of a portion of the MIM capacitor shown in fig. 1.
Fig. 3 to 8 are schematic structural diagrams of steps of the method for manufacturing the MIM capacitor shown in fig. 1.
[ detailed description ] embodiments
the technical solutions in the embodiments of the present invention will be clearly and completely described below, and it is obvious that the described embodiments are only a part of the embodiments of the present invention, and not all embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.
Referring to fig. 1, fig. 1 is a schematic cross-sectional view of an MIM capacitor according to a preferred embodiment of the present invention. The MIM capacitor includes a substrate, an insulating layer formed on the substrate, a conductive material layer formed on the insulating layer, a first electrode formed on the conductive material layer, a first dielectric layer formed on the first electrode, a second electrode formed on the first dielectric layer, an isolation layer formed on the second electrode, a third electrode formed on the isolation layer, a connecting element penetrating the isolation layer to electrically connect the second electrode and the third electrode, an opening penetrating the third electrode and the isolation layer, a second dielectric layer disposed on the third electrode and on the second electrode at the opening, a fourth electrode formed on the second dielectric layer, a passivation layer formed on the conductive material layer and the fourth electrode, a first contact hole penetrating the passivation layer and corresponding to the conductive material layer, a first conductive material layer formed on the first contact hole, a second conductive material layer formed on the second contact hole, and a second conductive material layer formed on the second contact hole, The second contact hole penetrates through the passivation layer and corresponds to the fourth electrode, the first lead structure is electrically connected with the conductive material layer through the first contact hole, the third contact hole is formed in the passivation layer and corresponds to the third electrode or the second electrode, and the second lead structure is electrically connected with the third electrode or the second electrode through the third contact hole.
In this embodiment, the third contact hole includes a first portion and a second portion, the first portion extends from a surface of the passivation layer away from the conductive material layer toward the conductive material layer, one end of the second portion is connected to the first portion, and the other end of the second portion extends in a direction parallel to the conductive material layer and is connected to one end of the third electrode or the second electrode. In the embodiment shown in fig. 1, the second portion is connected to one end of the third electrode, and the second lead structure is connected to one end of the third electrode via the third contact hole.
Further, the connecting element is a tungsten plug (i.e., a W plug). Referring to fig. 2, fig. 2 is a schematic plan view of the third electrode, the isolation layer, the second electrode and the connecting element. The opening divides the isolation layer and the third electrode into at least two mutually independent parts, and the number of the connecting elements corresponding to each part of the isolation layer and the third electrode is at least two. In this embodiment, the number of the openings is two, the openings are in the shape of a strip, the two openings divide the isolation layer and the third electrode into three portions, and each portion of the isolation layer and the third electrode may correspond to two connecting elements.
Further, the isolation layer is made of boron-phosphorus-silicon-glass (BPSG) material or phosphorus-silicon-glass (PSG) material. The thickness of the spacer layer is in a range between 3500 angstroms and 5000 angstroms.
it will be appreciated that the layer of conductive material may be a layer of metallic aluminium. The first electrode, the second electrode, the third electrode and the fourth electrode all comprise two layers of titanium nitride and a tungsten buffer layer sandwiched between the two layers of titanium nitride, wherein the isolation layer is formed on the upper layer of titanium nitride layer of the second electrode. The two titanium nitride layers can be respectively used for isolating adjacent dielectrics (such as the first dielectric layer or the second dielectric layer) and surface electrodes adjacent to the lead structure or the conductive material layer, the thickness of the titanium nitride layer for isolating can be in the range of 100-500 angstroms, the thickness of the titanium nitride layer for surface electrodes can be in the range of 50-200 angstroms, and the material of the tungsten buffer layer can be in the range of 800-1200 angstroms.
wherein the conductive material layer, the first electrode, the first lead structure and the fourth electrode are electrically connected and jointly constitute a first electrode structure of the MIM capacitor, and the second electrode, the connecting element, the third electrode and the second lead structure are electrically connected and jointly constitute a second electrode structure of the MIM capacitor. The first dielectric layer and the second dielectric layer are insulating dielectrics between the two electrode structures. The materials of the first dielectric layer and the second dielectric layer may include, but are not limited to, alumina Al2O3, oxidized clam HfO2, or zirconia ZrO 2. The thickness of the first dielectric layer and the second dielectric layer can be about 100 angstroms.
Referring to fig. 3 to 8, fig. 3 to 8 are schematic structural diagrams illustrating a portion of steps of the method for fabricating the MIM capacitor shown in fig. 1. The manufacturing method includes the following steps S1-S9.
in step S1, referring to fig. 3, a substrate is provided, an insulating layer and a conductive material layer are sequentially formed on the substrate, and a first electrode, a first dielectric layer and a second electrode are sequentially formed on the conductive material layer. It is understood that the first electrode, the first dielectric layer and the second electrode can be deposited by CVD, and formed into the structure shown in fig. 1 by photolithography and etching.
In step S2, referring to fig. 4, an isolation layer is formed on the second electrode. Specifically, the isolation layer may be a borophosphosilicate glass material layer or a phosphosilicate glass material layer formed on the second electrode by an APCVD method.
In step S3, referring to fig. 5, a third electrode is formed on the isolation layer.
Step S4, please refer to fig. 6 and 7, in which fig. 6 is a cross-sectional view, and fig. 7 is a plan view, the third electrode and the isolation layer are etched and etched to form an opening penetrating through the isolation layer and the third electrode. The openings may have a bar shape, and the number of the openings may be two, thereby dividing the third electrode and the isolation layer into three portions.
in step S5, referring to fig. 8, a second dielectric layer and the fourth electrode are sequentially formed on the third electrode and the second electrode at the opening. It is understood that the isolation layer, the third electrode, the second dielectric layer and the fourth electrode may be deposited by CVD, and formed into the structure shown in fig. 1 by photolithography and etching.
In step S6, please refer to fig. 1, a passivation layer is formed on the conductive material layer and the fourth electrode. The passivation layer may be made of silicon oxide and may be formed by PECVD.
in step S7, please refer to fig. 1 and fig. 2, a connecting element penetrating the isolation layer to electrically connect the second electrode and the third electrode is formed. It is understood that the step S5 may be located between the steps S2 and S3.
In step S8, referring to fig. 1, a first contact hole penetrating the passivation layer and corresponding to the conductive material layer, a second contact hole penetrating the passivation layer and corresponding to the fourth electrode, and a third contact hole corresponding to the third electrode or the second electrode are formed in the passivation layer. The first, second and third contact holes may be formed by photolithography and etching.
In step S9, referring to fig. 1, a first lead structure electrically connected to the conductive material layer through the first contact hole and a second lead structure electrically connected to the third electrode or the second electrode through the third contact hole are formed. The first lead structure and the second lead structure can also be formed in a photoetching and etching mode and formed in the same etching process.
It is understood that the structure, material and thickness of each element or film layer of the MIM capacitor involved in the fabrication method have been described in the description of the structure of the MIM capacitor, and thus are not described herein again.
Compared with the prior art, in the MIM capacitor and the manufacturing method thereof, the upper electrode structure and the lower electrode structure respectively comprise at least two layers of electrodes, and the dielectric layers between the upper electrode structure and the lower electrode structure comprise the first dielectric layer and the second dielectric layer on two sides, so that the density of the MIM capacitor is effectively increased. Furthermore, by means of the arrangement of the isolation layer, parasitic capacitance between some electrodes can be prevented, and the situation that the first dielectric layer or the second dielectric layer is easy to crack, leak electricity and the like due to overlarge stress of the titanium nitride material of the second electrode and the third electrode can be prevented, so that the reliability of the MIM capacitor is improved.
While the foregoing is directed to embodiments of the present invention, it will be understood by those skilled in the art that various changes may be made without departing from the spirit and scope of the invention.
Claims (10)
1. A MIM capacitor, wherein: the MIM capacitor includes a substrate, an insulating layer formed on the substrate, a conductive material layer formed on the insulating layer, a first electrode formed on the conductive material layer, a first dielectric layer formed on the first electrode, a second electrode formed on the first dielectric layer, an isolation layer formed on the second electrode, a third electrode formed on the isolation layer, a connecting element penetrating the isolation layer to electrically connect the second electrode and the third electrode, an opening penetrating the third electrode and the isolation layer, a second dielectric layer disposed on the third electrode and on the second electrode at the opening, a fourth electrode formed on the second dielectric layer, a passivation layer formed on the conductive material layer and the fourth electrode, a first contact hole penetrating the passivation layer and corresponding to the conductive material layer, a first conductive material layer formed on the first contact hole, a second conductive material layer formed on the second contact hole, and a second conductive material layer formed on the second contact hole, The second contact hole penetrates through the passivation layer and corresponds to the fourth electrode, the first lead structure is electrically connected with the conductive material layer through the first contact hole, the third contact hole is formed in the passivation layer and corresponds to the third electrode or the second electrode, and the second lead structure is electrically connected with the third electrode or the second electrode through the third contact hole.
2. The MIM capacitor according to claim 1 wherein: the third contact hole includes a first portion extending from a surface of the passivation layer away from the conductive material layer toward the conductive material layer, and a second portion having one end connected to the first portion and the other end extending in a direction parallel to the conductive material layer and connected to one end of the third electrode or the second electrode.
3. The MIM capacitor according to claim 2 wherein: the second portion is connected to one end of the third electrode, and the second lead structure is connected to one end of the third electrode through the third contact hole.
4. the MIM capacitor according to claim 1 wherein: the connecting element is a tungsten plug.
5. The MIM capacitor according to claim 1 wherein: the opening divides the isolation layer and the third electrode into at least two mutually independent parts, and the number of the connecting elements corresponding to each part of the isolation layer and the third electrode is at least two.
6. the MIM capacitor according to claim 1 wherein: the isolating layer is made of boron-phosphorus-silicon glass material or phosphorus-silicon glass material.
7. The MIM capacitor according to claim 1 wherein: the thickness of the spacer layer is in a range between 3500 angstroms and 5000 angstroms.
8. The MIM capacitor according to claim 1 wherein: the first electrode, the second electrode, the third electrode and the fourth electrode respectively comprise two layers of titanium nitride and a tungsten buffer layer clamped between the two layers of titanium nitride, and the isolating layer is formed on the upper layer of titanium nitride layer of the second electrode.
9. A manufacturing method of an MIM capacitor is characterized in that: the manufacturing method comprises the following steps:
Providing a substrate, sequentially forming an insulating layer and a conductive material layer on the substrate, and sequentially forming a first electrode, a first dielectric layer and a second electrode on the conductive material layer;
Forming an isolation layer on the second electrode;
Forming a third electrode on the isolation layer;
Forming an opening penetrating through the third electrode and the isolation layer;
Forming a second dielectric layer and a fourth electrode on the third electrode and the second electrode at the opening in sequence;
Forming a connection element that electrically connects the second electrode and the third electrode through the isolation layer;
a passivation layer formed on the conductive material layer and the fourth electrode;
Forming a first contact hole penetrating the passivation layer and corresponding to the conductive material layer, forming a second contact hole penetrating the passivation layer and corresponding to the fourth electrode, and forming a third contact hole in the passivation layer corresponding to the third electrode or the second electrode;
forming a first lead structure electrically connected to the conductive material layer through the first contact hole, and forming a second lead structure electrically connected to the third electrode or the second electrode through the third contact hole.
10. the method of fabricating the MIM capacitor of claim 9 wherein: the isolating layer is a boron-phosphorus-silicon glass material layer or a phosphorus-silicon glass material layer formed on the second electrode in an APCVD (active chemical vapor deposition) mode.
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| CN201711354002.0A CN108123040B (en) | 2017-12-15 | 2017-12-15 | MIM capacitor and manufacturing method thereof |
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| CN201711354002.0A CN108123040B (en) | 2017-12-15 | 2017-12-15 | MIM capacitor and manufacturing method thereof |
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| CN108123040B true CN108123040B (en) | 2019-12-10 |
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| KR20100057389A (en) * | 2008-11-21 | 2010-05-31 | 삼성전자주식회사 | Method of fabricating semiconductor device having mim capacitor |
| CN102420256B (en) * | 2011-05-13 | 2013-10-09 | 上海华力微电子有限公司 | Structure for improving density of MIM (metal injection molding) capacitor and manufacturing technology thereof |
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