CN108123038B - MIM capacitor and manufacturing method thereof - Google Patents
MIM capacitor and manufacturing method thereof Download PDFInfo
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- CN108123038B CN108123038B CN201711352412.1A CN201711352412A CN108123038B CN 108123038 B CN108123038 B CN 108123038B CN 201711352412 A CN201711352412 A CN 201711352412A CN 108123038 B CN108123038 B CN 108123038B
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L28/00—Passive two-terminal components without a potential-jump or surface barrier for integrated circuits; Details thereof; Multistep manufacturing processes therefor
- H01L28/40—Capacitors
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L28/00—Passive two-terminal components without a potential-jump or surface barrier for integrated circuits; Details thereof; Multistep manufacturing processes therefor
- H01L28/40—Capacitors
- H01L28/60—Electrodes
Abstract
The invention provides an MIM capacitor and a manufacturing method thereof. The MIM capacitor comprises a substrate, an insulating layer formed on the substrate, a lower electrode structure formed on the insulating layer, an isolating layer formed on the lower electrode structure, an opening penetrating through the isolating layer, and a dielectric material formed above the lower electrode structure corresponding to the opening and extending to the upper part of the isolating layer, the semiconductor device comprises an upper electrode structure formed on the dielectric material, a passivation layer formed on the isolation layer and the upper electrode structure, a first contact hole penetrating through the passivation layer and the isolation layer and corresponding to the lower electrode structure, a second contact hole penetrating through the passivation layer and corresponding to the upper electrode structure, a first lead structure arranged on the passivation layer and electrically connected to the lower electrode structure through the first contact hole, and a second lead structure arranged on the passivation layer and electrically connected to the upper electrode structure through the second contact hole.
Description
[ technical field ] A method for producing a semiconductor device
The invention relates to the technical field of capacitors, in particular to an MIM capacitor and a manufacturing method thereof
[ background of the invention ]
In very large scale integrated circuits, capacitors are one of the commonly used passive devices, which are usually integrated into active devices such as bipolar transistors or complementary metal oxide semiconductor transistors. The present technology for manufacturing capacitors can be divided into two types, i.e., a polysilicon electrode and a Metal electrode, and the polysilicon electrode causes a carrier shortage problem, so that when the voltage at two ends of the Capacitor changes, the capacitance changes, and thus the Capacitor using the polysilicon electrode cannot maintain the linear requirement of the present logic circuit, while the Capacitor using the Metal electrode does not have the problem, and the Capacitor is generally called a Metal-Insulator-Metal Capacitor (MIM)
The conventional MIM capacitor generally includes a lower electrode structure, an upper electrode structure, and a dielectric material formed between the lower electrode structure and the upper electrode structure, however, in the conventional MIM capacitor manufacturing process, the dielectric material is often damaged to a certain extent when the upper electrode is etched, so that the MIM capacitor has some leakage or other reliability problems, which need to be improved.
[ summary of the invention ]
One of the objectives of the present invention is to provide an MIM capacitor and a method for fabricating the same.
A MIM capacitor includes a substrate, an insulating layer formed on the substrate, a lower electrode structure formed on the insulating layer, an isolation layer formed on the lower electrode structure, an opening through the isolation layer, a dielectric material formed over the lower electrode structure corresponding to the opening and extending over the isolation layer, the semiconductor device comprises an upper electrode structure formed on the dielectric material, a passivation layer formed on the isolation layer and the upper electrode structure, a first contact hole penetrating through the passivation layer and the isolation layer and corresponding to the lower electrode structure, a second contact hole penetrating through the passivation layer and corresponding to the upper electrode structure, a first lead structure arranged on the passivation layer and electrically connected to the lower electrode structure through the first contact hole, and a second lead structure arranged on the passivation layer and electrically connected to the upper electrode structure through the second contact hole.
In one embodiment, the dielectric material upper surface includes a first recess corresponding to the opening, the upper electrode structure is disposed on the dielectric material upper surface, the upper electrode structure upper surface includes a second recess corresponding to the first recess, and widths of the opening, the first recess, and the second recess decrease in sequence.
In one embodiment, the number of the second contact holes is two, and both ends of the second lead structure are connected to the upper electrode structure via the two second contact holes.
In one embodiment, the second recess is located between the first and second contact holes.
In one embodiment, the lower electrode structure includes a metal layer, a first titanium nitride layer, a tungsten buffer layer, and a second titanium nitride layer sequentially disposed on the insulating layer, and the upper electrode structure includes a second titanium nitride layer, a tungsten buffer layer, and a first titanium nitride layer sequentially disposed on the dielectric material.
In one embodiment, the thickness of the spacer layer is greater than 10 times the thickness of the dielectric material.
In one embodiment, the material of the isolation layer includes one, two or three of silicon oxide, silicon nitride and aluminum oxide, and the thickness of the isolation layer is in a range from 1500 angstroms to 2000 angstroms.
In one embodiment, the dielectric material covers a portion of the isolation layer adjacent to the opening, and the first contact hole penetrates through the passivation layer and the isolation layer and is located on one side of the dielectric material.
In one embodiment, the dielectric material completely covers the isolation layer, and the first contact hole penetrates through the passivation layer, the isolation layer, and the dielectric material corresponding to the lower electrode structure.
A manufacturing method of an MIM capacitor comprises the following steps:
providing a substrate, forming an insulating layer on the substrate, and forming a lower electrode structure on the insulating layer;
forming an isolation layer having an opening on the lower electrode structure;
sequentially forming a dielectric material and an upper electrode material on the lower electrode structure and the isolation layer at the opening;
photoetching and etching are carried out on the upper electrode material to form an upper electrode structure; and
forming a passivation layer on the isolation layer and the upper electrode structure, forming a first contact hole penetrating through the passivation layer and the isolation layer and corresponding to the lower electrode structure, a second contact hole penetrating through the passivation layer and corresponding to the upper electrode structure, forming a first lead structure located on the passivation layer and electrically connected to the lower electrode structure through the first contact hole, and a second lead structure located on the passivation layer and electrically connected to the upper electrode structure through the second contact hole.
Compared with the prior art, in the MIM capacitor and the manufacturing method thereof, the isolation layer is arranged, and the dielectric material layer and the upper electrode structure are sequentially formed at the opening and above the isolation layer, so that an effective capacitance area is formed at the opening, and the dielectric material in the effective capacitance area is not easily damaged when the upper electrode structure is etched, thereby improving the device reliability of the MIM capacitor.
[ description of the drawings ]
In order to more clearly illustrate the technical solutions in the embodiments of the present invention, the drawings used in the description of the embodiments will be briefly introduced below, it is obvious that the drawings in the following description are only some embodiments of the present invention, and other drawings can be obtained by those skilled in the art without inventive efforts, wherein:
fig. 1 is a schematic cross-sectional view of a MIM capacitor according to a preferred embodiment of the present invention.
Fig. 2 is a schematic cross-sectional structure diagram of a modified embodiment of the MIM capacitor shown in fig. 1.
Fig. 3 to 7 are schematic cross-sectional structures of steps of the manufacturing method of the MIM capacitor shown in fig. 1 and 2.
[ detailed description ] embodiments
The technical solutions in the embodiments of the present invention will be clearly and completely described below, and it is obvious that the described embodiments are only a part of the embodiments of the present invention, and not all embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.
Referring to fig. 1, fig. 1 is a schematic cross-sectional view of an MIM capacitor according to a preferred embodiment of the present invention. The MIM capacitor comprises a substrate, an insulating layer formed on the substrate, a lower electrode structure formed on the insulating layer, an isolating layer formed on the lower electrode structure, an opening penetrating through the isolating layer, and a dielectric material formed above the lower electrode structure corresponding to the opening and extending to the upper part of the isolating layer, the semiconductor device comprises an upper electrode structure formed on the dielectric material, a passivation layer formed on the isolation layer and the upper electrode structure, a first contact hole penetrating through the passivation layer and the isolation layer and corresponding to the lower electrode structure, a second contact hole penetrating through the passivation layer and corresponding to the upper electrode structure, a first lead structure arranged on the passivation layer and electrically connected to the lower electrode structure through the first contact hole, and a second lead structure arranged on the passivation layer and electrically connected to the upper electrode structure through the second contact hole.
In this embodiment, the width of the dielectric material is the same as the width of the upper electrode structure, that is, the dielectric material only covers the lower electrode structure at the opening and extends to the upper part of a portion of the isolation layer adjacent to the opening, the first contact hole penetrates through the passivation layer and the isolation layer and is located at one side of the dielectric material, and the dielectric material and the upper electrode structure can be formed in the same etching process.
However, in an alternative embodiment, referring to fig. 2, fig. 2 is a schematic cross-sectional view of an alternative embodiment of the MIM capacitor shown in fig. 1. The dielectric material covers the lower electrode structure at the opening and extends to the whole area of the upper surface of the isolation layer (i.e. completely covers the isolation layer), and the first contact hole needs to penetrate through the passivation layer, the dielectric material and the isolation layer so as to correspond to the lower electrode structure. In this modified embodiment, the dielectric material may be formed without etching, and only an etching process is used to form the upper electrode structure.
Further, in the two embodiments, the dielectric material upper surface includes a first concave portion corresponding to the opening, the upper electrode structure is disposed on the dielectric material upper surface, the upper electrode structure upper surface includes a second concave portion corresponding to the first concave portion, and widths of the opening, the first concave portion, and the second concave portion decrease in sequence. The number of the second contact holes is two, and two ends of the second lead structure are connected with the upper electrode structure through the two second contact holes. The second recess is located between the first and second contact holes. The lower electrode structure comprises a metal layer (such as a metal Al layer), a first titanium nitride layer TiN-1, a tungsten buffer layer W and a second titanium nitride layer TiN-2 which are sequentially arranged on the insulating layer, and the upper electrode structure comprises the second titanium nitride layer TiN-2, the tungsten buffer layer W and the first titanium nitride layer TiN-1 which are sequentially arranged on the dielectric material. The thickness of the isolation layer is greater than 10 times the thickness of the dielectric material. The material of the isolation layer comprises one, two or three of silicon oxide, silicon nitride and aluminum oxide, and the thickness of the isolation layer is in the range of 1500-2000 angstroms
Referring to fig. 3 to 7, fig. 3 to 7 are schematic cross-sectional views illustrating steps of the manufacturing method of the MIM capacitor shown in fig. 1 and 2. The manufacturing method includes the following steps S1-S4.
In step S1, referring to fig. 3, a substrate is provided, an insulating layer is formed on the substrate, and a lower electrode structure is formed on the insulating layer.
In step S2, referring to fig. 4, an isolation layer having an opening is formed on the lower electrode structure.
In step S3, referring to fig. 5, a dielectric material and an upper electrode material are sequentially formed on the lower electrode structure and the isolation layer at the opening. The dielectric material and the upper electrode material sequentially, uniformly and completely cover the opening and the isolation layer, so that a first concave part corresponding to the opening is formed on the upper surface of the dielectric material, and a second concave part corresponding to the first concave part is formed on the upper surface of the upper electrode material.
In step S4, referring to fig. 6 and 7, if the MIM capacitor shown in fig. 1 is to be formed, the step S4 is: photoetching and etching the upper electrode material and the dielectric material to form an upper electrode structure and a dielectric material positioned below the upper electrode structure; if the MIM capacitor shown in fig. 2 is to be formed, the step S4 is: and photoetching and etching the upper electrode material to form an upper electrode structure.
Step S5, referring to fig. 1 and 2, a passivation layer is formed on the isolation layer and the upper electrode structure, a first contact hole penetrating through the passivation layer and the isolation layer and corresponding to the lower electrode structure, a second contact hole penetrating through the passivation layer and corresponding to the upper electrode structure, a first lead structure formed on the passivation layer and electrically connected to the lower electrode structure through the first contact hole, and a second lead structure formed on the passivation layer and electrically connected to the upper electrode structure through the second contact hole are formed.
Specific structures, materials and parameters of the upper electrode structure, the lower electrode structure, the isolation layer, the dielectric material, the passivation layer, the first contact hole, the first lead structure, the second contact hole and the second lead structure are described in the above description of the structure of the MIM capacitor shown in fig. 1 and 2, and detailed descriptions thereof are omitted here.
Compared with the prior art, in the MIM capacitor and the manufacturing method thereof, the isolation layer is arranged, and the dielectric material layer and the upper electrode structure are sequentially formed at the opening and above the isolation layer, so that an effective capacitance area is formed at the opening, and the dielectric material in the effective capacitance area is not easily damaged when the upper electrode structure is etched, thereby improving the device reliability of the MIM capacitor.
While the foregoing is directed to embodiments of the present invention, it will be understood by those skilled in the art that various changes may be made without departing from the spirit and scope of the invention.
Claims (9)
1. A MIM capacitor, wherein: the MIM capacitor comprises a substrate, an insulating layer formed on the substrate, a lower electrode structure formed on the insulating layer, an isolating layer formed on the lower electrode structure, an opening penetrating through the isolating layer, and a dielectric material formed above the lower electrode structure corresponding to the opening and extending to the upper part of the isolating layer, an upper electrode structure formed on the dielectric material, a passivation layer formed on the isolation layer and the upper electrode structure, a first contact hole penetrating the passivation layer and the isolation layer and corresponding to the lower electrode structure, a second contact hole penetrating the passivation layer and corresponding to the upper electrode structure, a first lead structure disposed on the passivation layer and electrically connected to the lower electrode structure through the first contact hole, and a second lead structure disposed on the passivation layer and electrically connected to the upper electrode structure through the second contact hole;
the thickness of the isolation layer is more than 10 times of the thickness of the dielectric material;
the upper surface of the dielectric material comprises a first concave part corresponding to the opening, the upper electrode structure is arranged on the upper surface of the dielectric material, the upper surface of the upper electrode structure comprises a second concave part corresponding to the first concave part, and the widths of the opening, the first concave part and the second concave part are sequentially reduced;
the effective capacitance region of the MIM capacitor is located in a region corresponding to the opening.
2. The MIM capacitor according to claim 1 wherein: the number of the second contact holes is two, and two ends of the second lead structure are connected with the upper electrode structure through the two second contact holes.
3. The MIM capacitor according to claim 2 wherein: the second recess is located between the first and second contact holes.
4. The MIM capacitor according to claim 1 wherein: the lower electrode structure comprises a metal layer, a first titanium nitride layer, a tungsten buffer layer and a second titanium nitride layer which are sequentially arranged on the insulating layer, and the upper electrode structure comprises a second titanium nitride layer, a tungsten buffer layer and a first titanium nitride layer which are sequentially arranged on the dielectric material.
5. The MIM capacitor according to claim 1 wherein: the thickness of the isolation layer is greater than 10 times the thickness of the dielectric material.
6. The MIM capacitor according to claim 1 wherein: the material of the isolation layer comprises one, two or three of silicon oxide, silicon nitride and aluminum oxide, and the thickness of the isolation layer is in the range of 1500-2000 angstroms.
7. The MIM capacitor according to claim 1 wherein: the dielectric material covers the part of the isolation layer adjacent to the opening, and the first contact hole penetrates through the passivation layer and the isolation layer and is located on one side of the dielectric material.
8. The MIM capacitor according to claim 1 wherein: the medium material completely covers the isolation layer, and the first contact hole penetrates through the passivation layer, the isolation layer and the medium material corresponding to the lower electrode structure.
9. A method of fabricating a MIM capacitor according to any one of claims 1-8, wherein: the manufacturing method comprises the following steps:
providing a substrate, forming an insulating layer on the substrate, and forming a lower electrode structure on the insulating layer;
forming an isolation layer having an opening on the lower electrode structure;
sequentially forming a dielectric material and an upper electrode material on the lower electrode structure and the isolation layer at the opening;
photoetching and etching are carried out on the upper electrode material to form an upper electrode structure; and
forming a passivation layer on the isolation layer and the upper electrode structure, forming a first contact hole penetrating through the passivation layer and the isolation layer and corresponding to the lower electrode structure, a second contact hole penetrating through the passivation layer and corresponding to the upper electrode structure, forming a first lead structure located on the passivation layer and electrically connected to the lower electrode structure through the first contact hole, and a second lead structure located on the passivation layer and electrically connected to the upper electrode structure through the second contact hole.
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| CN201711352412.1A CN108123038B (en) | 2017-12-15 | 2017-12-15 | MIM capacitor and manufacturing method thereof |
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| CN201711352412.1A CN108123038B (en) | 2017-12-15 | 2017-12-15 | MIM capacitor and manufacturing method thereof |
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| CN108123038B true CN108123038B (en) | 2020-10-16 |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| CN105023933A (en) * | 2014-04-25 | 2015-11-04 | 台湾积体电路制造股份有限公司 | Leakage resistant RRAM/MIM structure |
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| US7205634B2 (en) * | 2004-03-10 | 2007-04-17 | Taiwan Semiconductor Manufacturing Co., Ltd. | MIM structure and fabrication process with improved capacitance reliability |
| US7375002B2 (en) * | 2005-06-28 | 2008-05-20 | Freescale Semiconductor, Inc. | MIM capacitor in a semiconductor device and method therefor |
| JP2008016464A (en) * | 2006-07-03 | 2008-01-24 | Matsushita Electric Ind Co Ltd | Semiconductor device and manufacturing method thereof |
| US8546235B2 (en) * | 2011-05-05 | 2013-10-01 | Taiwan Semiconductor Manufacturing Company, Ltd. | Integrated circuits including metal-insulator-metal capacitors and methods of forming the same |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| CN105023933A (en) * | 2014-04-25 | 2015-11-04 | 台湾积体电路制造股份有限公司 | Leakage resistant RRAM/MIM structure |
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Effective date of registration: 20200807 Address after: 210000 Kechuang building, Futian Road, Zhetang street, Lishui Economic Development Zone, Nanjing City, Jiangsu Province Applicant after: Nanjing Lishui hi tech Venture Capital Management Co.,Ltd. Address before: 518000 Guangdong city of Shenzhen province Baoan District Fuyong Street Peace community Junfeng Industrial Zone A3 building the first floor Applicant before: SHENZHEN JINGTE SMART MANUFACTURING TECHNOLOGY Co.,Ltd. |
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Effective date of registration: 20210121 Address after: No. 8, Zhongxing West Road, economic development zone, Lishui District, Nanjing City, Jiangsu Province, 211200 Patentee after: Jiangsu Meihe Power Technology Co.,Ltd. Address before: 210000 Kechuang building, Futian Road, Zhetang street, Lishui Economic Development Zone, Nanjing, Jiangsu Province Patentee before: Nanjing Lishui hi tech Venture Capital Management Co.,Ltd. |