JPH06302780A - Ic memory and manufacture thereof - Google Patents

Abstract

PURPOSE:To provide an IC memory capable of increasing the integration degree of capacitor cells without increasing the possibility of generating soft errors especially due to alpha rays in the IC memory. CONSTITUTION:Within the IC memory comprising capacitor cells 22 charging and discharging any load through the intermediary of a FET 21, the dielectric film 22c of the capacitor cells 22 are to be formed taking an elliptic shell shape.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an IC memory, and more particularly to an IC memory capable of increasing the degree of integration of capacitor cells without increasing the risk of soft error due to α rays.

[0002]

2. Description of the Related Art Next, a conventional IC memory having a trench structure in a capacitor cell will be described with reference to FIG.
FIG. 4 is a schematic side sectional view of a main part of a conventional IC memory.

In FIG. 4, 10 is a silicon substrate, 10a is a trench, 11 is a FET including a gate insulating film 11a, a gate electrode 11b and impurity diffusion layers 11c and 11d, 12 is a first electrode 12a and a second electrode. A capacitor cell composed of an electrode 12b and a dielectric film 12c.

As shown in FIG. 4, in a capacitor cell 11 of a conventional IC memory, a predetermined region of a silicon substrate 10 is anisotropically etched to form a deep well-shaped trench 10a, and an inner surface of the trench 10a is formed. The dielectric film 12c was formed by depositing silicon oxide or the like.

[0005]

The capacitor cell 12 having the three-dimensional structure as described above is more preferable than a capacitor cell (not shown) having a planar structure in which electrodes are opposed to each other through a planar dielectric film. Since it can be formed with a large capacity, many I
Used in C memory.

However, even in such an IC memory, it is indispensable to reduce the area of the capacitor cell 12 in plan view in order to increase the degree of integration, and a reduction in the amount of charge that can be stored in the IC memory cannot be avoided. As a result, the risk of soft error due to α rays increases.

The present invention has been made to solve such a problem, and its purpose is to increase the integration degree of capacitor cells without increasing the risk of soft error due to α rays. It is to provide IC memory.

[0008]

As shown in FIG. 1, the above-mentioned object is to provide an IC memory including an FET 21 and a capacitor cell 22 which charges and discharges electric charge through the FET 21. This is achieved by an IC memory characterized in that the dielectric film 22c of 22 is formed in an elliptical shell shape.

[0009]

The function of the capacitor cell 22 of the IC memory of the present invention is
The dielectric film 22c is formed in an elliptical shell shape. Therefore, since the area of the dielectric film 22c is larger than the area of the dielectric film 12c of the capacitor cell 12 of the conventional IC memory described with reference to FIG. 4, more electric charges can be accumulated and the risk of soft error is increased. Sex decreases.

[0010]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS A method of manufacturing an IC memory according to an embodiment of the present invention will be described below with reference to FIGS.

First, the surface side of the silicon substrate 20 is exposed to plasma generated in a plasma etching apparatus (not shown), and an opening formed in the silicon oxide film 20a on the surface is exposed.
The silicon substrate 20 is isotropically etched from 20b to form an ellipsoidal cavity A therein (see FIG. 2 (a)).

Next, the silicon substrate 20 (silicon oxide film
20a), and the inner surface of the cavity A, the source 21 of the FET 21
c and drain 21d and first electrode of capacitor cell 22
The first polysilicon layer 20c to be 22a is formed by a normal vapor phase growth method, and the first polysilicon layer 20c is formed.
Thickly deposit silicon oxide 20d on the surface of 20c (Fig. 2
(See (b) and (c)).

Thereafter, the silicon oxide film on the silicon substrate 20 is formed.
The silicon oxide 20d is etched back to the extent that it slightly remains on the surface 20a to form a silicon oxide film 20d 'which will be the gate insulating film 21a (see FIG. 1) of the FET 21 (see FIG. 2D).

It is needless to say that the silicon oxide 20d in the cavity A remains as it is even after the etching back. Then, a second polysilicon layer 20e to be the gate electrode 21b of the FET 21 is deposited on the surface side of the silicon substrate 20 on which the silicon oxide film 20d 'is formed by a normal vapor deposition method, and then the second polysilicon layer 20e is deposited. A resist pattern 31a is formed on the region of the layer 20e which will be the gate electrode 21b (see FIG. 2 (f)).

Next, after the region exposed from the resist pattern 31a of the second polysilicon layer 20e is etched to form the gate electrode 21b, the resist pattern 31a is peeled from the silicon substrate 20 (see FIG. 3 (a)). ).

After that, a resist pattern (not shown) is formed on the surface of the silicon substrate 20, and impurities are injected into both sides of the gate electrode 21b to form impurity diffusion layers 21c and 21d to be the source and drain of the FET 21. (See Fig. 3 (b))
.

After peeling off the resist pattern,
Another resist pattern (not shown) is formed on the surface of the silicon substrate 20, and the silicon oxide 20d in the cavity A is removed by etching to expose the surface of the first polysilicon layer 20c.
(See Figure 3 (b)).

Next, the dielectric film 22 of the capacitor cell 22.
After the interlayer insulating film 20f to be c is formed on the surface side of the recon substrate 20, the capacitor cell 21 is formed on the interlayer insulating film 20f.
A third polysilicon layer 20g to be the second electrode 22b is formed by vapor phase epitaxy (see FIG. 3 (d)).

Then, after forming a resist pattern 31b (see FIG. 3 (e)) on the surface side of the silicon substrate 20, the FET is formed.
The dielectric film 22 of the capacitor cell 22 is formed by etching the third polysilicon layer 20g in the region corresponding to 21.
An IC memory according to an embodiment of the present invention in which the shape of c is an elliptical shell is completed.

The dielectric film 22c of the capacitor cell 22 of the IC memory thus constructed has a larger area than the dielectric film 12c of the capacitor cell 12 of the conventional IC memory. Therefore, in the IC memory of one embodiment of the present invention configured as described above, it is possible to increase the degree of integration of the capacitor cell without increasing the risk of soft error due to α rays.

[0021]

As described above, the present invention makes it possible to provide an IC memory in which the degree of integration of capacitor cells can be increased without increasing the risk of soft error due to α rays.

[Brief description of drawings]

FIG. 1 is a schematic side sectional view of an essential part of an IC memory according to an embodiment of the present invention.

FIG. 2 is a side sectional view of an essential part of a manufacturing process of an IC memory according to an embodiment of the present invention.

FIG. 3 is a side sectional view of a main part of a manufacturing process of an IC memory according to an embodiment of the present invention.

FIG. 4 is a schematic side sectional view of a main part of a conventional IC memory.

[Explanation of symbols]

 10, silicon substrate 10a, trench 11, FET 11a, gate insulating film 11b, gate electrodes 11c and 11d, impurity diffusion layer 12, capacitor cell 12a, first electrode 12b, second electrode The electrode 12c, the dielectric film 20, the silicon substrate 20a, the silicon oxide film 20b, the opening 20c, the first polysilicon layers 20d and 20d ', the silicon oxide film 20e, and the second polysilicon film. The layer 20f is the interlayer insulating film 20g, the third polysilicon layer 21, the FET 21a, the gate insulating film 21b, the gate electrode 21c, the source 21d, the drain 22, the capacitor cell 22a is the first layer. The electrode 22b of the second electrode 22c is the dielectric film

Claims (2)

[Claims] 1. An IC memory comprising an FET (21) and a capacitor cell (22) which charges and discharges electric charge through the FET (21), wherein a dielectric film of the capacitor cell (22). An IC characterized in that (22c) is formed in an elliptical shell shape.
memory. 2. The opening (20b) provided in the insulating film (20a) on the substrate (20) is isotropically etched to form an ellipsoidal shape that extends from the opening (20b) into the substrate (20). The source (21c) and drain (21d) of the FET (21) according to claim 1, wherein the step of forming a cavity (A), the insulating film (20a) of the substrate (20) and the inner surface of the cavity (A). ) And the first electrode (22a) of the capacitor cell (22)
A step of forming a first conductive layer (20c) that becomes a substrate, a step of depositing an insulator (20d) on the surface side of the substrate (20) on which the first conductive layer (20c) is deposited, The insulating material (20d) is etched back to such an extent that it slightly remains on the insulating film (20a) of the substrate (20), and an insulating film (20d ') to be the gate insulating film (21a) of the FET (21) is formed. A step of forming the second conductive layer (2) to be the gate electrode (21b) of the FET (21) on the surface side of the substrate (20) on which the insulating film (20d ′) is formed.
0e) is deposited, a resist pattern (31a) is formed on a region of the second conductive layer (20e) to be the gate electrode (21b).
And a step of forming a resist pattern (31a) of the second conductive layer (20e)
Etching the exposed area from the second conductive layer (20e)
Of the non-etching region of the gate electrode (21b), and impurities are implanted into both sides of the gate electrode (21b) formed on the substrate (20) to form the source (21c) and the drain.
(21d), a step of etching away the insulator (20d) in the cavity (A) to expose the surface of the first conductive layer (20c), and the capacitor cell (22 After forming the interlayer insulating film (20f) to be the dielectric film (22c) on the surface side of the substrate (20),
The second capacitor cell (22) is formed on the interlayer insulation film (20f).
Forming a third conductive layer (20g) to be the electrode (22b) of the substrate, and forming a resist pattern (31b) on the surface side of the substrate (20), and then forming a region corresponding to the FET (21). The method of manufacturing a semiconductor device according to claim 1, further comprising the step of etching the third conductive layer (20 g).