JP2017059741A - Semiconductor device, method of manufacturing the same, and power conversion device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To suppress a reverse leakage current in a semiconductor device having a Schottky junction interface.SOLUTION: A semiconductor 100 includes; a semiconductor layer 120; an insulating film 130 which is formed on the semiconductor layer 120 and has an opening 138; and an anode electrode 140 which is formed over the insulating film 130 from the inside of the opening 138 and forms a Schottky junction interface together with the semiconductor layer through the inside of the opening 138. The semiconductor layer 120 includes: a first region 120a for forming Schottky junction interface SB together with the anode electrode 140; and a second region 120b formed on the outer side than the Schottky junction interface SB, sandwiching the insulating film 130 between the electrode 140 and having higher electric resistance than that in the first region 120a.SELECTED DRAWING: Figure 1

Description

  The present invention relates to a semiconductor device, a manufacturing method thereof, and a power conversion device.

  As one of semiconductor devices (semiconductor devices, semiconductor elements), a Schottky Barrier Diode (SBD) is known. In a Schottky barrier diode, when a reverse voltage is applied, the reverse leakage current increases due to the concentration of the electric field at the end of the Schottky junction interface.

  In Patent Document 1, in order to suppress electric field concentration at the end of the Schottky junction interface, in a silicon carbide (SiC) Schottky barrier diode, other semiconductor layers adjacent to the end of the Schottky junction interface are provided. It is disclosed that a region having a conductive property different from that of the first region is formed by ion implantation.

  In Patent Documents 2 and 3, in order to suppress electric field concentration at the end of the Schottky junction interface, in a gallium nitride (GaN) Schottky barrier diode, a semiconductor layer adjacent to the end of the Schottky junction interface is provided. It is disclosed that a high resistance region having a relatively higher electric resistance than other regions is formed by ion implantation.

Japanese Patent No. 5306392 Japanese Patent No. 2015-76577 Japanese Patent No. 2013-42183

  In the technique of Patent Document 1, since it is difficult to form a p-type semiconductor region by ion implantation in a gallium nitride (GaN) n-type semiconductor layer, it is applied to a gallium nitride (GaN) Schottky barrier diode. Can not. Further, according to the inventors of the present invention, it has been found that, in the techniques of Patent Documents 2 and 3, the reverse leakage current is increased instead of the reverse leakage current being suppressed. The cause is considered to be that reverse leakage current easily flows through the high resistance region adjacent to the Schottky junction interface.

  The present invention solves at least a part of the problems described above and can be realized as the following forms.

(1) One embodiment of the present invention provides a semiconductor device. The semiconductor device includes: a semiconductor layer; an insulating film formed on the semiconductor layer and having an opening; and formed from the inside of the opening to the insulating film, and through the inside of the opening And an electrode that forms a Schottky junction interface, and the semiconductor layer is formed on the electrode and a first region that forms the Schottky junction interface; And a second region having an electric resistance higher than that of the first region with the insulating film interposed therebetween. According to this embodiment, reverse leakage current through the second region can be prevented, and electric field concentration at the end of the Schottky junction interface can be suppressed by the second region. As a result, the reverse leakage current can be effectively suppressed.

(2) In the above-described semiconductor device, the second region has an interface between the end portion of the Schottky junction interface and the end portion of the electrode in the plane direction in which the semiconductor layer extends. May be present on the side. According to this embodiment, electric field concentration at the end of the Schottky junction interface can be effectively suppressed.

(3) In the semiconductor device described above, the second region may be separated from the end portion of the Schottky junction interface by 0.5 μm or more in a plane direction in which the semiconductor layer extends. According to this form, the reverse leakage current through the second region can be sufficiently prevented.

(4) In the semiconductor device described above, the second region may exist within 5.0 μm from an end of the Schottky junction interface in a plane direction in which the semiconductor layer extends. According to this embodiment, electric field concentration at the end of the Schottky junction interface can be effectively suppressed.

(5) In the semiconductor device described above, the second region may exist within 1.0 μm from an end of the Schottky junction interface in a plane direction in which the semiconductor layer extends. According to this embodiment, electric field concentration at the end of the Schottky junction interface can be further suppressed.

(6) In the above semiconductor device, the semiconductor layer has a plateau-like mesa structure having an upper surface and side surfaces, the Schottky junction interface is formed on the upper surface, and the second region is It may be formed on at least the side surface. According to this embodiment, the electric field concentration at the end of the Schottky junction interface can be further suppressed by the mesa structure.

(7) In the semiconductor device described above, the semiconductor layer may be mainly made of gallium nitride (GaN). According to this embodiment, reverse leakage current can be effectively suppressed in a gallium nitride (GaN) based semiconductor device.

(8) In the above semiconductor device, the second region includes boron (B), neon (Ne), argon (Ar), zinc (Zn), carbon (C), iron (Fe), and nitrogen (N). In addition, at least one of fluorine (F) and magnesium (Mg) may be contained in the range of 1 × 10 ¹⁵ cm ^{−3 to} 1 × 10 ²² cm ⁻³ . According to this form, the second region can be easily realized.

(9) In the semiconductor device described above, the electrode may include a metal layer mainly composed of at least one of nickel (Ni), palladium (Pd), platinum (Pt), and iridium (Ir). According to this embodiment, an electrode that forms a Schottky junction interface can be easily realized.

  One embodiment of the present invention provides a method for manufacturing a semiconductor device. The manufacturing method includes: an etching step of forming a mesa structure with a portion where the mask is formed as an upper surface by etching the periphery of the mask in a semiconductor layer where the mask is formed; and after the etching step is finished An ion implantation step of ion-implanting atoms to increase the electrical resistance of the semiconductor layer around the mask in the semiconductor layer having the mesa structure with the mask formed on the upper surface; A removal step of removing the mask; and after finishing the removal step, an insulating film having an opening is formed from the upper surface to the periphery of the mesa structure, and Schottky junction is formed with the upper surface through the inside of the opening. Forming an electrode over the insulating film extending from the inside of the opening to the periphery of the mesa structure; Obtain. According to this embodiment, since it is not necessary to separately prepare a mask used for the ion implantation process by self-alignment using the mask used for the etching process, manufacturing cost can be suppressed.

  The present invention can be realized in various forms other than the semiconductor device and the manufacturing method thereof. For example, the present invention can be realized in the form of a power conversion device including the semiconductor device of the above form and a manufacturing apparatus that performs the manufacturing method of the above form. .

  According to the present invention, reverse leakage current through the second region can be prevented, and electric field concentration at the end of the Schottky junction interface can be suppressed by the second region. As a result, the reverse leakage current can be effectively suppressed.

It is sectional drawing which shows the structure of a semiconductor device typically. It is process drawing which shows the manufacturing method of a semiconductor device. It is a graph which shows the result of having evaluated the relationship between distance and reverse direction leakage current. It is sectional drawing which shows typically the structure of the semiconductor device 200 in 2nd Embodiment. It is process drawing which shows the manufacturing method of the semiconductor device 200 in 2nd Embodiment. It is explanatory drawing which shows a mode that a semiconductor device is manufactured. It is explanatory drawing which shows a mode that a semiconductor device is manufactured. It is sectional drawing which shows typically the structure of the semiconductor device in 3rd Embodiment. It is explanatory drawing which shows the structure of a power converter device.

A. First Embodiment FIG. 1 is a cross-sectional view schematically showing a configuration of a semiconductor device 100. FIG. 1 shows XYZ axes orthogonal to each other. Of the XYZ axes in FIG. 1, the X axis is an axis from the left side to the right side in FIG. The + X-axis direction is a direction toward the right side of the paper, and the -X-axis direction is a direction toward the left side of the paper. Of the XYZ axes in FIG. 1, the Y axis is an axis that extends from the front side of the paper in FIG. 1 toward the back of the paper. The + Y-axis direction is a direction toward the back of the sheet, and the -Y-axis direction is a direction toward the front of the sheet. Of the XYZ axes in FIG. 1, the Z axis is an axis that extends from the bottom of FIG. 1 to the top of the page. The + Z-axis direction is a direction toward the paper surface, and the -Z-axis direction is a direction toward the paper surface. The XYZ axes in FIG. 1 correspond to the XYZ axes in the other drawings.

  The semiconductor device 100 is a GaN-based semiconductor device formed using gallium nitride (GaN). In the present embodiment, the semiconductor device 100 is a vertical Schottky barrier diode. In the present embodiment, the semiconductor device 100 is used for power control and is also called a power device. The semiconductor device 100 includes a substrate 110, a semiconductor layer 120, an insulating film 130, an anode electrode 140, and a cathode electrode 150.

  The substrate 110 of the semiconductor device 100 is a semiconductor having a plate shape extending along the X axis and the Y axis. The thickness of the substrate 110 (the length in the Z-axis direction) is preferably 100 μm or more and 500 μm or less, and is about 300 μm in this embodiment.

In the present embodiment, the substrate 110 is mainly made of gallium nitride (GaN). In the description of the present specification, “mainly composed of gallium nitride (GaN)” means that 90% or more of gallium nitride (GaN) is contained in a molar fraction. In the present embodiment, the substrate 110 is an n-type semiconductor having n-type characteristics. In the present embodiment, the substrate 110 contains silicon (Si) as a donor element. In this embodiment, the average value of the silicon (Si) concentration contained in the substrate 110 is about 1 × 10 ¹⁸ cm ⁻³ .

  The semiconductor layer 120 of the semiconductor device 100 is formed on the substrate 110. In this embodiment, in this embodiment, the semiconductor layer 120 is formed on the + Z-axis direction side of the substrate 110. The semiconductor layer 120 is a semiconductor layer formed by epitaxial growth (crystal growth). In the present embodiment, the semiconductor layer 120 extends along the X axis and the Y axis. The thickness (the length in the Z-axis direction) of the semiconductor layer 120 is preferably 5 μm or more and 30 μm or less, and is about 10 μm in this embodiment.

In the present embodiment, the semiconductor layer 120 is mainly made of gallium nitride (GaN). In the present embodiment, the semiconductor layer 120 is an n-type semiconductor having n-type characteristics. In the present embodiment, the semiconductor layer 120 contains silicon (Si) as a donor element. In this embodiment, the average value of the silicon (Si) concentration contained in the semiconductor layer 120 is about 1 × 10 ¹⁶ cm ⁻³ . The semiconductor layer 120 includes a low resistance region 120a and a high resistance region 120b.

  The low resistance region 120a of the semiconductor layer 120 is a first region that forms the anode electrode 140 and the Schottky junction interface SB. The Schottky junction interface SB is an interface where the low resistance region 120a and the anode electrode 140 are in contact with each other to make a Schottky junction. The low resistance region 120a has a lower electrical resistance than the high resistance region 120b. In the present embodiment, the low resistance region 120a constitutes a part of the surface of the semiconductor layer 120 on the + Z-axis direction side and the entire surface of the semiconductor layer 120 on the −Z-axis direction side. The low resistance region 120a is a region of the semiconductor layer 120 that is not affected by ion implantation.

  The high resistance region 120b of the semiconductor layer 120 is a second region having a higher electrical resistance than the low resistance region 120a. The high resistance region 120b is formed outside the Schottky junction interface SB. The high resistance region 120b sandwiches the insulating film 130 between the anode electrode 140 and the high resistance region 120b. In the present embodiment, the high resistance region 120b constitutes a part of the surface of the semiconductor layer 120 on the + Z axis direction side.

The high resistance region 120b is a region of the semiconductor layer 120 in which atoms that increase the electrical resistance of the semiconductor layer 120 are ion-implanted. The high resistance region 120b includes, as atoms that increase the electrical resistance of the semiconductor layer 120, boron (B), neon (Ne), argon (Ar), zinc (Zn), carbon (C), iron (Fe), nitrogen ( N), fluorine (F) and magnesium (Mg) are preferably contained in the range of 1 × 10 ¹⁵ cm ^{−3 to} 1 × 10 ²² cm ⁻³ . In the present embodiment, the high resistance region 120b contains boron (B) in the range of 1 × 10 ¹⁵ cm ⁻³ or more and 1 × 10 ²² cm ⁻³ or less as atoms that increase the electrical resistance of the semiconductor layer 120.

  From the viewpoint of suppressing the reverse leakage current, the high resistance region 120b includes the end Ei of the Schottky junction interface SB and the end of the anode electrode 140 in the plane direction (X-axis direction and Y-axis direction) in which the semiconductor layer 120 extends. It is preferably present on the Schottky junction interface SB side from the intermediate point Pc with Ee.

  From the viewpoint of suppressing reverse leakage current, the high resistance region 120b is separated from the end Ei of the Schottky junction interface SB by 0.5 μm or more in the plane direction (X axis direction and Y axis direction) in which the semiconductor layer 120 extends. Preferably it is. Further, from the viewpoint of suppressing reverse leakage current, the high resistance region 120b is preferably present within 5.0 μm in the plane direction (X-axis direction and Y-axis direction) in which the semiconductor layer 120 extends, and is 1.0 μm. More preferably, it is present within. That is, the distance Ds between the end Ei of the Schottky junction interface SB and the high resistance region 120b is preferably 0.5 μm or more and 5.0 μm or less, and preferably 0.5 μm or more and 1.0 μm or less. Even more preferable.

The insulating film 130 of the semiconductor device 100 is an insulator formed on the semiconductor layer 120. In the present embodiment, the insulating film 130 is formed on the + Z axis direction side of the semiconductor layer 120. The insulating film 130 has an opening 138. In the present embodiment, a Schottky junction interface SB is formed inside the opening 138. In the present embodiment, the insulating film 130 has an insulating layer (thickness) mainly made of silicon oxide (SiO ₂ ) on an insulating layer (thickness: about 100 nm) mainly made of aluminum oxide (Al ₂ O ₃ ). : About 500 nm).

  The anode electrode 140 of the semiconductor device 100 is a Schottky electrode that forms the Schottky junction interface SB with the semiconductor layer 120 through the inside of the opening 138. In the present embodiment, the thickness (length in the Z-axis direction) of the anode electrode 140 is about 100 nm. The anode electrode 140 is composed of one or more metal layers mainly composed of at least one of nickel (Ni), palladium (Pd), platinum (Pt), iridium (Ir), and the like. In the present embodiment, the cathode electrode 150 is composed of one metal layer mainly made of nickel (Ni).

  The anode electrode 140 is formed from the inside of the opening 138 in the insulating film 130 over the insulating film 130. As a result, the anode electrode 140 forms a field plate structure in which the insulating film 130 is sandwiched between the anode electrode 140 and the semiconductor layer 120. From the viewpoint of suppressing electric field concentration at the end Ei of the Schottky junction interface SB, the length Lf of the field plate structure in the anode electrode 140 is preferably 1.0 μm or more, more preferably 5.0 μm or more, and even more preferably 10 μm or more. preferable. From the viewpoint of improving the degree of integration of the semiconductor device 100, the length Lf is preferably 1 mm or less.

  The cathode electrode 150 of the semiconductor device 100 is a back electrode formed on the opposite side of the substrate 110 from the side on which the semiconductor layer 120 is formed. In the present embodiment, the cathode electrode 150 is formed on the −Z axis direction side of the substrate 110. The cathode electrode 150 is in ohmic contact with the substrate 110. In the present embodiment, the thickness (the length in the Z-axis direction) of the cathode electrode 150 is about 2 μm. The cathode electrode 150 is composed of one or more metal layers mainly composed of at least one of aluminum-silicon (AlSi), titanium (Ti), copper (Cu), and gold (Au). In the present embodiment, the cathode electrode 150 has a multilayer structure in which a metal layer mainly made of aluminum-silicon (AlSi) is laminated on a metal layer mainly made of titanium (Ti).

  FIG. 2 is a process diagram showing a method for manufacturing the semiconductor device 100. First, the manufacturer of the semiconductor device 100 forms the semiconductor layer 120 (process P110). In the present embodiment, the manufacturer forms the semiconductor layer 120 on the substrate 110 by epitaxial growth using metal organic chemical vapor deposition (MOCVD). In this embodiment, the manufacturer forms the semiconductor layer 120 mainly composed of gallium nitride (GaN).

  After forming the semiconductor layer 120 (process P110), the manufacturer performs an ion implantation process (process P120). In the ion implantation process (process P120), the manufacturer forms an ion implantation mask on a portion of the surface of the semiconductor layer 120 to be left as the low resistance region 120a. The ion implantation mask is a photoresist in this embodiment, and may be an insulating film or a metal film in other embodiments.

  After forming the ion implantation mask, the manufacturer ion-implants atoms that increase the electrical resistance of the semiconductor layer 120 around the ion implantation mask in the semiconductor layer 120. As a result, the portion of the semiconductor layer 120 affected by the ion implantation becomes the high resistance region 120b. After the ion implantation is completed, the manufacturer removes the ion implantation mask.

The ion implantation species in the ion implantation process (process P120) are boron (B), neon (Ne), argon (Ar), zinc (Zn), carbon (C), iron (Fe), nitrogen (N), fluorine ( At least one of F) and magnesium (Mg) is preferable, and in this embodiment, boron (B). The ion implantation amount in the ion implantation step (process P120) is 1 × 10 ¹³ cm so that the ion implantation species included in the high resistance region 120b is 1 × 10 ¹⁵ cm ⁻³ or more and 1 × 10 ²² cm ⁻³ or more. It is preferably in the range of not less than ^{−2 and not} more than 1 × 10 ¹⁶ cm ⁻² . From the viewpoint of preventing the channeling effect during ion implantation, the ion implantation angle in the ion implantation step (process P120) is preferably 5 degrees or more and 10 degrees or less with respect to the Z-axis direction.

  In order to maintain the electrical resistance of the high resistance region 120b which has been increased by the ion implantation, after forming the high resistance region 120b in the ion implantation step (process P120), the manufacturer activates the ions implanted into the high resistance region 120b. Do not perform excessive heat treatment.

After performing the ion implantation process (process P120), the manufacturer forms the insulating film 130 (process P130). In this embodiment, the manufacturer forms an insulating layer mainly made of aluminum oxide (Al ₂ O ₃ ) using an atomic layer deposition (ALD) method, and then uses plasma chemical vapor deposition ( The insulating film 130 is formed by laminating an insulating layer mainly made of silicon oxide (SiO ₂ ) using plasma CVD: Plasma Chemical Vapor Deposition. In this embodiment, the manufacturer forms the opening 138 in the insulating film 130 by dry etching.

  After forming the insulating film 130 (process P130), the manufacturer forms the anode electrode 140 and the cathode electrode 150 (process P140). In the present embodiment, the anode electrode 140 is formed as a metal layer mainly composed of nickel (Ni) by using an electron beam evaporation method. In this embodiment, the manufacturer forms a metal layer mainly composed of titanium (Ti) by using an electron beam evaporation method, and then laminates the metal layer mainly composed of aluminum-silicon (AlSi). A cathode electrode 150 is formed. Through these steps, the semiconductor device 100 is completed.

  FIG. 3 is a graph showing the results of evaluating the relationship between the distance Ds and the reverse leakage current. In the evaluation test of FIG. 3, the tester prepared semiconductor devices having different distances Ds as samples. The structure of each sample is the same as that of the semiconductor device 100 described above except that the distances Ds are different. The tester applied a reverse voltage of 200 V to each sample, and measured the reverse leakage current flowing at that time.

  The distance Ds of each sample is −3.0 μm, 0.0 μm, 0.5 μm, 1.0 μm, 5.0 μm, 10.0 μm and 15.0 μm. In the sample having the distance Ds of 0.0 μm, the high resistance region 120b exists outside the end Ei of the Schottky junction interface SB. The distance Ds that is a negative value indicates the length that the high resistance region 120b has entered inside the end Ei of the Schottky junction interface SB. The length Lf of the field plate structure in each sample is 10.0 μm.

  The horizontal axis in FIG. 3 indicates the distance Ds between the end Ei of the Schottky junction interface SB and the high resistance region 120b. The vertical axis in FIG. 3 represents the reverse leakage current ratio, which is the ratio of the reverse leakage current of each sample to the reverse leakage current of the sample whose distance Ds is 15 μm. The vertical axis in FIG. 3 is a logarithmic axis.

  According to the evaluation results of FIG. 3, the distance Ds is preferably larger than 0.0 μm from the viewpoint of suppressing the reverse leakage current. In other words, the high resistance region 120b is preferably located outside the Schottky junction interface SB. From the viewpoint of further suppressing the reverse leakage current, the distance Ds is preferably 0.5 μm or more and 5.0 μm or less, and more preferably 0.5 μm or more and 1.0 μm or less. Further, in the relationship between the distance Ds and the length Lf, the distance Ds is preferably shorter than half the length Lf (5.0 μm). In other words, the high resistance region 120b is preferably present on the Schottky junction interface SB side from the intermediate point Pc.

  In the first embodiment described above, the high resistance region 120b is formed outside the Schottky junction interface SB, and the insulating film 130 is sandwiched between the anode electrode 140 and the high resistance region 120b. Therefore, reverse leakage current through the high resistance region 120b can be prevented, and electric field concentration at the end Ei of the Schottky junction interface SB can be suppressed by the high resistance region 120b. As a result, the reverse leakage current can be effectively suppressed.

  Further, the high resistance region 120b has a Schottky junction interface SB from an intermediate point Pc between the end Ei of the Schottky junction interface SB and the end Ee of the anode electrode 140 in the plane direction (X-axis direction and Y-axis direction). Therefore, electric field concentration at the end Ei of the Schottky junction interface SB can be effectively suppressed.

  Further, since the high resistance region 120b is separated from the end Ei of the Schottky junction interface SB by 0.5 μm or more in the surface direction (X-axis direction and Y-axis direction), reverse leakage through the high resistance region 120b is caused. Current can be sufficiently prevented.

  Further, since the high resistance region 120b exists within 1.0 μm from the end Ei of the Schottky junction interface SB in the plane direction (X-axis direction and Y-axis direction), the high-resistance region 120b is located at the end Ei of the Schottky junction interface SB. Electric field concentration can be further suppressed.

B. Second Embodiment FIG. 4 is a cross-sectional view schematically showing a configuration of a semiconductor device 200 according to a second embodiment. FIG. 4 shows the XYZ axes as in FIG.

  The semiconductor device 200 is a GaN-based semiconductor device formed using gallium nitride (GaN). In the present embodiment, the semiconductor device 200 is a vertical Schottky barrier diode. In the present embodiment, the semiconductor device 200 is used for power control and is also called a power device.

  The semiconductor device 200 includes a substrate 210, a semiconductor layer 220, an insulating film 230, an anode electrode 240, and a cathode electrode 250. The substrate 210 of the semiconductor device 200 is the same as the substrate 110 of the first embodiment. The cathode electrode 250 of the semiconductor device 200 is the same as the cathode electrode 150 of the first embodiment.

  The semiconductor layer 220 of the semiconductor device 200 is the same as the semiconductor layer 120 of the first embodiment except that it has a mesa structure 220m. The mesa structure 220m has a plateau shape having an upper surface 221 and a side surface 222. A peripheral surface 223 extends around the mesa structure 220m. In the present embodiment, the mesa structure 220m is a structure formed by dry etching in the −Z-axis direction with respect to the semiconductor layer 220. In the present embodiment, the thickness of the semiconductor layer 220 (the length in the Z-axis direction) is about 10 μm in the mesa structure 220m portion.

  From the viewpoint of suppressing electric field concentration at the end Ei of the Schottky junction interface SB, the height Hm of the mesa structure 220m is preferably thicker than the thickness of the insulating film 230. From the viewpoint of ensuring workability, the height Hm of the mesa structure 220m is preferably 5.0 μm or less. From the viewpoint of suppressing electric field concentration at the end Ei of the Schottky junction interface SB, the angle Am of the side surface 222 with respect to the peripheral surface 223 is preferably 10 ° or more and 90 ° or less.

  The semiconductor layer 220 includes a low resistance region 220a and a high resistance region 220b. The low resistance region 220a is the same as the low resistance region 120a of the first embodiment except that the anode electrode 240 and the Schottky junction interface SB are formed on the upper surface 221 of the mesa structure 220m. The high resistance region 220b is the same as the high resistance region 120b of the first embodiment except that the high resistance region 220b is formed at least on the side surface 222 of the mesa structure 220m. In the present embodiment, the high resistance region 220 b is formed from the entire side surface 222 to the peripheral surface 223.

  The insulating film 230 of the semiconductor device 200 is the same as the insulating film 130 of the first embodiment except that the insulating film 230 is formed from the upper surface 221 to the peripheral surface 223 through the side surface 222 and has an opening 238 on the upper surface 221. is there.

  The anode electrode 240 of the semiconductor device 200 is formed from the inside of the opening 238 to the top of the insulating film 230 extending to the peripheral surface 223, and the Schottky junction interface SB is formed on the upper surface 221 through the inside of the opening 238. Except for the point to form, it is the same as the anode electrode 140 of 1st Embodiment.

  FIG. 5 is a process diagram illustrating a method for manufacturing the semiconductor device 200 according to the second embodiment. 6 and 7 are explanatory views showing a state in which the semiconductor device 200 is manufactured. First, the manufacturer of the semiconductor device 200 forms the semiconductor layer 220 similarly to the semiconductor layer 120 of the first embodiment (process P210).

  After forming the semiconductor layer 220 (process P210), the manufacturer performs an etching process (process P215, FIG. 6). In the etching process (process P215), the manufacturer forms a mask 810 in the semiconductor layer 220, and then etches the periphery of the mask 810 in the semiconductor layer 220, whereby the portion where the mask 810 is formed becomes the mesa. A structure 220m is formed. Thus, the manufacturer obtains the semiconductor device 200a in which the mesa structure 220m is formed in the semiconductor layer 220 as the semiconductor device 200 being manufactured. In this embodiment, the manufacturer forms the mesa structure 220m by dry etching.

  After finishing the etching process (process P215), the manufacturer performs an ion implantation process (process P220, FIG. 7). In the ion implantation process (process P220), the manufacturer ion-implants atoms that increase the electrical resistance of the semiconductor layer 220 around the mask 810 in the semiconductor layer 220 of the semiconductor device 200a where the mask 810 is left. Thus, the manufacturer obtains the semiconductor device 200b in which the high resistance region 220b is formed from the side surface 222 to the peripheral surface 223. The ion implantation process (process P220) of the second embodiment is the same as the ion implantation process (process P120) of the first embodiment except that the mask 810 used in the etching process (process P215) is used.

  After finishing the ion implantation process (process P220), the manufacturer performs a removal process (process P225). In the removal process (process P225), the manufacturer removes the mask 810 from the upper surface 221 of the semiconductor device 200b.

  After finishing the removal process (process P225), the manufacturer forms the insulating film 230 in the same manner as the insulating film 130 of the first embodiment (process P230). Thereafter, the manufacturer forms the anode electrode 240 and the cathode electrode 250 in the same manner as in the first embodiment (process P240). Through these steps, the semiconductor device 200 is completed.

  According to the second embodiment described above, similarly to the first embodiment, reverse leakage current through the high resistance region 220b is prevented, and at the end Ei of the Schottky junction interface SB by the high resistance region 220b. Electric field concentration can be suppressed. As a result, the reverse leakage current can be effectively suppressed.

  Further, the Schottky junction interface SB is formed on the upper surface 221 of the mesa structure 220m, and the high resistance region 220b is formed from the side surface 222 to the peripheral surface 223. Therefore, the electric field concentration at the end Ei of the Schottky junction interface SB can be further suppressed by the mesa structure 220m.

  Further, since the mask used for the ion implantation process (process P220) does not need to be separately manufactured by self-alignment using the mask 810 used in the etching process (process P215), the manufacturing cost can be suppressed.

C. Third Embodiment FIG. 8 is a cross-sectional view schematically showing a configuration of a semiconductor device 300 according to a third embodiment. FIG. 8 shows the XYZ axes as in FIG.

  The semiconductor device 300 is the same as the semiconductor device 200 of the second embodiment except that the semiconductor device 300 includes an insulating film 330 instead of the insulating film 230 and a cathode electrode 340 instead of the anode electrode 240. The cathode electrode 340 of the semiconductor device 300 includes a Schottky electrode 341 and a wiring electrode 342.

  The insulating film 330 of the semiconductor device 300 is formed from the top of the Schottky electrode 341 to the peripheral surface 223 through the upper surface 221 and the side surface 222, and the point having the opening 338 on the Schottky electrode 341, This is the same as the insulating film 230 of the second embodiment.

  The Schottky electrode 341 of the cathode electrode 340 in the semiconductor device 300 forms a Schottky junction interface SB on the upper surface 221 of the semiconductor layer 220. In this embodiment, the Schottky electrode 341 includes, in order from the semiconductor layer 220 side, a metal layer (thickness: about 100 nm) mainly made of nickel (Ni) and a metal layer (thickness) mainly made of palladium (Pd). : About 100 nm) and a multilayer structure in which a metal layer (thickness: about 20 nm) mainly composed of molybdenum (Mo) is laminated.

  The wiring electrode 342 of the cathode electrode 340 in the semiconductor device 300 is formed from the inside of the opening 338 of the insulating film 330 over the insulating film 330 spreading on the peripheral surface 223. As a result, the wiring electrode 342 forms a field plate structure in which the insulating film 330 is interposed between the wiring electrode 342 and the semiconductor layer 220. The wiring electrode 342 contacts the Schottky electrode 341 inside the opening 338. In the present embodiment, the wiring electrode 342 includes, in order from the semiconductor layer 220 side, a metal layer mainly composed of titanium (Ti) (thickness: about 20 nm) and a metal layer mainly composed of titanium nitride (TiN) (thickness). : About 200 nm), a multilayer structure in which a metal layer mainly composed of titanium (Ti) (thickness: about 20 nm) and a metal layer mainly composed of aluminum-silicon (AlSi) (thickness: about 2000 nm) are laminated. Have

  According to the third embodiment described above, as in the first embodiment, reverse leakage current through the high resistance region 220b is prevented, and at the end Ei of the Schottky junction interface SB by the high resistance region 220b. Electric field concentration can be suppressed. As a result, the reverse leakage current can be effectively suppressed.

  Similarly to the second embodiment, the Schottky junction interface SB is formed on the upper surface 221 of the mesa structure 220m, and the high resistance region 220b is formed from the side surface 222 to the peripheral surface 223. Therefore, the electric field concentration at the end Ei of the Schottky junction interface SB can be further suppressed by the mesa structure 220m.

  In addition, since the cathode electrode 340 is divided into the Schottky electrode 341 and the wiring electrode 342, the Schottky junction interface SB has a higher Schottky barrier height without being restricted by the adhesion to the insulating film 330. The configuration (material and structure) of the Schottky electrode 341 capable of realizing the above can be selected. As a result, the reverse leakage current can be more effectively suppressed.

D. Fourth Embodiment FIG. 9 is an explanatory diagram showing a configuration of the power conversion device 10. The power converter 10 is a device that converts power supplied from the AC power source E to the load R. The power conversion device 10 includes a control circuit 20, a transistor TR, four diodes D1, a coil L, a diode D2, and a capacitor C as components of a power factor correction circuit that improves the power factor of the AC power source E. Is provided. In the present embodiment, the diodes D1 and D2 are the same as the semiconductor device 100 of the first embodiment. In other embodiments, the diodes D1 and D2 may be the same as the semiconductor device 200 of the second embodiment, or may be the same as the semiconductor device 300 of the third embodiment.

  Diodes D1 and D2 of power converter 10 are Schottky barrier diodes. In the power conversion device 10, the four diodes D1 constitute a diode bridge DB that rectifies the AC voltage of the AC power source E. The diode bridge DB has a positive electrode output terminal Tp and a negative electrode output terminal Tn as terminals on the DC side. The coil L is connected to the positive electrode output terminal Tp of the diode bridge DB. The anode side of the diode D2 is connected to the positive electrode output terminal Tp via the coil L. The cathode side of the diode D2 is connected to the negative output terminal Tn via the capacitor C. The load R is connected in parallel with the capacitor C.

  The transistor TR of the power conversion device 10 is an FET (Field-Effect Transistor). The source side of the transistor TR is connected to the negative output terminal Tn. The drain side of the transistor TR is connected to the positive electrode output terminal Tp via the coil L. The gate side of the transistor TR is connected to the control circuit 20. The control circuit 20 of the power conversion device 10 is configured so that the source-drain of the transistor TR is based on the voltage output to the load R and the current in the diode bridge DB so that the power factor of the AC power supply E is improved. Control the current.

  According to the fourth embodiment described above, the device characteristics of the diodes D1 and D2 can be improved. As a result, the power conversion efficiency by the power conversion device 10 can be improved.

E. Other Embodiments The present invention is not limited to the above-described embodiments, examples, and modifications, and can be realized with various configurations without departing from the spirit thereof. For example, among the technical features in the embodiments, examples, and modifications, those corresponding to the technical features in each embodiment described in the summary section of the invention are for solving some or all of the above-described problems. Alternatively, in order to achieve part or all of the above-described effects, replacement and combination can be performed as appropriate. Further, technical features that are not described as essential in the present specification can be appropriately deleted.

In the above-described embodiment, the material of the substrate is not limited to gallium nitride (GaN), and may be any of silicon (Si), sapphire (Al ₂ O ₃ ), silicon carbide (SiC), and the like.

  In the above-described embodiment, the material of the semiconductor layer is not limited to gallium nitride (GaN), but may be other group III nitrides (for example, aluminum nitride (AlN) and indium nitride (InN)), Silicon carbide (SiC) may be used.

  In the above-described embodiment, the donor element contained in the substrate and the semiconductor layer is not limited to silicon (Si), but may be germanium (Ge), oxygen (O), or the like.

  In the above-described embodiment, the substrate and the semiconductor layer are not limited to n-type semiconductors but may be p-type semiconductors. The acceptor element contained in the p-type semiconductor may be magnesium (Mg), zinc (Zn), carbon (C), or the like.

In the above-described embodiment, the material of the insulating film may be any material having electrical insulation properties, and in addition to silicon dioxide (SiO ₂ ), silicon nitride (SiNx), aluminum oxide (Al ₂ O ₃ ), aluminum nitride ( AlN), zirconium oxide (ZrO ₂ ), hafnium oxide (HfO ₂ ), silicon oxynitride (SiON), aluminum oxynitride (AlON), zirconium oxynitride (ZrON), hafnium oxynitride (HfON), etc. There may be. The insulating film may be a single layer or two or more layers.

  In the above-described embodiment, the material of each electrode is not limited to the material of the above-described embodiment, and may be other materials.

DESCRIPTION OF SYMBOLS 10 ... Power converter 20 ... Control circuit 100 ... Semiconductor device 110 ... Substrate 120 ... Semiconductor layer 120a ... Low resistance area 120b ... High resistance area 130 ... Insulating film 138 ... Opening 140 ... Anode electrode 150 ... Cathode electrode 200 ... Semiconductor device 200a, 200b ... Semiconductor device 210 ... Substrate 220 ... Semiconductor layer 220a ... Low resistance region 220b ... High resistance region 220m ... Mesa structure 221 ... Upper surface 222 ... Side surface 223 ... Peripheral surface 230 ... Insulating film 238 ... Opening 240 ... Anode electrode 250 ... Cathode electrode 300 ... Semiconductor device 330 ... Insulating film 338 ... Opening 340 ... Cathode electrode 341 ... Schottky electrode 342 ... Wiring electrode 810 ... Mask

Claims (11)

A semiconductor device,
A semiconductor layer;
An insulating film formed on the semiconductor layer and having an opening;
An electrode that is formed from the inside of the opening to the top of the insulating film, and that forms a Schottky junction interface with the semiconductor layer through the inside of the opening,
The semiconductor layer is
A first region forming the electrode and the Schottky junction interface;
And a second region formed outside the Schottky junction interface, sandwiching the insulating film between the electrodes and having a higher electric resistance than the first region.   The second region is present on the Schottky junction interface side from an intermediate point between an end portion of the Schottky junction interface and an end portion of the electrode in a plane direction in which the semiconductor layer extends. The semiconductor device described.   3. The semiconductor device according to claim 1, wherein the second region is separated from an end of the Schottky junction interface by 0.5 μm or more in a plane direction in which the semiconductor layer extends.   4. The semiconductor according to claim 1, wherein the second region exists within 5.0 μm from an end of the Schottky junction interface in a plane direction in which the semiconductor layer extends. 5. apparatus.   5. The semiconductor according to claim 1, wherein the second region exists within 1.0 μm from an end of the Schottky junction interface in a plane direction in which the semiconductor layer extends. apparatus. A semiconductor device according to any one of claims 1 to 5,
The semiconductor layer has a mesa structure having a plateau shape having an upper surface and side surfaces;
The Schottky junction interface is formed on the upper surface,
The semiconductor device, wherein the second region is formed at least on the side surface.   The semiconductor device according to any one of claims 1 to 6, wherein the semiconductor layer is mainly made of gallium nitride (GaN). The second region includes boron (B), neon (Ne), argon (Ar), zinc (Zn), carbon (C), iron (Fe), nitrogen (N), fluorine (F) and magnesium (Mg). ) In the range of 1 × 10 ¹⁵ cm ^{−3 to} 1 × 10 ²² cm ⁻³ . 8. The semiconductor device according to claim 1.   9. The electrode according to claim 1, wherein the electrode includes a metal layer mainly composed of at least one of nickel (Ni), palladium (Pd), platinum (Pt), and iridium (Ir). A semiconductor device according to 1.   A power converter device comprising the semiconductor device according to any one of claims 1 to 9. A method for manufacturing a semiconductor device, comprising:
An etching step of forming a mesa structure with the portion where the mask is formed as an upper surface by etching the periphery of the mask in the semiconductor layer where the mask is formed;
After the etching step, an ion implantation step of ion-implanting atoms that increase the electrical resistance of the semiconductor layer around the mask in the semiconductor layer having the mesa structure with the mask formed on the upper surface;
A removal step of removing the mask after finishing the ion implantation;
After finishing the removing step, an insulating film having an opening is formed from the upper surface to the periphery of the mesa structure, and an electrode that forms a Schottky junction with the upper surface through the inside of the opening is formed from the inside of the opening And a step of forming over the insulating film extending around the mesa structure.

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