JP2002246610A - Semiconductor element - Google Patents

Abstract

PROBLEM TO BE SOLVED: To reduce leak current while ensuring a high current capacity in a semiconductor element where Schottky barrier and the rectifying part of a PN junction are arranged contiguously to each other. SOLUTION: A plurality of insular P+ type silicon regions 15 are formed in the surface region of an N type silicon region 12. An anode electrode 13 is provided above the P+ type silicon region 15 through an insulation film 16 having an opening 16a. Outermost circumferential P+ type silicon region 15a in the vicinity of the opening 16a is arranged not to touch the anode electrode 13. Furthermore, the P+ type silicon region 15a is arranged to form a substantially integrated depletion layer upon application of a reverse voltage.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device having a rectifying function, and more particularly to a semiconductor device in which a rectifying portion having a Schottky barrier and a rectifying portion having a PN junction are adjacent to each other.

[0002]

2. Description of the Related Art A semiconductor device used for a rectifier or the like, for example, a switching device is required to have high switching speed and forward and reverse characteristics. As such a semiconductor rectifier, a PN junction diode using a PN junction and a Schottky diode using a Schottky junction are widely used.

A PN junction diode has high reverse characteristics, such as low leakage current and high withstand voltage when a reverse voltage is applied. However, a PN junction diode has a low switching speed and is not suitable for use in a high-speed circuit. As a means for improving the switching speed, there is a method of diffusing a heavy metal such as gold or platinum. However, while the switching speed is improved, the reverse leakage current increases and the forward voltage drop increases.

[0004] Schottky diodes have high switching characteristics such as high switching speed. However, the Schottky diode has low reverse characteristics, and has a problem particularly when used in a high-voltage, large-current circuit. For example, the resistance to the overvoltage in the reverse direction (surge resistance) is low, and when a reverse voltage near the breakdown voltage is applied, the leakage current flowing over the Schottky barrier sharply increases, so that the element is likely to be destroyed.

As a semiconductor element having both the characteristics of the PN junction diode and the Schottky diode described above, there is known a semiconductor element disclosed in Japanese Patent Publication No. 59-35183. The semiconductor device disclosed above has a configuration in which a rectifying portion having a Schottky barrier and a rectifying portion having a PN junction are arranged adjacent to each other.

The semiconductor device has a structure in which, when viewed in cross section, a rectifying portion of a Schottky barrier and a rectifying portion of a PN junction are alternately arranged adjacent to an interface between an electrode (Schottky metal) and a semiconductor layer. Having. According to the above configuration, at the time of forward operation, a current flows through the Schottky barrier, so that a high switching characteristic similar to that of a Schottky diode can be obtained. Also, during the reverse operation, the Schottky junction region is filled with a depletion layer formed by the PN junction, so that leakage current from the Schottky junction region can be suppressed. Therefore, good reverse voltage characteristics (surge resistance) can be obtained.

However, in the above-described semiconductor device, when a reverse voltage is applied, a region where a rectifying portion formed by a Schottky junction and a junction portion formed by a PN junction are arranged adjacent to each other (hereinafter, referred to as a “rectifying composite region”). The leakage current is likely to flow at the peripheral edge of ()).

As a means for preventing a leakage current, there is known a method of forming an annular guard ring region so as to be adjacent to and surround the outer periphery of a rectifying composite region. The guard ring region is formed as a PN junction region and provided in contact with the electrode. That is, the outer periphery of the rectification composite region is
The junction is terminated, and a boundary portion between the insulating film and the electrode is formed on the surface of the diffusion region constituting the PN junction at the termination. The guard ring region surrounding the rectifying composite region effectively prevents leakage current from the peripheral edge by a depletion layer extending around the guard ring region when a reverse voltage is applied.

[0009]

In a configuration having a guard ring region, when a small current or a medium current flows,
The forward current mainly flows through the Schottky junction. Therefore, the guard ring region becomes a substantially inactive region during the forward operation, and by forming the guard ring region, the substantial current capacity of the device is reduced. As described above, the conventional semiconductor element having the structure in which the Schottky junction and the PN junction are adjacent to each other cannot effectively prevent the leakage current while securing a high current capacity.

In view of the above circumstances, an object of the present invention is to provide a highly reliable semiconductor device. It is another object of the present invention to provide a semiconductor device in which a Schottky barrier and a rectifying portion of a PN junction are arranged adjacent to each other and which can reduce a leakage current while securing a high current capacity.

[0011]

In order to achieve the above object, a semiconductor device according to the present invention is formed in a semiconductor substrate of a first conductivity type and in a surface region of the semiconductor substrate, and has a different impurity concentration from the semiconductor substrate. A first semiconductor region of a first conductivity type, a metal layer provided on the first semiconductor region and forming a Schottky junction with the first semiconductor region, and a metal layer on a surface region of the first semiconductor region. A second semiconductor layer formed to be in contact with the first semiconductor region and forming a PN junction with the first semiconductor region;
A second semiconductor region of a conductivity type, a peripheral region of a region of the first semiconductor region that contacts the metal layer, and a surface region that does not contact the metal layer, which is formed to surround the second semiconductor region; Second forming a PN junction with the first semiconductor region
A third semiconductor region of a conductivity type, wherein the first semiconductor region, the second semiconductor region and the third semiconductor region,
Is characterized in that when a reverse voltage is applied, a substantially integrated depletion layer is formed.

According to the above configuration, the Schottky junction and the PN
By providing a configuration in which the joint and the joint are arranged adjacent to each other,
A semiconductor device having a low forward voltage drop, a low leakage current, and a high surge resistance can be obtained. Further, according to the above configuration, the third semiconductor region not in contact with the metal layer, the second semiconductor region adjacent thereto, and the first semiconductor region are formed in the peripheral portion of the region in contact with the metal layer in the first semiconductor region. , A depletion layer is formed integrally with the peripheral portion when a reverse voltage is applied. Therefore, the leakage current can be reduced without providing a guard ring or the like on the peripheral portion. Furthermore, no guard ring or the like is provided on the peripheral portion, and a Schottky junction is formed by the metal layer and the first semiconductor region. Therefore, conduction of the peripheral portion when a forward voltage is applied is ensured, and substantially. High current capacity can be obtained.

In the above structure, for example, the third semiconductor region is formed so as to be exposed in a plurality of islands at equal intervals. Thus, when a reverse voltage is applied, the third semiconductor region can form a uniform depletion layer together with the second semiconductor.

In the above structure, for example, the second semiconductor region and the third semiconductor region are formed with substantially the same impurity concentration and diffusion depth. That is, the second semiconductor region and the third semiconductor region can be formed in the same step. Therefore, a semiconductor device can be manufactured at low manufacturing cost.

In the above structure, the third semiconductor region may be formed so as to be shallower than the second semiconductor region.

[0016]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS A semiconductor device according to an embodiment of the present invention will be described below with reference to the drawings. Figure 1
Shows a cross-sectional view of the semiconductor device according to the present embodiment,
FIG. 2 shows a plan view of the semiconductor device of FIG. The semiconductor element described below functions as a diode having a Schottky junction and a PN junction.

As shown in FIG. 1, a semiconductor device 1 according to the present embodiment has an N ^{+ type} silicon layer 11 and an N type silicon region 12 formed on a silicon substrate 10 made of silicon single crystal. It comprises an anode electrode 13 and a cathode electrode 14 provided on the front and back surfaces.

The N ^{+ type} silicon layer 11 is formed on the silicon substrate 1
0. The impurity concentration of the N ^{+ type} silicon layer 11 is, for example, about 1.5 × 10 ¹⁹ cm ⁻³ . N
The silicon region 12 is formed on the N ⁺ silicon layer 11 by epitaxial growth. N-type silicon region 12 has, for example, an impurity concentration of about 1.0 × 10 ¹⁶ cm ⁻³ . The thickness is 2 μm to 15 μm.
m. At this time, the specific resistance of the N-type silicon region 12 is about 0.5 Ωcm to 5 Ωcm.

The surface of the N-type silicon region 12 has a P⁺form
A silicon region 15 is formed. P⁺Silicon area
Region 15 is encapsulated in N-type silicon region 12 leaving its surface.
Surrounded by a plurality of islands in the surface region of the N-type silicon region 12.
They are formed at equal intervals. P ⁺The silicon region 15 is
For example, 1.0 × 10¹⁶cm^-3~ 1.0 × 10^{1 9}
cm^-3Impurity concentration, for example, 0.5 μm
It has a diffusion depth of about 10 to 10 μm.

The P ^{+ type} silicon region 15 forms a PN junction with the N type silicon region 12. This allows P
A rectifying portion is formed between the ^{+ type} silicon region 15 and the N type silicon region 12 by a PN junction.
It has a function as an N-junction diode.

FIG. 2 is a plan view of the semiconductor device 1 shown in FIG. As shown in FIG. 2, on the surface of the silicon substrate 10, a plurality of square P ⁺ -type silicon regions 15 are exposed in a lattice pattern. Therefore, the surface of the silicon substrate 10 has a configuration in which the N-type silicon region 12 is exposed in a mesh shape between the P ⁺ -type silicon regions 15 exposed in an island shape. Where P
The interval between the ^{+ -type} silicon regions 15 is, for example, 0.5 μm.
m to about 3 μm.

Referring back to FIG. 1, an insulating film 16 is disposed on the upper surface of the silicon substrate 10. The insulating film 16 is made of a silicon oxide film or the like, and has an opening 16a. When viewed from above as shown in FIG.
Opening 16a surrounds the plurality of P ⁺ -type silicon regions 15 and has the outermost periphery of the P ⁺ -type silicon region 1.
5a.

Returning to FIG. 1, an anode electrode 13 is provided on the upper surface of the insulating film 16. The anode electrode 13 is
It is made of a metal such as palladium and functions as an anode electrode of the semiconductor element 1 as a diode. The anode electrode 13 is in contact with the N-type silicon region 12 exposed inside the opening 16a via the opening 16a of the insulating film 16. The anode electrode 13 contacts the N-type silicon region 12 to form a Schottky junction with the N-type silicon region 12. As a result, a rectifying portion by a Schottky junction is formed between the anode electrode 13 and the N-type silicon region 12, and the semiconductor element 1 has a function as a Schottky diode.

As described above, the Schottky junction and the PN junction formed by the anode electrode 13, the N-type silicon region 12, and the P ⁺ -type silicon region 15 are formed on the anode-side main surface of the silicon substrate 10. A rectifying composite region formed by composite is formed. In the rectification composite region, the rectification portion by the PN junction and the rectification portion by the Schottky junction are alternately adjacent to each other. With the above configuration, the characteristics of the Schottky diode and the PN junction diode, that is, low forward voltage drop and reverse breakdown voltage can be obtained.

The distance between the P ^{+ type} silicon regions 15 is, for example, about 0.5 μm to 3 μm. Thereby, when a reverse voltage is applied to the semiconductor element 1,
As shown in FIG. 3, the island-shaped P ^{+ type} silicon region 15 and N
The depletion layer 30 formed by the PN junction with the silicon region 12 is connected to and substantially integrated with each other, so that a so-called pinch-off state is obtained. Thereby, the electric field intensity applied to the Schottky barrier formed between N-type silicon region 12 and anode electrode 13 is reduced, and the leakage current is reduced.

Here, the P ^{+ type} silicon region 15a at the outermost periphery of the P ^{+ type} silicon region 15 is
It is arranged in a position that does not contact with. However, the outermost P
^{The + -type} silicon region 15a receives another P when a reverse voltage is applied.
^The depletion layer 30 integrated with the ^{+ type} silicon region 15 is formed. Therefore, not formed the P ⁺ silicon region 15, the periphery of the contact area between the anode electrode 13 of the N-type silicon region 12 also, as shown in FIG. 3, it is formed from the outermost P ⁺ form silicon regions 15a It is covered by the depletion layer 30. This effectively prevents leakage current at the end of the anode electrode 13 when a reverse breakdown voltage is applied without providing a guard ring or the like.

Further, the anode of the N-type silicon region 12
P at the periphery of the contact area with the electrode 13 ⁺Silicon area 1
5 is not present, and the anode electrode 13 has an N-type
It comes into direct contact with the control region 12. As a result,
A Schottky junction is formed even when the
Indicates that the periphery can be energized even when a small or medium current is applied.
And a high current capacity can be obtained.

A cathode electrode 14 is provided on the lower surface of the silicon substrate 10 and is in low resistance contact with the N ^{+ type} silicon layer 11. The cathode electrode 14 is made of, for example, nickel. Here, the N ^{+ type} silicon layer 11 and the N type silicon region 12 function as a cathode region of the diode.

As described above, in the semiconductor device of the present embodiment, P ^{+ type} silicon region 15 is formed on the inner peripheral side of N type silicon region 12 in contact with anode electrode 13, The outermost P ⁺ -type silicon region 15a is arranged and formed at a position where it does not come into contact with. Also, the adjacent P ^{+ type} silicon region 1
The interval of 5 is such that the depletion layers 30 extending from the PN junction formed by the P ⁺ -type silicon region 15 including the outermost P ⁺ -type silicon region 15a are continuous with each other when the reverse breakdown voltage is applied.

Therefore, a low leakage current and a high surge withstand voltage when a reverse voltage is applied can be obtained without providing a guard ring or the like at the periphery of the contact region of the N-type silicon region 12 with the anode electrode 13. Therefore, a highly reliable semiconductor device 1 can be obtained. Further, the outer peripheral edge of the anode electrode 13 is in contact with the N-type silicon region 12, and a Schottky junction through which a forward current flows dominantly is also formed at the peripheral portion of the contact region, so that a high current capacity can be obtained.

Of course, the semiconductor device 1 having the above-described structure employs an element structure in which the rectifying portion of the Schottky barrier and the rectifying portion of the PN junction are arranged adjacent to each other. Is,
A low forward voltage drop and a high reverse breakdown voltage are obtained.

The present invention is not limited to the above embodiment, and various modifications and applications are possible. Hereinafter, modifications of the above-described embodiment applicable to the present invention will be described.

In the above embodiment, the N-type silicon region 1
The anode electrode 13 that forms a Schottky junction with the anode 2 is made of palladium, but is not limited thereto.
If it functions as a Schottky metal, such as chromium, titanium, molybdenum, tungsten, and aluminum,
Any metal is possible.

In the above embodiment, the structure is such that the P ^{+ type} silicon regions 15 are scattered in the N type silicon region 12 in an island shape. However, a configuration in which the P ^{+ type} silicon region 15 is formed in a stripe shape on the N type silicon region 12 is also possible.
Conversely, a configuration in which the N-type silicon region 12 is exposed in an island shape is also possible. Furthermore, the P ^{+ type} silicon region 15
May be a circle, a polygon, or the like, instead of a square.

In the above embodiment, the outermost P ⁺ -type silicon region 15a is formed in the same impurity diffusion step as the other P ⁺ -type silicon regions 15 and has substantially the same impurity concentration and diffusion depth. . However, the outermost P ^{+ type} silicon region 15a may be formed in another step, for example, may be formed to have a higher impurity concentration and shallower than the inner peripheral side. Also, regarding the interval between the P ^{+ type} silicon regions 15,
The distance between the outermost P ^{+ type} silicon region 15a and the innermost P ^{+ type} silicon region 15a may be changed. Furthermore, the outermost P
^The shapes of the ^{+ type} silicon region 15a and the P ^{+ type} silicon region 15 on the inner peripheral side may be changed. At this time, for example, as shown in FIG. 4, the outermost P ⁺ -type silicon region 15a is formed in a ring shape, and the inner peripheral side P ⁺ -type silicon region 15 is formed in an island shape, a ring shape, or a stripe shape. Is also good.

In the above embodiment, the N-type silicon region 1
The P ⁺ -type silicon region 15 was not formed at the peripheral portion of the contact region with the second anode electrode 13, so that the anode electrode 13 did not completely intersect the P ⁺ -type silicon region 15 at the peripheral portion. However, as shown in FIG. 5, the inner P ⁺ -type silicon region 15 adjacent to the outermost P ⁺ -type silicon region 15a may be partially in contact with the anode electrode 13.

In the above embodiment, the N-type silicon layer 12
The structure is such that a P-type diffusion region is formed thereon. However, the configuration is not limited to this, and an N-type diffusion region may be formed on the P-type silicon layer.

[0038]

As described above, according to the present invention,
A highly reliable semiconductor element is provided.

[Brief description of the drawings]

FIG. 1 is a sectional view of a semiconductor device according to an embodiment of the present invention.

FIG. 2 is a plan view of a semiconductor device according to an embodiment of the present invention.

FIG. 3 is a cross-sectional view of the semiconductor device when a reverse voltage is applied.

FIG. 4 is a diagram showing a semiconductor device according to another embodiment.

FIG. 5 is a diagram showing a semiconductor device according to another embodiment.

[Explanation of symbols]

DESCRIPTION OF SYMBOLS 1 Semiconductor element 10 Silicon substrate 11 N ^{+ type} silicon layer 12 N type silicon region 13 Anode electrode 14 Cathode electrode 15, 15a P ^{+ type} silicon region 16 Insulating film 16a Opening 30 Depletion layer

Claims (4)

[Claims] A semiconductor substrate of a first conductivity type; a first semiconductor region of a first conductivity type formed in a surface region of the semiconductor substrate and having an impurity concentration different from that of the semiconductor substrate; A metal layer provided to form a Schottky junction with the first semiconductor region; and a surface region of the first semiconductor region formed to be in contact with the metal layer to form a PN junction with the first semiconductor region. A second semiconductor region of a second conductivity type, and a peripheral region of a region of the first semiconductor region that is in contact with the metal layer, formed on a surface region that is not in contact with the metal layer so as to surround the second semiconductor region. A third semiconductor region of a second conductivity type forming a PN junction with the first semiconductor region;
A PN junction formed by the first semiconductor region, the second semiconductor region, and the third semiconductor region forms a substantially integrated depletion layer when a reverse voltage is applied. A semiconductor element characterized by the above-mentioned. 2. The semiconductor device according to claim 1, wherein said third semiconductor region is formed in an island shape so as to be exposed at a plurality of equal intervals. 3. The semiconductor device according to claim 1, wherein said second semiconductor region and said third semiconductor region are formed with substantially the same impurity concentration and diffusion depth. 4. The semiconductor device according to claim 1, wherein said third semiconductor region is formed so as to be shallower than said second semiconductor region.