JP3489567B2 - Semiconductor element - Google Patents

Abstract

PROBLEM TO BE SOLVED: To reduce leak current while ensuring a high current capacity in a semiconductor element where Schottky barrier and the rectifying part of a PN junction are arranged contiguously to each other. SOLUTION: A plurality of insular P+ type silicon regions 15 are formed in the surface region of an N type silicon region 12. An anode electrode 13 is provided above the P+ type silicon region 15 through an insulation film 16 having an opening 16a. Outermost circumferential P+ type silicon region 15a in the vicinity of the opening 16a is arranged not to touch the anode electrode 13. Furthermore, the P+ type silicon region 15a is arranged to form a substantially integrated depletion layer upon application of a reverse voltage.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor element having a rectifying function, and more particularly to a semiconductor element in which a rectifying section of a Schottky barrier and a rectifying section of a PN junction are adjacent to each other.

[0002]

2. Description of the Related Art A semiconductor element used for a rectifier or the like, for example, a switching element is required to have high switching speed and forward and reverse characteristics. As such a semiconductor rectifying element, a PN junction diode using a PN junction and a Schottky diode using a Schottky junction are widely used.

The PN junction diode has a high reverse characteristic such as a small leakage current when a reverse voltage is applied and a high breakdown voltage. However, the PN junction diode has a slow switching speed and is not suitable for use in a high speed circuit. As a means for improving the switching speed, there is a method of diffusing a heavy metal such as gold or platinum. However, while the switching speed is improved, the reverse leakage current is increased and the forward voltage drop is increased.

Schottky diodes have high switching characteristics such as high switching speed. However, the Schottky diode has a low reverse characteristic, and there is a problem particularly when it is used in a high-voltage, large-current circuit. For example, the resistance against the overvoltage in the reverse direction (surge withstand amount) is low, and when a reverse voltage near the breakdown voltage is applied, the leakage current flowing over the Schottky barrier rapidly increases, and the element is likely to be destroyed.

As a semiconductor device having the characteristics of the above-mentioned PN junction diode and Schottky diode, a semiconductor device disclosed in Japanese Patent Publication No. 59-35183 is known. The semiconductor device disclosed above has a configuration in which the rectifying section of the Schottky barrier and the rectifying section of the PN junction are arranged adjacent to each other.

In the above semiconductor device, the rectifying portion of the Schottky barrier and the rectifying portion of the PN junction are alternately and adjacently arranged near the interface between the electrode (Schottky metal) and the semiconductor layer when viewed in cross section. Have. According to the above configuration, during forward operation, a current flows through the Schottky barrier, so that high switching characteristics similar to those of a Schottky diode can be obtained. In the reverse operation, the Schottky junction region is filled with the depletion layer formed by the PN junction, and the leakage current from the Schottky junction region can be suppressed. Therefore, good reverse voltage characteristics (surge withstand) can be obtained.

However, in the above semiconductor device, when a reverse voltage is applied, a region in which a rectifying portion formed by a Schottky junction and a junction portion formed by a PN junction are arranged adjacent to each other (hereinafter referred to as "rectifying composite region"). The leakage current easily flows at the peripheral edge of ().

As a means for preventing leakage current, a method is known in which an annular guard ring region is formed so as to be adjacent to and surround the outer periphery of the rectifying composite region. The guard ring region is formed as a PN junction region and is provided in contact with the electrode. That is, the outer periphery of the rectifying composite area is PN
The junction is terminated, and a boundary portion between the insulating film and the electrode is formed on the surface of the diffusion region forming the PN junction at the termination. The guard ring region surrounding the rectification composite region effectively blocks the leakage current from the peripheral end portion by the depletion layer spreading around the guard ring region when the reverse voltage is applied.

[0009]

In the structure including the guard ring region, when a small current or a medium current is passed,
The forward current mainly flows through the Schottky junction. Therefore, the guard ring region becomes a region that is substantially inactive during forward operation, and the formation of the guard ring region reduces the substantial current capacity of the device. As described above, the conventional semiconductor element having the structure in which the Schottky junction and the PN junction are adjacent to each other cannot secure the high current capacity and effectively prevent the leakage current.

In view of the above circumstances, it is an object of the present invention to provide a highly reliable semiconductor device. It is another object of the present invention to provide a semiconductor element in which a Schottky barrier and a rectifying portion of a PN junction are arranged adjacent to each other, and a leakage current can be reduced while ensuring a high current capacity.

In order to achieve the above object, a semiconductor device of the present invention comprises a semiconductor substrate of a first conductivity type and a first conductivity type semiconductor substrate formed in a surface region of the semiconductor substrate and having an impurity concentration different from that of the semiconductor substrate. A first semiconductor region, a metal layer provided on the first semiconductor region and forming a Schottky junction with the first semiconductor region, and a surface region of the first semiconductor region formed in contact with the metal layer. A second semiconductor region of a second conductivity type that forms a PN junction with the first semiconductor region, and a peripheral surface region of the first semiconductor region in contact with the metal layer, the surface region not in contact with the metal layer, A third semiconductor region of a second conductivity type formed so as to surround the second semiconductor region and forming a PN junction with the first semiconductor region, the first semiconductor region and the second semiconductor region. And the third The PN junction formed by the semiconductor region forms a substantially integrated depletion layer when a reverse voltage is applied, and a contact surface between the metal layer and the first semiconductor region is formed.
A Schottky barrier is formed in a ring shape on the outer peripheral edge of .

According to the above structure, the Schottky junction and the PN
By having a configuration in which the junction and the adjacent are arranged,
A semiconductor device having a low forward voltage drop, a low leakage current, and a high surge resistance can be obtained. Further, according to the above configuration, the third semiconductor region not in contact with the metal layer, the second semiconductor region adjacent to the third semiconductor region, and the first semiconductor region are provided in the peripheral portion of the region in contact with the metal layer of the first semiconductor region. Due to the PN junction formed by, the depletion layer integrated with the peripheral portion is formed when a reverse voltage is applied. Therefore, the leakage current can be reduced without providing a guard ring or the like on the peripheral portion. Furthermore, since the Schottky junction is formed by the metal layer and the first semiconductor region without providing a guard ring or the like on the peripheral portion, energization of the peripheral portion at the time of applying a forward voltage is ensured, and substantially. High current capacity can be obtained.

In the above structure, for example, the third semiconductor regions are formed so as to be exposed in a plurality of islands at equal intervals. Thereby, when a reverse voltage is applied, the third semiconductor region and the second semiconductor can form a uniform depletion layer.

In the above structure, for example, the second semiconductor region and the third semiconductor region are formed with substantially the same impurity concentration and diffusion depth. That is, the second semiconductor region and the third semiconductor region can be formed in the same process. Therefore, it is possible to manufacture a semiconductor device at a low manufacturing cost.

In the above structure, the third semiconductor region may be formed so as to be shallower than the second semiconductor region.

[0016]

BEST MODE FOR CARRYING OUT THE INVENTION A semiconductor device according to an embodiment of the present invention will be described below with reference to the drawings. Figure 1
Shows a cross-sectional view of the semiconductor element according to the present embodiment,
FIG. 2 shows a plan view of the semiconductor device of FIG. The semiconductor element described below functions as a diode having a Schottky junction and a PN junction.

As shown in FIG. 1, the semiconductor device 1 of the present embodiment has an N ^{+ type} silicon layer 11 and an N type silicon region 12 formed on a silicon substrate 10 made of silicon single crystal, and a silicon substrate 10. It is composed of an anode electrode 13 and a cathode electrode 14 provided on the front and back surfaces.

The N ^{+ type} silicon layer 11 is formed on the silicon substrate 1.
Configures 0. The impurity concentration of the N ^{+ type} silicon layer 11 is, for example, about 1.5 × 10 ¹⁹ cm ⁻³ . N
The silicon region 12 is formed on the N ⁺ silicon layer 11 by epitaxial growth. The N-type silicon region 12 has, for example, an impurity concentration of about 1.0 × 10 ¹⁶ cm ⁻³ . The thickness is 2 μm to 15 μm.
It is about m. At this time, the specific resistance of the N-type silicon region 12 is about 0.5 Ωcm to 5 Ωcm.

On the surface of the N-type silicon region 12, P⁺form
A silicon region 15 is formed. P⁺Shaped silicon area
Region 15 is enclosed in N-type silicon region 12 leaving its surface.
Surrounded by a plurality of islands in the surface region of the N-type silicon region 12.
It is formed at equal intervals. P ⁺The shaped silicon region 15 is
For example, 1.0 × 10¹⁶cm^-3~ 1.0 x 10^{1 9}
cm^-3Impurity concentration of about 0.5 μm
It has a diffusion depth of about 10 μm.

The P ^{+ type} silicon region 15 forms a PN junction with the N type silicon region 12. This gives P
A rectifying portion formed by a PN junction is formed between the ^{+ type} silicon region 15 and the N type silicon region 12, and the semiconductor element 1 has P
It has a function as an N-junction diode.

FIG. 2 shows a plan view of the semiconductor device 1 shown in FIG. As shown in FIG. 2, a plurality of square P ⁺ -type silicon regions 15 are exposed in a lattice pattern on the surface of the silicon substrate 10. Therefore, the surface of the silicon substrate 10 has a structure in which the N-type silicon regions 12 are exposed in a mesh shape between the P ⁺ -type silicon regions 15 exposed in an island shape. Where P
The distance between the ^{+ type} silicon regions 15 is 0.5 μ, for example.
It is about m to 3 μm.

Returning to FIG. 1, an insulating film 16 is arranged on the upper surface of the silicon substrate 10. The insulating film 16 is made of a silicon oxide film or the like and has an opening 16a. In addition, as shown in FIG. 2, when viewed from above, the insulating film 16
16a surrounds the plurality of P ⁺ -type silicon regions 15 and has the outermost periphery of the P ⁺ -type silicon regions 1.
It is configured to be inside 5a.

Returning to FIG. 1, the anode electrode 13 is provided on the upper surface of the insulating film 16. The anode electrode 13 is
It is made of metal such as palladium and functions as an anode electrode of the semiconductor element 1 as a diode. Further, the anode electrode 13 is in contact with the N-type silicon region 12 exposed inside the opening 16a through the opening 16a of the insulating film 16. The anode electrode 13 contacts the N-type silicon region 12 and forms a Schottky junction with the N-type silicon region 12. As a result, a rectifying portion by Schottky junction is formed between the anode electrode 13 and the N-type silicon region 12, and the semiconductor element 1 has a function as a Schottky diode.

As described above, the Schottky junction and the PN junction formed by the anode electrode 13, the N-type silicon region 12, and the P ⁺ -type silicon region 15 are formed on the main surface of the silicon substrate 10 on the anode side. A rectifying composite region composed of composite is formed. In the rectification composite region, the rectification part by the PN junction and the rectification part by the Schottky junction are alternately adjacent to each other. With the above configuration, characteristics of the Schottky diode and the PN junction diode, that is, low forward voltage drop and reverse breakdown voltage can be obtained.

The distance between the P ^{+ type} silicon regions 15 is, for example, about 0.5 μm to 3 μm. As a result, when a reverse voltage is applied to the semiconductor element 1,
As shown in FIG. 3, island-shaped P ⁺ -type silicon regions 15 and N
The depletion layer 30 formed by the PN junction with the silicon region 12 is connected to each other and is substantially integrated, and is in a so-called pinch-off state. Thereby, the electric field intensity applied to the Schottky barrier formed between the N-type silicon region 12 and the anode electrode 13 is reduced, and the leakage current is reduced.

Here, the P ^{+ -type} silicon region 15a at the outermost periphery of the P ⁺ -type silicon region 15 is the anode electrode 13.
It is placed in a position where it does not touch. However, the outermost P
^When the reverse voltage is applied, the ^{+ -type} silicon region 15a receives another P
A depletion layer 30 integrated with the ^{+ type} silicon region 15 is formed. Therefore, not formed the P ⁺ silicon region 15, the periphery of the contact area between the anode electrode 13 of the N-type silicon region 12 also, as shown in FIG. 3, it is formed from the outermost P ⁺ form silicon regions 15a It is covered by the depletion layer 30. Thereby, the leakage current at the end of the anode electrode 13 when the reverse breakdown voltage is applied is also effectively blocked without providing a guard ring or the like.

Further, the anode of the N-type silicon region 12
P on the periphery of the contact area with the electrode 13 ⁺Silicon region 1
5 does not exist, and the anode electrode 13 is N-type
Direct contact with the con region 12. As a result,
Schottky junction is formed even when the forward voltage is applied.
Is capable of energizing the peripheral portion even when a small current or medium current is applied.
And a high current capacity can be obtained.

A cathode electrode 14 is provided on the lower surface of the silicon substrate 10 and is in low resistance contact with the N ^{+ type} silicon layer 11. The cathode electrode 14 is made of nickel, for example. Here, the N ^{+ type} silicon layer 11 and the N type silicon region 12 function as the cathode region of the diode.

As described above, in the semiconductor device of the present embodiment, the P ⁺ -type silicon region 15 is formed on the inner peripheral side of the N-type silicon region 12 which is in contact with the anode electrode 13 and the anode electrode is formed. An outermost P ⁺ -type silicon region 15a is arranged and formed at a position where it does not contact 13. In addition, the adjacent P ^{+ type} silicon region 1
The interval of 5 is such that, when a reverse breakdown voltage is applied, the depletion layers 30 extending from the PN junction formed by the P ⁺ -type silicon region 15 including the outermost peripheral P ⁺ -type silicon region 15a are continuous with each other.

Therefore, a low leakage current and a high surge withstanding voltage when a reverse voltage is applied can be obtained without providing a guard ring or the like on the peripheral portion of the contact region of the N-type silicon region 12 with the anode electrode 13. Therefore, the highly reliable semiconductor element 1 can be obtained. Further, the outer peripheral edge of the anode electrode 13 is in contact with the N-type silicon region 12, and the Schottky junction in which the forward current mainly flows is formed also in the peripheral portion of the contact region, so that a high current capacity can be obtained.

Of course, the semiconductor device 1 having the above-mentioned structure employs an element structure in which the rectifying portion of the Schottky barrier and the rectifying portion of the PN junction are arranged adjacent to each other, so that the advantages of both the Schottky diode and the PN junction diode are obtained. Is,
A low forward voltage drop and a high reverse breakdown voltage can be obtained.

The present invention is not limited to the above embodiment, but various modifications and applications are possible. Hereinafter, modifications of the above-described embodiment applicable to the present invention will be described.

In the above embodiment, the N-type silicon region 1 is used.
Although the anode electrode 13 forming the Schottky junction with 2 is made of palladium, the invention is not limited to this.
If it functions as a Schottky metal such as chromium, titanium, molybdenum, tungsten, aluminum,
Any metal is possible.

In the above embodiment, the P ^{+ type} silicon regions 15 are scattered in the N type silicon regions 12 in an island shape. However, a configuration in which the P ^{+ -type} silicon region 15 is formed in a stripe shape on the N-type silicon region 12 is also possible.
On the contrary, a configuration in which the N-type silicon region 12 is exposed in an island shape is also possible. Furthermore, the P ^{+ type} silicon region 15
The plane shape of 2 may be a circle, a polygon, or the like instead of a square.

In the above embodiment, the outermost P ^{+ type} silicon region 15a is formed in the same impurity diffusion step as the other P ^{+ type} silicon regions 15 and has substantially the same impurity concentration and diffusion depth. . However, the P ^{+ -type} silicon region 15a at the outermost periphery may be formed in a separate process, for example, the impurity concentration may be higher and shallower than that at the inner periphery side. Also, regarding the distance between the P ^{+ type} silicon regions 15,
The distance between the outermost P ^{+ -type} silicon region 15a and the innermost one may be changed. Furthermore, the outermost P
^The shapes of the ^{+ type} silicon region 15a and the P ^{+ type} silicon region 15 on the inner peripheral side may be changed. At this time, for example, as shown in FIG. 4, the outermost P ⁺ -type silicon region 15a is formed in a ring shape, and the inner peripheral P ⁺ -type silicon region 15 is formed in an island shape, a ring shape, or a stripe shape. Good.

In the above embodiment, the N-type silicon region 1 is used.
The P ⁺ -type silicon region 15 was not formed in the peripheral portion of the contact region 2 with the anode electrode 13, so that the anode electrode 13 was not completely intersected with the P ⁺ -type silicon region 15 in the peripheral portion. However, as shown in FIG. 5, the innermost P ⁺ -type silicon region 15 adjacent to the outermost P ⁺ -type silicon region 15 a may partially contact the anode electrode 13.

In the above embodiment, the N-type silicon layer 12 is used.
The P-type diffusion region is formed on the top. However, the configuration is not limited to this, and the N-type diffusion region may be formed on the P-type silicon layer.

[0038]

As described above, according to the present invention,
A highly reliable semiconductor device is provided.

[Brief description of drawings]

FIG. 1 is a sectional view of a semiconductor device according to an embodiment of the present invention.

FIG. 2 is a plan view of a semiconductor device according to an embodiment of the present invention.

FIG. 3 is a cross-sectional view of a semiconductor device when a reverse voltage is applied.

FIG. 4 is a diagram showing a semiconductor device of another embodiment.

FIG. 5 is a diagram showing a semiconductor device according to another embodiment.

[Explanation of symbols]

1 semiconductor element 10 silicon substrate 11 N ^{+ type} silicon layer 12 N type silicon region 13 anode electrode 14 cathode electrodes 15, 15a P ^{+ type} silicon region 16 insulating film 16a opening 30 depletion layer

─────────────────────────────────────────────────── ─── Continuation of front page (58) Fields surveyed (Int.Cl. ⁷ , DB name) H01L 29/47 H01L 29/861 H01L 29/872

Claims (3)

(57) [Claims] And 1. A first conductivity type semiconductor substrate, wherein formed on the surface region of the semiconductor substrate, said semiconductor substrate and an impurity concentration different first semiconductor region of a first conductivity type, said first semiconductor region A metal layer provided to form a Schottky junction with the first semiconductor region; and a surface region of the first semiconductor region formed in contact with the metal layer to form a PN junction with the first semiconductor region. A second semiconductor region of the second conductivity type and a peripheral region of a region of the first semiconductor region that contacts the metal layer are formed so as to surround the second semiconductor region in a surface region that does not contact the metal layer. A third semiconductor region of a second conductivity type forming a PN junction with the first semiconductor region,
A PN junction formed by the first semiconductor region and the second semiconductor region and the third semiconductor region forms an integrated depletion layer when a reverse voltage is applied, and A semiconductor device, wherein a shot barrier is formed in a ring shape on an outer peripheral edge of a contact surface with the first semiconductor region. 2. The semiconductor device according to claim 1, wherein the third semiconductor regions are formed so as to be exposed in a plurality of islands at equal intervals. 3. A semiconductor substrate of a first conductivity type, a first semiconductor region of a first conductivity type formed in a surface region of the semiconductor substrate and having an impurity concentration different from that of the semiconductor substrate, and on the first semiconductor region. A metal layer provided to form a Schottky junction with the first semiconductor region; and a surface region of the first semiconductor region formed in contact with the metal layer to form a PN junction with the first semiconductor region. A second semiconductor region of the second conductivity type and a peripheral region of a region of the first semiconductor region that contacts the metal layer are formed so as to surround the second semiconductor region in a surface region that does not contact the metal layer. A third semiconductor region of a second conductivity type forming a PN junction with the first semiconductor region,
A PN junction formed by the first semiconductor region and the second semiconductor region and the third semiconductor region forms an integrated depletion layer when a reverse voltage is applied, The semiconductor element is characterized in that the regions are formed so as to be exposed in a plurality of islands at equal intervals.