JP2018170335A - Method of manufacturing semiconductor device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a technique of restoring deterioration of crystallinity in an ion implantation region.SOLUTION: A method of manufacturing a semiconductor device includes: an ion implantation step of ion implanting a p-type impurity into an n-type semiconductor layer containing an n-type impurity with an integrated dose amount D; and a heat treatment step of performing heat treatment to an ion implantation region into which the p-type impurity is ion-implanted at a temperature T over a time t under an atmosphere containing nitrogen. The integrated dose amount D, the temperature T, and the time t satisfy a predetermined relationship.SELECTED DRAWING: Figure 2

Description

  The present invention relates to a method for manufacturing a semiconductor device.

  Conventionally, a technique for forming a p-type semiconductor region by ion implantation in a group III nitride semiconductor such as gallium nitride (GaN) is known. In Patent Documents 1 to 3, as a method for forming a p-type semiconductor region, a method is described in which after a p-type impurity is ion-implanted into a semiconductor layer, a heat treatment is performed to recover the crystallinity in the ion-implanted region. ing.

JP 2004-356257 A Japanese Patent Laid-Open No. 2006-181580 Japanese Patent No. 5358955

  However, generally, the crystallinity deterioration due to ion implantation is severe, and the conventional method may not sufficiently recover the crystallinity deterioration in the ion implantation region even after the heat treatment. Further, when the deterioration of crystallinity in the ion implantation region is not sufficiently recovered, there is a problem that the leakage current of the semiconductor device increases. For this reason, a method for sufficiently recovering the deterioration of crystallinity in the ion implantation region has been desired.

  SUMMARY An advantage of some aspects of the invention is to solve at least a part of the problems described above, and the invention can be implemented as the following forms.

(1) According to an aspect of the present invention, a method for manufacturing a semiconductor device is provided. This method of manufacturing a semiconductor device includes an ion implantation step of ion-implanting p-type impurities into an n-type semiconductor layer containing n-type impurities with an integrated dose amount D, and an ion implantation region in which the p-type impurities are ion-implanted. A heat treatment step of performing heat treatment at a temperature T and a time t in an atmosphere containing nitrogen, and the integrated dose amount D, the temperature T, and the time t satisfy the following formula (1): . According to the method for manufacturing a semiconductor device of this aspect, it is possible to recover the deterioration of crystallinity in the ion implantation region.

(2) In the manufacturing method described above, in the ion implantation step, the p-type impurity may include at least one selected from the group consisting of magnesium, beryllium, and calcium.

(3) In the manufacturing method described above, the implantation temperature in the ion implantation step may be 20 ° C. or higher and 900 ° C. or lower.

(4) In the above manufacturing method, the implantation angle in the ion implantation step may be 0 ° or more and 15 ° or less.

(5) In the above manufacturing method, at least one selected from the group consisting of nitrogen, ammonia, and hydrazine may be used as a nitrogen source in the heat treatment step.

(6) In the above manufacturing method, the pressure in the heat treatment step may be 10 kPa or more and 110 kPa or less.

  The present invention can also be realized in various forms other than the semiconductor device manufacturing method. For example, it can be realized in the form of a semiconductor device manufactured using the above-described manufacturing method, or an apparatus for manufacturing a semiconductor device using the above-described manufacturing method.

  According to the method for manufacturing a semiconductor device of the present invention, the deterioration of crystallinity in the ion implantation region can be recovered.

FIG. 3 is a cross-sectional view schematically showing the configuration of the semiconductor device according to the first embodiment. Process drawing which shows the manufacturing method of the semiconductor device in 1st Embodiment. The schematic diagram which shows the state after a cap layer was formed. The figure which shows the result of an evaluation test. The figure which shows the relationship between the time in a heat processing process, and a half value width. The figure which shows the relationship between the time in a heat processing process, and a half value width. The figure which shows the relationship between the temperature in a heat processing process, and the time in a heat processing process. The figure which shows the relationship between the integrated dose amount to a p-type semiconductor region, and hole concentration. Sectional drawing which shows the structure of the semiconductor device in 2nd Embodiment typically. Sectional drawing which shows the structure of the semiconductor device in 3rd Embodiment typically.

A. First embodiment A-1. Configuration of Semiconductor Device FIG. 1 is a cross-sectional view schematically showing a configuration of a semiconductor device 100 in the first embodiment. FIG. 1 shows XYZ axes orthogonal to each other. Of the XYZ axes in FIG. 1, the X axis is an axis from the left side to the right side in FIG. The + X-axis direction is a direction toward the right side of the paper, and the -X-axis direction is a direction toward the left side of the paper. Of the XYZ axes in FIG. 1, the Y axis is an axis that extends from the front side of the paper in FIG. 1 toward the back of the paper. The + Y-axis direction is a direction toward the back of the sheet, and the -Y-axis direction is a direction toward the front of the sheet. Of the XYZ axes in FIG. 1, the Z axis is an axis that extends from the bottom of FIG. 1 to the top of the page. The + Z-axis direction is a direction toward the paper surface, and the -Z-axis direction is a direction toward the paper surface. The XYZ axes in FIG. 1 correspond to the XYZ axes in the other drawings.

  In the present embodiment, the semiconductor device 100 is a GaN-based semiconductor device formed using gallium nitride (GaN). In the present embodiment, the semiconductor device 100 is a vertical pn junction diode. In the present embodiment, the semiconductor device 100 is used for power control.

  The semiconductor device 100 includes a substrate 110, an n-type semiconductor layer 112, and a p-type semiconductor region 113. The semiconductor device 100 has a recess 124 as a structure formed in these semiconductor layers. The semiconductor device 100 further includes an insulating film 130, an anode electrode 142, and a cathode electrode 144.

  The substrate 110, the n-type semiconductor layer 112, and the p-type semiconductor region 113 of the semiconductor device 100 are plate-like semiconductors that extend along the X axis and the Y axis. In the present embodiment, the substrate 110, the n-type semiconductor layer 112, and the p-type semiconductor region 113 are formed of a group III nitride semiconductor. Examples of the group III nitride semiconductor include gallium nitride (GaN), aluminum nitride (AlN), aluminum gallium nitride (AlGaN), indium gallium nitride (InGaN), and indium aluminum gallium nitride (InAlGaN). From the viewpoint of use in a power control semiconductor device, the group III nitride semiconductor is preferably gallium nitride (GaN) or aluminum gallium nitride (AlGaN). In the present embodiment, gallium nitride (GaN) is used as the group III nitride semiconductor. It should be noted that a part of gallium nitride (GaN) may be replaced with another group III element such as aluminum (Al) or indium (In) within the range where the effect of the present embodiment is obtained, and other impurities may be included. May be.

The substrate 110 of the semiconductor device 100 is a semiconductor having n-type characteristics. In the present embodiment, the silicon (Si) concentration contained in the substrate 110 is 1 × 10 ¹⁸ cm ⁻³ or more. In the present embodiment, the thickness of the substrate 110 (the length in the Z-axis direction) is not less than 100 μm and not more than 500 μm.

The n-type semiconductor layer 112 of the semiconductor device 100 is a semiconductor having n-type characteristics. In the present embodiment, the n-type semiconductor layer 112 is located on the + Z axis direction side of the substrate 110. In the present embodiment, the silicon (Si) concentration contained in the n-type semiconductor layer 112 is 1 × 10 ¹⁶ cm ⁻³ . In the present embodiment, the n-type semiconductor layer 112 has a thickness (length in the Z-axis direction) of 10 μm or more and 20 μm or less.

The p-type semiconductor region 113 of the semiconductor device 100 is a region formed by ion implantation with respect to the surface (surface on the + Z-axis direction side) of the n-type semiconductor layer 112. The p-type semiconductor region 113 is also referred to as an ion implantation region 113. The semiconductor in the p-type semiconductor region 113 has p-type characteristics. In the present embodiment, the p-type semiconductor region 113 contains magnesium (Mg) as an acceptor element (p-type impurity). In the present embodiment, the concentration of magnesium (Mg) in the p-type semiconductor region 113 is 1 × 10 ¹⁸ cm ⁻³ or more and 5 × 10 ¹⁹ cm ⁻³ or less. In the present embodiment, the thickness (the length in the Z-axis direction) of the p-type semiconductor region 113 is not less than 0.1 μm and not more than 1.0 μm.

  In the p-type semiconductor region 113, the half-value width of the diffraction peak on the (0002) plane in the omega (ω) angle scan by X-ray diffraction measurement is 100 arcsec or less, preferably 60 arcsec or less.

  The recess 124 of the semiconductor device 100 is a groove that penetrates the p-type semiconductor region 113 from the surface (the surface on the + Z-axis direction side) of the p-type semiconductor region 113 and falls to the n-type semiconductor layer 112. In the present embodiment, the recess 124 is formed by dry etching on the p-type semiconductor region 113 and the n-type semiconductor layer 112. Due to the recess 124, the p-type semiconductor region 113 has a plate-like shape having a surface and side surfaces.

  The anode electrode 142 of the semiconductor device 100 is formed on the p-type semiconductor region 113. The anode electrode 142 is an electrode that is in ohmic contact with the p-type semiconductor region 113. In the present embodiment, the anode electrode 142 is an electrode formed by applying a heat treatment to a layer formed from palladium (Pd).

The insulating film 130 of the semiconductor device 100 is a film that is formed on the n-type semiconductor layer 112 and the anode electrode 142 and has electrical insulation. In the present embodiment, the insulating film 130 is in contact with the surface of the n-type semiconductor layer 112 and a part of the surface of the anode electrode 142, and is in contact with the side surface of the p-type semiconductor region 113 and the side surface of the anode electrode 142. In the present embodiment, the insulating film 130 is made of silicon dioxide (SiO ₂ ).

  The cathode electrode 144 of the semiconductor device 100 is an electrode that is in ohmic contact with the back surface of the substrate 110 on the −Z axis direction side. In the present embodiment, the cathode electrode 144 is an electrode formed by laminating a layer formed of aluminum (Al) on a layer formed of titanium (Ti) and then applying heat treatment.

A-2. Manufacturing Method of Semiconductor Device FIG. 2 is a process diagram showing a manufacturing method of the semiconductor device 100 according to the first embodiment. First, in step P101, the manufacturer prepares the substrate 110, and then continuously forms the n-type semiconductor layer 112 and the through film on the substrate 110 in this order. The through film is used to adjust the concentration distribution of the p-type impurity implanted into the n-type semiconductor layer 112 in an ion implantation process described later. The n-type semiconductor layer 112 and the through film are formed by metal organic chemical vapor deposition (MOCVD). By forming the n-type semiconductor layer 112 and the through film continuously, impurity contamination between the n-type semiconductor layer 112 and the through film can be prevented. The through film is formed of an element that does not contain an element serving as a donor in a group III nitride semiconductor. By doing so, it is possible to prevent the component elements of the through film from being implanted into the n-type semiconductor layer 112 in the ion implantation step described later. In the present embodiment, the through film is formed from amorphous aluminum nitride (AlN), and the thickness of the through film is 30 nm.

ここで、Ｔは、後述する熱処理工程における温度（℃）であり、ｔは、熱処理工程における時間（分）である。例えば、まず、温度Ｔを１２５０℃と設定し、時間ｔを０．１分（６秒）と設定した場合、（１）式の右辺は４．６×１０^１４となる。このため、温度Tが１２５０℃であり、時間ｔが０．１分（６秒）である場合、積算ドーズ量Ｄは４．６×１０^１４ｃｍ^−２以下となる。これとは反対に、まず、所望のホール濃度から必要な積算ドーズ量Ｄを設定した後、（１）式を満たすように温度Ｔと時間ｔとを設定してもよい。 Next, in step P103, the manufacturer ion-implants the p-type impurity into the n-type semiconductor layer 112 containing the n-type impurity with an integrated dose D (cm ⁻² ) that satisfies the following formula (1). Note that the process P103 is also referred to as an ion implantation process.

Here, T is a temperature (° C.) in a heat treatment step to be described later, and t is a time (minute) in the heat treatment step. For example, when the temperature T is set to 1250 ° C. and the time t is set to 0.1 minute (6 seconds), the right side of the expression (1) is 4.6 × 10 ¹⁴ . For this reason, when the temperature T is 1250 ° C. and the time t is 0.1 minute (6 seconds), the integrated dose amount D is 4.6 × 10 ¹⁴ cm ⁻² or less. On the contrary, first, after setting the necessary integrated dose D from the desired hole concentration, the temperature T and the time t may be set so as to satisfy the equation (1).

  The manufacturer controls the amount of p-type impurity implanted in the ion implantation process by the integrated dose amount. The smaller the integrated dose, the smaller the half-value width of the diffraction peak on the (0002) plane in the omega (ω) angle scan by X-ray diffraction measurement. That is, the smaller the integrated dose, the smaller the crystal defects in the ion implantation region 113 due to ion implantation.

  The p-type impurity used for ion implantation preferably includes at least one selected from the group consisting of magnesium (Mg), beryllium (Be), and calcium (Ca). In this embodiment, magnesium (Mg) is used as the p-type impurity. A part of the n-type semiconductor layer 112 on the surface side (the surface on the + Z-axis direction side), which is a region into which p-type impurities are implanted, becomes a p-type semiconductor region 113 through heat treatment described later.

The integrated dose is preferably 1.0 × 10 ¹⁴ cm ⁻² or more and 1.0 × 10 ¹⁵ cm ⁻² or less. In the present embodiment, the integrated dose amount is 1.0 × 10 ¹⁴ cm ⁻² . The implantation temperature in the ion implantation step is preferably 20 ° C. or higher and 900 ° C. or lower. The implantation angle in the ion implantation step is preferably 0 ° or more and 15 ° or less.

  By performing ion implantation on the n-type semiconductor layer 112 with the through film formed, the distribution of the concentration of the p-type impurity implanted into the n-type semiconductor layer 112 can be adjusted appropriately. In the ion-implanted region, the concentration distribution of the implanted impurities is a distribution obtained by adding two or more normal distributions in the depth direction (Z-axis direction). Here, the concentration distribution being a normal distribution means that the concentration of the implanted impurity is highest at a position at a predetermined distance from the exposed surface in the depth direction (Z-axis direction), It means that the concentration of impurities decreases as the distance from the surface to the front surface and back surface increases. Ion implantation is performed with a through film designed to have the highest magnesium atom (Mg) concentration at a predetermined position in the n-type semiconductor layer 112 near the surface of the n-type semiconductor layer 112. Thus, the impurity concentration peak can be set near the surface of the n-type semiconductor layer 112.

  In Step P105, the manufacturer forms a cap layer on the through film.

  FIG. 3 is a schematic diagram showing a state after the cap layer is formed. In FIG. 3, the cap layer 154 formed on the through film 152 is formed of amorphous aluminum nitride (AlN) in this embodiment. In this embodiment, the cap layer 154 is formed by metal organic chemical vapor deposition (MOCVD), but may be formed by sputtering.

  The through film 152 and the cap layer 154 are a coating layer 150 that covers the ion implantation region 113 in a heat treatment process to be described later. In the present embodiment, the coating layer 150 is made of amorphous aluminum nitride (AlN). In the present embodiment, the thickness of the cap layer 154 is 1 nm or more and 1000 nm or less. The cap layer 154 may be formed of, for example, (i) aluminum gallium nitride (AlGaN), and (ii) a layer of aluminum nitride (AlN) and a layer of aluminum gallium nitride (AlGaN) by sputtering. You may use what laminated | stacked these in this order.

  Next, in step P107 (see FIG. 2), the manufacturer heat-treats the ion-implanted region 113 into which the p-type impurity is ion-implanted in an atmosphere containing nitrogen (N). Process P107 is also referred to as a heat treatment process. In the state shown in FIG. 3, a heat treatment step is performed. In this embodiment, the heat treatment is performed in a state where the p-type semiconductor region 113 is covered, but the heat treatment may be performed in a state where the p-type semiconductor region 113 is exposed.

  The temperature T in the heat treatment step is a temperature that satisfies the above-described expression (1). The temperature T in the heat treatment step is preferably 800 ° C. or higher and 1500 ° C. or lower. In the present embodiment, the temperature T in the heat treatment step is 1250 ° C. The time t in the heat treatment step is preferably 1 second or more and 10 minutes or less, and more preferably 1 second or more and less than 1 minute. In the present embodiment, the time t in the heat treatment step is 30 seconds (0.5 minutes). The pressure in the heat treatment step is preferably 10 kPa or more and 110 kPa or less. In the present embodiment, the pressure in the heat treatment step is 100 kPa.

Moreover, it is preferable to use at least one selected from the group consisting of nitrogen (N ₂ ), ammonia (NH ₃ ), and hydrazine (N ₂ H ₄ ) as the nitrogen source in the heat treatment step. Through the heat treatment step, the p-type impurity in the ion implantation region 113 is activated and a high hole concentration is obtained.

  Next, in Step P109 (see FIG. 2), the manufacturer removes the covering layer 150. In this embodiment, the manufacturer performs wet etching using tetramethylammonium hydroxide (TMAH) having a temperature of 65 ° C. or higher and 85 ° C. or lower and a pH of 12. Note that dry etching may be used instead of wet etching.

  In step P111, the manufacturer forms the recess 124 by dry etching. Thereafter, in step P113, the manufacturer forms an electrode on the ion implantation region 113 by at least one of a vapor deposition method and a sputtering method. In this embodiment, the manufacturer forms the anode electrode 142 and the cathode electrode 144 on the ion implantation region 113 by vapor deposition.

In Step P115, the manufacturer uses silicon dioxide (SiO ₂ ) on the n-type semiconductor layer 112 and the anode electrode 142 by at least one of a sputtering method and an atomic layer deposition method (ALD: Atomic Layer Deposition). Then, an insulating film 130 is formed from at least one selected from the group consisting of aluminum oxide (Al ₂ O ₃ ) and silicon nitride (Si ₃ N ₄ ). In the present embodiment, the manufacturer forms the insulating film 130 from silicon dioxide (SiO ₂ ) by atomic layer deposition. Through these steps, the semiconductor device 100 is completed.

A-3. Effects According to the manufacturing method of the first embodiment described above, the ion implantation step (step P103) and the heat treatment step (step P107) are provided, the integrated dose amount D (cm ⁻² ), and the temperature in the heat treatment step When T (° C.) and the time (minutes) in the heat treatment step satisfy the following expression (1), the deterioration of crystallinity in the ion implantation region can be recovered. The result of the evaluation test which confirms that such an effect is acquired is shown.

A-4. Test result A-4-1. First Test Result FIG. 4 is a diagram showing the result of the evaluation test. The tester found that the half-width of the GaN (0002) diffraction peak (hereinafter also simply referred to as “half-width”) in the omega (ω) angle scan by X-ray diffraction measurement is 150, 100, 60, and 50 arcsec, respectively. A vertical pn junction diode having a type semiconductor region 113 was manufactured according to the above-described manufacturing method. FIG. 4 shows the result of measuring the leakage current when a voltage is applied to these vertical pn junction diodes. In FIG. 4, the horizontal axis represents voltage (V), and the vertical axis represents leakage current (A). Here, in FIG. 4, the vertical axis indicates logarithm.

  From the results of FIG. 4, the following was found. That is, the leakage current of the vertical pn junction diode having a half-value width of 150 arcsec is very high compared to the theoretical characteristics, whereas the leakage current of the vertical pn junction diode is reduced as the half-value width is reduced. It was. It was also found that the leakage current of the vertical pn junction diode having a half width of 60 arcsec or less substantially matches the theoretical characteristics.

FIG. 5 is a diagram showing the relationship between the time t in the heat treatment step and the half-value width when the temperature T in the heat treatment step is changed. In FIG. 5, the horizontal axis represents time t (minutes) in the heat treatment step, and the vertical axis represents the half width (arcsec). In FIG. 5, the horizontal axis is shown logarithmically. In FIG. 5, the result which set temperature T in a heat treatment process to 1250 degreeC and 1300 degreeC is shown. Here, the integrated dose amount was set to 2.3 × 10 ¹⁵ cm ⁻² . FIG. 5 shows the following. That is, it was found that the full width at half maximum decreases exponentially as the time t in the heat treatment process increases. In FIG. 5, the time t and the half width in the heat treatment step can be expressed by a linear function. When the temperature T in the heat treatment step is changed, the slope of the linear function does not substantially change, and the linear function Only the section was found to change.

FIG. 6 is a diagram showing the relationship between the time t in the heat treatment step and the half-value width when the integrated dose is changed. In FIG. 6, the horizontal axis represents the time t (minutes) in the heat treatment step, and the vertical axis represents the half width (arcsec). In FIG. 6, the horizontal axis is shown logarithmically. In FIG. 6, the integrated dose amount is (i) 2.3 × 10 ¹⁵ cm ⁻² , (ii) 1.15 × 10 ¹⁵ cm ^−2, and (iii) 4.6 × 10. ^The result of ¹⁴ cm ⁻² is shown. Here, the temperature T in the heat treatment step was set to 1250 ° C.

  From FIG. 6, the following was found. That is, it was found that the full width at half maximum decreases exponentially as the time t in the heat treatment process increases. In FIG. 6, the time t and the half width in the heat treatment step can be expressed by a linear function. When the integrated dose is changed, the slope of the linear function is not substantially changed, and only the intercept of the linear function is obtained. Was found to change.

From the above results, it was found that the integrated dose amount D (cm ⁻² ), the time t (minute) in the heat treatment step, and the temperature T (° C.) in the heat treatment step satisfy the relationship of the following formula (2). .

FIG. 7 is a diagram showing the relationship between the temperature T in the heat treatment step and the time t in the heat treatment step. In FIG. 7, the horizontal axis represents the temperature T (° C.) in the heat treatment step, and the vertical axis represents the time t (minute) in the heat treatment step. In FIG. 7, the vertical axis represents logarithm. FIG. 7 shows the result of setting the integrated dose amount to 2.3 × 10 ¹⁵ cm ⁻² . In FIG. 7, the relational expression of the above expression (2) is indicated by a straight line L. Further, in FIG. 7, the test result under the heat treatment condition of the temperature T and the time t at which the half width becomes 60 arcsec or less is indicated by “□ (white square)”, and the temperature T and the time at which the half width becomes larger than 60 arcsec. The test result under the heat treatment condition with t is indicated by “■ (black square)”. From this result, it is understood that the straight line L representing the relational expression of the above formula (2) is a boundary line between the heat treatment condition indicated by “□” and the heat treatment condition indicated by “■”. It was found that when the relational expression of Expression (1) is satisfied, the full width at half maximum is 60 arcsec or less.

A-4-2. Second Test Results FIG. 8 is a diagram showing the relationship between the integrated dose amount to the p-type semiconductor region 113 and the hole concentration after the heat treatment process in the ion implantation region 113. In FIG. 8, the horizontal axis represents the integrated dose amount (cm ⁻² ) to the p-type semiconductor region 113, and the vertical axis represents the hole concentration (cm ⁻³ ). In FIG. 8, the vertical axis and the horizontal axis are shown logarithmically.

  In general, the larger the integrated dose, the greater the crystal degradation of the p-type semiconductor region 113 due to ion implantation. For this reason, in order to recover the crystallinity in the p-type semiconductor region 113, it is necessary to lengthen the time in the heat treatment step, and it is necessary to increase the temperature in the heat treatment step. On the other hand, the smaller the integrated dose, the smaller the crystal degradation of the p-type semiconductor region 113 due to ion implantation. For this reason, the time in the heat treatment step can be shortened, and the temperature in the heat treatment step can be lowered, but the required hole concentration may not be obtained.

  FIG. 8 shows that the hole concentration does not increase when the integrated dose amount is too large or too small, and that the hole concentration becomes the highest by setting the specific integrated dose amount.

Here, in order to set the breakdown voltage of the pn junction diode to 600 V or higher, the hole concentration in the ion implantation region 113 after the heat treatment step needs to be 1 × 10 ¹⁶ cm ⁻³ or higher. In FIG. 8, when the integrated dose is 1.0 × 10 ¹⁴ cm ⁻² or more and 1.0 × 10 ¹⁵ cm ⁻² or less, the hole concentration in the ion implantation region 113 after the heat treatment step is 1 × 10 ¹⁶ cm. ^-3 or more. For this reason, it is preferable that an integrated dose amount shall be 1.0 * 10 ^{< 14} > cm ^<-2 > or more and 1.0 * 10 ^{< 15} > cm ^<-2 > or less.

  In general, the smaller the half width of the diffraction peak on the (0002) plane in the omega (ω) angle scan by X-ray diffraction measurement, the smaller the crystal defects in the ion implantation region. Although there is a report that the half width is 150 arcsec or less by epitaxial growth (see, for example, Japanese Patent Application Laid-Open No. 2005-167275), no report has been made that the half width is 60 arcsec or less in the ion-implanted region. For this reason, according to the manufacturing method in this embodiment, it turns out that the deterioration of crystallinity in an ion implantation area | region is fully recovered.

B. Second Embodiment FIG. 9 is a cross-sectional view schematically showing a configuration of a semiconductor device 200 in a second embodiment. In this embodiment, the semiconductor device 200 is a GaN-based semiconductor device formed using gallium nitride (GaN), and is a vertical Schottky barrier diode. In the present embodiment, the semiconductor device 200 is used for power control.

  The semiconductor device 200 includes a substrate 210, an n-type semiconductor layer 212, and a p-type semiconductor region 213. The semiconductor device 200 has a recess 222 as a structure formed in these semiconductor layers. The semiconductor device 100 further includes an insulating film 253, an anode electrode 251, and a cathode electrode 252.

  Also in the manufacturing method of the semiconductor device 200 of this embodiment, as in the first embodiment, (i) the n-type semiconductor layer 212 containing an n-type impurity has an integrated dose amount D that satisfies the above-described expression (1). an ion implantation step of ion-implanting p-type impurities; and (ii) p-type semiconductor region 213 which is an ion-implanted region into which p-type impurities are ion-implanted, in the nitrogen-containing atmosphere, A heat treatment step of performing a heat treatment at a temperature T and a time t to be satisfied. For this reason, also in the manufacturing method of the semiconductor device 200 of this embodiment, the deterioration of the crystallinity in the ion implantation region can be recovered.

  In the method for manufacturing the semiconductor device 200 according to the present embodiment, after the heat treatment step, the sputtering method and the atomic layer deposition method are performed on the n-type semiconductor layer 212 and the p-type semiconductor region 213 that is an ion implantation region. The method includes forming the insulating film 253 from at least one selected from the group consisting of silicon dioxide, aluminum oxide, and silicon nitride. Since the crystallinity of the p-type semiconductor region 213 has been recovered by the heat treatment process, leakage current at the interface with the insulating film 253 and the like can be prevented. Therefore, in the method for manufacturing the semiconductor device 200 of this embodiment, a good semiconductor can be obtained. A device can be obtained.

C. Third Embodiment FIG. 10 is a cross-sectional view schematically showing a configuration of a semiconductor device 300 according to a third embodiment. In this embodiment, the semiconductor device 300 is a GaN-based semiconductor device formed using gallium nitride (GaN), and is a vertical trench MOSFET (Metal-Oxide-Semiconductor Field-Effect Transistor). In the present embodiment, the semiconductor device 300 is used for power control.

  The semiconductor device 300 includes a substrate 310, an n-type semiconductor layer 312, a p-type semiconductor region 313, a p-type semiconductor layer 314, and an n-type semiconductor layer 316. The semiconductor device 300 includes a trench 322 and a recess 324 as a structure formed in these semiconductor layers. The semiconductor device 300 further includes an insulating film 330, a gate electrode 342, a body electrode 344, a source electrode 346, and a drain electrode 348.

  Also in the manufacturing method of the semiconductor device 300 of this embodiment, as in the first embodiment, (i) the n-type semiconductor layer 312 containing an n-type impurity has an integrated dose amount D that satisfies the above-described expression (1). an ion implantation step of ion-implanting p-type impurities; and (ii) p-type semiconductor region 313, which is an ion-implanted region of p-type impurities, is subjected to the above-described equation (1) in an atmosphere containing nitrogen. A heat treatment step of performing a heat treatment at a temperature T and a time t to be satisfied. For this reason, also in the manufacturing method of the semiconductor device 300 of this embodiment, the deterioration of crystallinity in the ion implantation region can be recovered.

  In the method for manufacturing the semiconductor device 300 of this embodiment, after the heat treatment step, on the p-type semiconductor region 313 that is the ion implantation region, at least one of metal organic vapor phase epitaxy and molecular beam epitaxy is used. forming a p-type semiconductor layer 314 containing a p-type impurity. Since the crystallinity of the p-type semiconductor region 313 is recovered, the crystallinity of the p-type semiconductor layer 314 formed on the flat surface of the p-type semiconductor region 313 is improved. For this reason, in the manufacturing method of the semiconductor device 300 of this embodiment, a favorable semiconductor device can be obtained.

D. Other Embodiments The present invention is not limited to the above-described embodiments, and can be realized with various configurations without departing from the spirit of the present invention. For example, the technical features in the embodiments, examples, and modifications corresponding to the technical features in each embodiment described in the summary section of the invention are to solve some or all of the above-described problems, or In order to achieve part or all of the above-described effects, replacement or combination can be performed as appropriate. Further, if the technical feature is not described as essential in the present specification, it can be deleted as appropriate.

In the above-described embodiment, the material of the semiconductor layer is not limited to gallium nitride (GaN), but other group III nitride semiconductors such as aluminum nitride (AlN), for example, silicon (Si), silicon carbide (SiC), It may be gallium oxide (Ga ₂ O ₃ ), gallium arsenide (GaAs), diamond (C), or the like. The material for the substrate may be, for example, sapphire (Al ₂ O ₃ ) in addition to the material for the semiconductor layer.

DESCRIPTION OF SYMBOLS 100 ... Semiconductor device 110 ... Substrate 112 ... N-type semiconductor layer 113 ... P-type semiconductor region (ion implantation region)
DESCRIPTION OF SYMBOLS 124 ... Recess 130 ... Insulating film 142 ... Anode electrode 144 ... Cathode electrode 150 ... Cover layer 152 ... Through film 154 ... Cap layer 200 ... Semiconductor device 210 ... Substrate 212 ... N-type semiconductor layer 213 ... P-type semiconductor region 222 ... Recess 251 ... Anode electrode 252 ... Cathode electrode 253 ... Insulating film 300 ... Semiconductor device 310 ... Substrate 312 ... n-type semiconductor layer 313 ... p-type semiconductor region 314 ... p-type semiconductor layer 316 ... n-type semiconductor layer 322 ... trench 324 ... recess 330 ... Insulating film 342 ... Gate electrode 344 ... Body electrode 346 ... Source electrode 348 ... Drain electrode D ... Integrated dose T ... Temperature t ... Time

Claims (6)

A method for manufacturing a semiconductor device, comprising:
an ion implantation step of ion-implanting a p-type impurity with an integrated dose amount D into an n-type semiconductor layer containing the n-type impurity;
A heat treatment step of heat-treating the ion-implanted region into which the p-type impurity is ion-implanted in a nitrogen-containing atmosphere at a temperature T and a time t,
The integrated dose amount D, the temperature T, and the time t satisfy the following expression (1).

A method of manufacturing a semiconductor device according to claim 1,
In the ion implantation step, the p-type impurity includes at least one selected from the group consisting of magnesium, beryllium, and calcium. A method of manufacturing a semiconductor device according to claim 1 or 2,
The method for manufacturing a semiconductor device, wherein an implantation temperature in the ion implantation step is 20 ° C. or higher and 900 ° C. or lower. It is a manufacturing method of the semiconductor device according to any one of claims 1 to 3,
The method of manufacturing a semiconductor device, wherein an implantation angle in the ion implantation step is 0 ° to 15 °. A method for manufacturing a semiconductor device according to any one of claims 1 to 4,
A method for manufacturing a semiconductor device, wherein at least one selected from the group consisting of nitrogen, ammonia, and hydrazine is used as a nitrogen source in the heat treatment step. A method for manufacturing a semiconductor device according to any one of claims 1 to 5,
The method for manufacturing a semiconductor device, wherein the pressure in the heat treatment step is 10 kPa or more and 110 kPa or less.

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