JP6801556B2 - Manufacturing method of semiconductor devices - Google Patents

Description

The present invention relates to a method for manufacturing a semiconductor device.

Conventionally, a technique for forming a p-type semiconductor region by ion implantation into a group III nitride semiconductor such as gallium nitride (GaN) has been known. Patent Documents 1 to 3 describe, as a method for forming a p-type semiconductor region, a method in which a p-type impurity is ion-implanted into a semiconductor layer and then a heat treatment is performed to restore crystallinity in the ion-implanted region. ing.

Japanese Unexamined Patent Publication No. 2004-356257 Japanese Unexamined Patent Publication No. 2016-181580 Patent No. 5358955

However, in general, the deterioration of crystallinity due to ion implantation is severe, and there is a possibility that the conventional method cannot sufficiently recover the deterioration of crystallinity in the ion implantation region even after heat treatment. Further, if the deterioration of crystallinity in the ion implantation region cannot be sufficiently recovered, there is a problem that the leakage current of the semiconductor device increases. Therefore, a method for sufficiently recovering the deterioration of crystallinity in the ion-implanted region has been desired.

［形態２］半導体装置の製造方法であって、
ｎ型不純物を含有しIII属窒化物半導体から形成されるｎ型半導体層に、積算ドーズ量Ｄでｐ型不純物をイオン注入するイオン注入工程と、
加熱装置を用いて、前記ｐ型不純物がイオン注入されたイオン注入領域を、窒素を含有する雰囲気下において、温度Ｔ及び時間ｔで熱処理を行う熱処理工程と、
を備え、
前記加熱装置における前記温度Tおよび前記時間ｔを設定する制御装置において、前記積算ドーズ量Dを用いて下記（１）式に基づき、前記温度Tと前記時間ｔとを設定する工程を、さらに備える、半導体装置の製造方法。

The present invention has been made to solve at least a part of the above-mentioned problems, and can be realized as the following forms.
[Form 1] A method for manufacturing a semiconductor device.
On the substrate, an n-type semiconductor layer containing an n-type impurity and formed of a group III nitride semiconductor and a through film formed of an element whose main component is not a donor element in the n-type semiconductor layer are formed. The process of forming in order and
An ion implantation step of ion-implanting a p-type impurity into the n-type semiconductor layer containing the n-type impurity with the through film formed at an integrated dose amount D.
After the ion implantation, a step of forming a cap layer on the through film and
A heat treatment in which the ion-implanted region in which the p-type impurities are ion-implanted is covered with a coating layer composed of the through film and the cap layer, and heat treatment is performed at a temperature T and a time t in a nitrogen-containing atmosphere. With process,
A method for manufacturing a semiconductor device, wherein the integrated dose amount D, the temperature T, and the time t satisfy the following equation (1).

[Form 2] A method for manufacturing a semiconductor device.
An ion implantation step of ion-implanting a p-type impurity into an n-type semiconductor layer containing an n-type impurity and formed from a group III nitride semiconductor with an integrated dose amount D.
A heat treatment step in which the ion-implanted region in which the p-type impurities are ion-implanted is heat-treated at a temperature T and a time t in an atmosphere containing nitrogen using a heating device.
With
The control device for setting the temperature T and the time t in the heating device further includes a step of setting the temperature T and the time t based on the following equation (1) using the integrated dose amount D. , Manufacturing method of semiconductor device.

(1) According to one embodiment of the present invention, a method for manufacturing a semiconductor device is provided. The method for manufacturing this semiconductor device includes an ion implantation step of ion-implanting a p-type impurity into an n-type semiconductor layer containing an n-type impurity with an integrated dose amount D, and an ion implantation region in which the p-type impurity is ion-implanted. A heat treatment step of performing heat treatment at a temperature T and a time t in an atmosphere containing nitrogen is provided, and the integrated dose amount D, the temperature T, and the time t satisfy the following equation (1). .. According to the method for manufacturing a semiconductor device of this form, the deterioration of crystallinity in the ion implantation region can be recovered.

(2) In the above-mentioned production method, in the ion implantation step, the p-type impurity may contain at least one selected from the group consisting of magnesium, beryllium, and calcium.

(3) In the above-mentioned production method, the implantation temperature in the ion implantation step may be 20 ° C. or higher and 900 ° C. or lower.

(4) In the above-mentioned manufacturing method, the implantation angle in the ion implantation step may be 0 ° or more and 15 ° or less.

(5) In the above-mentioned production method, at least one selected from the group consisting of nitrogen, ammonia, and hydrazine may be used as the nitrogen source in the heat treatment step.

(6) In the above-mentioned production method, the pressure in the heat treatment step may be 10 kPa or more and 110 kPa or less.

The present invention can also be realized in various forms other than the method for manufacturing a semiconductor device. For example, it can be realized in the form of a semiconductor device manufactured by using the above-mentioned manufacturing method, an apparatus for manufacturing a semiconductor device by using the above-mentioned manufacturing method, or the like.

According to the method for manufacturing a semiconductor device of the present invention, the deterioration of crystallinity in the ion implantation region can be recovered.

The cross-sectional view which shows typically the structure of the semiconductor device in 1st Embodiment. The process drawing which shows the manufacturing method of the semiconductor device in 1st Embodiment. The schematic diagram which shows the state after the cap layer was formed. The figure which shows the result of the evaluation test. The figure which shows the relationship between the time in a heat treatment process and a half width. The figure which shows the relationship between the time in a heat treatment process and a half width. The figure which shows the relationship between the temperature in a heat treatment process and time in a heat treatment process. The figure which shows the relationship between the integrated dose amount to the p-type semiconductor region, and the hole density. The cross-sectional view which shows typically the structure of the semiconductor device in 2nd Embodiment. The cross-sectional view which shows typically the structure of the semiconductor device in 3rd Embodiment.

A. First Embodiment A-1. Configuration of Semiconductor Device FIG. 1 is a cross-sectional view schematically showing the configuration of the semiconductor device 100 according to the first embodiment. FIG. 1 shows XYZ axes that are orthogonal to each other. Of the XYZ axes of FIG. 1, the X axis is an axis from the left side of the paper surface to the right side of the paper surface of FIG. The + X-axis direction is the direction toward the right side of the paper surface, and the −X-axis direction is the direction toward the left side of the paper surface. Of the XYZ axes of FIG. 1, the Y axis is an axis from the front side of the paper surface to the back side of the paper surface of FIG. The + Y-axis direction is the direction toward the back of the paper, and the −Y-axis direction is the direction toward the front of the paper. Of the XYZ axes of FIG. 1, the Z axis is an axis extending from below the paper surface to above the paper surface of FIG. The + Z-axis direction is the direction toward the top of the paper, and the −Z-axis direction is the direction toward the bottom of the paper. The XYZ axes in FIG. 1 correspond to the XYZ axes in other figures.

In the present embodiment, the semiconductor device 100 is a GaN-based semiconductor device formed by using gallium nitride (GaN). In this embodiment, the semiconductor device 100 is a vertical pn junction diode. In this embodiment, the semiconductor device 100 is used for power control.

The semiconductor device 100 includes a substrate 110, an n-type semiconductor layer 112, and a p-type semiconductor region 113. The semiconductor device 100 has a recess 124 as a structure formed in these semiconductor layers. The semiconductor device 100 further includes an insulating film 130, an anode electrode 142, and a cathode electrode 144.

The substrate 110, the n-type semiconductor layer 112, and the p-type semiconductor region 113 of the semiconductor device 100 are plate-shaped semiconductors extending along the X-axis and the Y-axis. In the present embodiment, the substrate 110, the n-type semiconductor layer 112, and the p-type semiconductor region 113 are formed of a group III nitride semiconductor. Examples of the group III nitride semiconductor include gallium nitride (GaN), aluminum nitride (AlN), aluminum gallium nitride (AlGaN), indium gallium nitride (InGaN), and indium gallium nitride (InAlGaN). From the viewpoint of being used in a semiconductor device for power control, gallium nitride (GaN) and aluminum gallium nitride (AlGaN) are preferable as the group III nitride semiconductor. In this embodiment, gallium nitride (GaN) is used as the group III nitride semiconductor. In addition, in the range where the effect of this embodiment is exhibited, a part of gallium nitride (GaN) may be replaced with another group III element such as aluminum (Al) or indium (In), and may contain other impurities. You may.

The substrate 110 of the semiconductor device 100 is a semiconductor having n-type characteristics. In the present embodiment, the silicon (Si) concentration contained in the substrate 110 is 1 × 10 ¹⁸ cm ^-3 or more. In the present embodiment, the thickness of the substrate 110 (length in the Z-axis direction) is 100 μm or more and 500 μm or less.

The n-type semiconductor layer 112 of the semiconductor device 100 is a semiconductor having n-type characteristics. In the present embodiment, the n-type semiconductor layer 112 is located on the + Z axis direction side of the substrate 110. In the present embodiment, the silicon (Si) concentration contained in the n-type semiconductor layer 112 is 1 × 10 ¹⁶ cm ^-3 . In the present embodiment, the thickness (length in the Z-axis direction) of the n-type semiconductor layer 112 is 10 μm or more and 20 μm or less.

The p-type semiconductor region 113 of the semiconductor device 100 is a region formed by ion implantation on the surface (the surface on the + Z axis direction side) of the n-type semiconductor layer 112. The p-type semiconductor region 113 is also referred to as an ion implantation region 113. The semiconductor in the p-type semiconductor region 113 has p-type characteristics. In the present embodiment, the p-type semiconductor region 113 contains magnesium (Mg) as an acceptor element (p-type impurity). In the present embodiment, the concentration of magnesium (Mg) in the p-type semiconductor region 113 is 1 × 10 ¹⁸ cm ^-3 or more and 5 × 10 ¹⁹ cm ^-3 or less. In the present embodiment, the thickness (length in the Z-axis direction) of the p-type semiconductor region 113 is 0.1 μm or more and 1.0 μm or less.

In the p-type semiconductor region 113, the full width at half maximum of the diffraction peak on the (0002) plane in the omega (ω) angle scan by X-ray diffraction measurement is 100 arcsec or less, preferably 60 arcsec or less.

The recess 124 of the semiconductor device 100 is a groove that penetrates the p-type semiconductor region 113 from the surface (the surface on the + Z axis direction side) of the p-type semiconductor region 113 and falls into the n-type semiconductor layer 112. In the present embodiment, the recess 124 is formed by dry etching the p-type semiconductor region 113 and the n-type semiconductor layer 112. Due to the recess 124, the p-type semiconductor region 113 has a plateau-like shape having a surface and a side surface.

The anode electrode 142 of the semiconductor device 100 is formed on the p-type semiconductor region 113. The anode electrode 142 is an electrode that makes ohmic contact with the p-type semiconductor region 113. In the present embodiment, the anode electrode 142 is an electrode formed by applying heat treatment to a layer formed of palladium (Pd).

The insulating film 130 of the semiconductor device 100 is a film formed on the n-type semiconductor layer 112 and the anode electrode 142 and having electrical insulation. In the present embodiment, the insulating film 130 is in contact with the surface of the n-type semiconductor layer 112 and a part of the surface of the anode electrode 142, and is also in contact with the side surface of the p-type semiconductor region 113 and the side surface of the anode electrode 142. In the present embodiment, the insulating film 130 is formed of silicon dioxide (SiO ₂ ).

The cathode electrode 144 of the semiconductor device 100 is an electrode that makes ohmic contact with the back surface of the substrate 110 on the −Z axis direction side. In the present embodiment, the cathode electrode 144 is an electrode formed by laminating a layer formed of aluminum (Al) on a layer formed of titanium (Ti) and then applying heat treatment.

A-2. Manufacturing Method of Semiconductor Device FIG. 2 is a process diagram showing a manufacturing method of the semiconductor device 100 according to the first embodiment. First, in step P101, after preparing the substrate 110, the manufacturer continuously forms the n-type semiconductor layer 112 and the through film on the substrate 110 in this order. The through film is used to adjust the concentration distribution of p-type impurities implanted in the n-type semiconductor layer 112 in the ion implantation step described later. The n-type semiconductor layer 112 and the through film are formed by a metal organic chemical vapor deposition (MOCVD) method. By continuously forming the n-type semiconductor layer 112 and the through film, impurity contamination between the n-type semiconductor layer 112 and the through film can be prevented. The through film is formed of an element whose main component is not a donor element in a group III nitride semiconductor. By doing so, it is possible to prevent the component elements of the through film from being implanted into the n-type semiconductor layer 112 in the ion implantation step described later. In the present embodiment, the through film is formed of amorphous aluminum nitride (AlN), and the thickness of the through film is 30 nm.

ここで、Ｔは、後述する熱処理工程における温度（℃）であり、ｔは、熱処理工程における時間（分）である。例えば、まず、温度Ｔを１２５０℃と設定し、時間ｔを０．１分（６秒）と設定した場合、（１）式の右辺は４．６×１０^１４となる。このため、温度Tが１２５０℃であり、時間ｔが０．１分（６秒）である場合、積算ドーズ量Ｄは４．６×１０^１４ｃｍ^−２以下となる。これとは反対に、まず、所望のホール濃度から必要な積算ドーズ量Ｄを設定した後、（１）式を満たすように温度Ｔと時間ｔとを設定してもよい。 Next, in step P103, the manufacturer ion-implants the p-type impurity into the n-type semiconductor layer 112 containing the n-type impurity with an integrated dose amount D (cm- ² ) that satisfies the following equation (1). The step P103 is also referred to as an ion implantation step.

Here, T is the temperature (° C.) in the heat treatment step described later, and t is the time (minutes) in the heat treatment step. For example, when the temperature T is first set to 1250 ° C. and the time t is set to 0.1 minutes (6 seconds), the right side of the equation (1) is 4.6 × 10 ¹⁴ . Therefore, when the temperature T is 1250 ° C. and the time t is 0.1 minutes (6 seconds), the integrated dose amount D is 4.6 × 10 ¹⁴ cm- ² or less. On the contrary, the temperature T and the time t may be set so as to satisfy the equation (1) after first setting the required integrated dose amount D from the desired hole concentration.

The manufacturer controls the amount of p-type impurities implanted in the ion implantation step by the integrated dose amount. The smaller the integrated dose amount, the smaller the half width of the diffraction peak on the (0002) plane in the omega (ω) angle scan by X-ray diffraction measurement. That is, the smaller the integrated dose amount, the smaller the crystal defects in the ion implantation region 113 due to ion implantation.

The p-type impurity used for ion implantation preferably contains at least one selected from the group consisting of magnesium (Mg), beryllium (Be), and calcium (Ca). In this embodiment, magnesium (Mg) is used as the p-type impurity. A part of the surface side (+ Z-axis direction side surface) of the n-type semiconductor layer 112, in which the p-type impurities are injected, becomes the p-type semiconductor region 113 by undergoing the heat treatment described later.

The integrated dose amount is preferably 1.0 × 10 ¹⁴ cm- ² or more and 1.0 × 10 ¹⁵ cm- ² or less. In this embodiment, the integrated dose amount is 1.0 × 10 ¹⁴ cm- ² . The implantation temperature in the ion implantation step is preferably 20 ° C. or higher and 900 ° C. or lower. The implantation angle in the ion implantation step is preferably 0 ° or more and 15 ° or less.

By performing ion implantation on the n-type semiconductor layer 112 with the through film formed, the distribution of the concentration of p-type impurities injected into the n-type semiconductor layer 112 can be appropriately adjusted. In the ion-implanted region, the concentration distribution of the implanted impurities is the sum of two or more normal distributions in the depth direction (Z-axis direction). Here, when the concentration distribution is a normal distribution, the concentration of the injected impurities becomes the highest at a position at a predetermined distance from the exposed surface in the depth direction (Z-axis direction). It means that the concentration of impurities decreases as the distance from the front side and the back side increases. Ion implantation is performed in a state where a through film designed to have the highest concentration of magnesium atoms (Mg) is arranged at a predetermined position in the n-type semiconductor layer 112 near the surface of the n-type semiconductor layer 112. Thereby, the peak of the concentration of impurities can be set near the surface of the n-type semiconductor layer 112.

In step P105, the manufacturer forms a cap layer on the through film.

FIG. 3 is a schematic view showing a state after the cap layer is formed. In FIG. 3, the cap layer 154 formed on the through film 152 is formed of amorphous aluminum nitride (AlN) in this embodiment. In the present embodiment, the cap layer 154 is formed by the organic metal vapor phase growth method (MOCVD), but may be formed by a sputtering method.

The through film 152 and the cap layer 154 are the coating layer 150 that covers the ion implantation region 113 in the heat treatment step described later. In this embodiment, the coating layer 150 is made of amorphous aluminum nitride (AlN). In the present embodiment, the thickness of the cap layer 154 is 1 nm or more and 1000 nm or less. The cap layer 154 may be formed of, for example, (i) aluminum gallium nitride (AlGaN), and by (ii) sputtering, a layer of aluminum nitride (AlN) and a layer of aluminum gallium nitride (AlGaN). And may be used in this order.

Next, in step P107 (see FIG. 2), the manufacturer heat-treats the ion-implanted region 113 in which p-type impurities are ion-implanted in an atmosphere containing nitrogen (N). Step P107 is also referred to as a heat treatment step. The heat treatment step is carried out in the state shown in FIG. Further, in the present embodiment, the heat treatment is performed in a state where the p-type semiconductor region 113 is covered, but the heat treatment may be performed in a state where the p-type semiconductor region 113 is exposed.

The temperature T in the heat treatment step is a temperature that satisfies the above equation (1). The temperature T in the heat treatment step is preferably 800 ° C. or higher and 1500 ° C. or lower. In the present embodiment, the temperature T in the heat treatment step is 1250 ° C. The time t in the heat treatment step is preferably 1 second or more and 10 minutes or less, and more preferably 1 second or more and less than 1 minute. In the present embodiment, the time t in the heat treatment step is 30 seconds (0.5 minutes). The pressure in the heat treatment step is preferably 10 kPa or more and 110 kPa or less. In this embodiment, the pressure in the heat treatment step is 100 kPa.

Further, as the nitrogen source in the heat treatment step, it is preferable to use at least one selected from the group consisting of nitrogen (N ₂ ), ammonia (NH ₃ ) and hydrazine (N ₂ H ₄ ). By undergoing the heat treatment step, p-type impurities in the ion implantation region 113 are activated, and a high hole concentration can be obtained.

Next, in step P109 (see FIG. 2), the manufacturer removes the coating layer 150. In the present embodiment, the manufacturer performs wet etching using tetramethylammonium hydroxide (TMAH) having a pH of 65 ° C. or higher and 85 ° C. or lower. In addition, dry etching may be used instead of wet etching.

In step P111, the manufacturer forms the recess 124 by dry etching. Then, in step P113, the manufacturer forms an electrode on the ion implantation region 113 by at least one of a vapor deposition method and a sputtering method. In the present embodiment, the manufacturer forms the anode electrode 142 and the cathode electrode 144 on the ion implantation region 113 by a vapor deposition method.

Then, in step P115, the manufacturer applies silicon dioxide (SiO ₂ ) on the n-type semiconductor layer 112 and the anode electrode 142 by at least one of a sputtering method and an atomic layer deposition method (ALD). The insulating film 130 is formed from at least one selected from the group consisting of aluminum oxide (Al ₂ O ₃ ) and silicon nitride (Si ₃ N ₄ ). In the present embodiment, the manufacturer forms the insulating film 130 from silicon dioxide (SiO ₂ ) by the atomic layer deposition method. Through these steps, the semiconductor device 100 is completed.

A-3. Effect According to the manufacturing method of the first embodiment described above, the ion implantation step (step P103) and the heat treatment step (step P107) are provided, and the integrated dose amount D (cm- ² ) and the temperature in the heat treatment step are provided. When T (° C.) and the time (minutes) in the heat treatment step satisfy the following equation (1), the deterioration of crystallinity in the ion implantation region can be recovered. The results of the evaluation test confirming that such an effect can be obtained are shown.

A-4. Test result A-4-1. First Test Result FIG. 4 is a diagram showing the result of the evaluation test. The tester found that the half width of the GaN (0002) diffraction peak (hereinafter, also simply referred to as "half width") in the omega (ω) angle scan by X-ray diffraction measurement is 150, 100, 60, 50 arcsec, respectively. A vertical pn junction diode having a type semiconductor region 113 was manufactured according to the above-mentioned manufacturing method. FIG. 4 shows the results of measuring the leakage current when a voltage is applied to these vertical pn junction diodes. In FIG. 4, the horizontal axis is the voltage (V) and the vertical axis is the leak current (A). Here, in FIG. 4, the vertical axis is shown logarithmically.

From the results of FIG. 4, the following was found. That is, it was found that the leakage current of the vertical pn junction diode with a half width of 150 arcsec is very high compared to the theoretical characteristics, whereas the leakage current of the vertical pn junction diode becomes smaller as the half width becomes smaller. It was. It was also found that the leakage current of the vertical pn junction diode having a half width of 60 arcsec or less almost matches the theoretical characteristics.

FIG. 5 is a diagram showing the relationship between the time t in the heat treatment step and the full width at half maximum when the temperature T in the heat treatment step is changed. In FIG. 5, the horizontal axis is the time t (minutes) in the heat treatment step, and the vertical axis is the full width at half maximum (arcsec). In FIG. 5, the horizontal axis is shown logarithmically. FIG. 5 shows the result of setting the temperature T in the heat treatment step to 1250 ° C and the result of setting the temperature T to 1300 ° C. Here, the integrated dose amount was set to 2.3 × 10 ¹⁵ cm- ² . From FIG. 5, the following was found. That is, it was found that the half-value width decreased exponentially as the time t in the heat treatment step increased. Further, in FIG. 5, the time t and the full width at half maximum in the heat treatment step can be expressed by a linear function, and when the temperature T in the heat treatment step is changed, the slope of this linear function hardly changes, and the slope of this linear function does not change. It was found that only the sections changed.

FIG. 6 is a diagram showing the relationship between the time t in the heat treatment step and the full width at half maximum when the integrated dose amount is changed. In FIG. 6, the horizontal axis is the time t (minutes) in the heat treatment step, and the vertical axis is the full width at half maximum (arcsec). In FIG. 6, the horizontal axis is shown logarithmically. In FIG. 6, the cumulative dose amount is (i) 2.3 × 10 ¹⁵ cm- ² , (ii) 1.15 × 10 ¹⁵ cm- ^2, and (iii) 4.6 × 10. ^The result of ¹⁴ cm- ² is shown. Here, the temperature T in the heat treatment step was set to 1250 ° C.

From FIG. 6, the following was found. That is, it was found that the half-value width decreased exponentially as the time t in the heat treatment step increased. Further, in FIG. 6, the time t and the full width at half maximum in the heat treatment step can be expressed by a linear function, and when the integrated dose amount is changed, the slope of this linear function hardly changes, and only the intercept of this linear function. Turned out to change.

From the above results, it was found that the integrated dose amount D (cm- ² ), the time t (minutes) in the heat treatment step, and the temperature T (° C.) in the heat treatment step satisfy the relationship of the following formula (2). ..

FIG. 7 is a diagram showing the relationship between the temperature T in the heat treatment step and the time t in the heat treatment step. In FIG. 7, the horizontal axis is the temperature T (° C.) in the heat treatment step, and the vertical axis is the time t (minutes) in the heat treatment step. In FIG. 7, the vertical axis is shown logarithmically. FIG. 7 shows the result of setting the integrated dose amount to 2.3 × 10 ¹⁵ cm- ² . In FIG. 7, the relational expression of the above equation (2) is shown by a straight line L. Further, in FIG. 7, the test results under the heat treatment conditions of the temperature T and the time t whose half width is 60 arcsec or less are indicated by “□ (white square)”, and the temperature T and time when the half width is larger than 60 arcsec The test results under the heat treatment conditions with t are indicated by "■ (black square)". From this result, it can be seen that the straight line L representing the relational expression of the above equation (2) is the boundary line between the heat treatment conditions indicated by “□” and the heat treatment conditions indicated by “■”. It was found that the full width at half maximum was 60 arcsec or less when the relational expression of the equation (1) was satisfied.

A-4-2. The second test result FIG. 8 is a diagram showing the relationship between the integrated dose amount into the p-type semiconductor region 113 and the hole concentration after the heat treatment step in the ion implantation region 113. In FIG. 8, the horizontal axis is the integrated dose amount (cm- ² ) to the p-type semiconductor region 113, and the vertical axis is the hole concentration (cm- ³ ). In FIG. 8, the vertical axis and the horizontal axis are shown logarithmically.

In general, the larger the integrated dose amount, the greater the crystal deterioration of the p-type semiconductor region 113 due to ion implantation. Therefore, in order to restore the crystallinity in the p-type semiconductor region 113, it is necessary to lengthen the time in the heat treatment step, and it is necessary to raise the temperature in the heat treatment step. On the other hand, the smaller the integrated dose amount, the smaller the crystal deterioration of the p-type semiconductor region 113 due to ion implantation. Therefore, the time in the heat treatment step can be shortened, and the temperature in the heat treatment step can be lowered, but there is a possibility that the required hole concentration cannot be obtained.

From FIG. 8, it was found that the hole concentration did not increase when the integrated dose amount was too large or too small, and that the hole concentration became the highest when the integrated dose amount was set to a specific value.

Here, in order to make the withstand voltage of the pn junction diode 600 V or more, the hole concentration in the ion implantation region 113 after the heat treatment step needs to be 1 × 10 ¹⁶ cm ^-3 or more. In FIG. 8, when the integrated dose amount is 1.0 × 10 ¹⁴ cm- ² or more and 1.0 × 10 ¹⁵ cm- ² or less, the hole concentration in the ion implantation region 113 after the heat treatment step is 1 × 10 ¹⁶ cm. It becomes ^-3 or more. Therefore, the integrated dose amount is preferably 1.0 × 10 ¹⁴ cm- ² or more and 1.0 × 10 ¹⁵ cm- ² or less.

Further, in general, in an omega (ω) angle scan by X-ray diffraction measurement, the smaller the half width of the diffraction peak on the (0002) plane, the smaller the crystal defect in the ion implantation region. Although there is a report that the half width is 150 arcsec or less due to epitaxial growth (see, for example, Japanese Patent Application Laid-Open No. 2005-167275), there is no report that the half width is 60 arcsec or less in the region where ion implantation is performed. Therefore, according to the production method in the present embodiment, it can be seen that the deterioration of crystallinity in the ion implantation region is sufficiently recovered.

B. Second Embodiment FIG. 9 is a cross-sectional view schematically showing the configuration of the semiconductor device 200 in the second embodiment. In the present embodiment, the semiconductor device 200 is a GaN-based semiconductor device formed by using gallium nitride (GaN), and is a vertical Schottky barrier diode. In this embodiment, the semiconductor device 200 is used for power control.

The semiconductor device 200 includes a substrate 210, an n-type semiconductor layer 212, and a p-type semiconductor region 213. The semiconductor device 200 has a recess 222 as a structure formed in these semiconductor layers. The semiconductor device 100 further includes an insulating film 253, an anode electrode 251 and a cathode electrode 252.

Also in the method for manufacturing the semiconductor device 200 of the present embodiment, similarly to the first embodiment, the n-type semiconductor layer 212 containing (i) n-type impurities has an integrated dose amount D satisfying the above-mentioned equation (1). The ion implantation step of ion-implanting the p-type impurity and (ii) the p-type semiconductor region 213, which is the ion-implanted region in which the p-type impurity is ion-implanted, are subjected to the above-mentioned equation (1) in an atmosphere containing nitrogen. A heat treatment step of performing heat treatment at a temperature T and a time t to be satisfied is provided. Therefore, even in the manufacturing method of the semiconductor device 200 of the present embodiment, the deterioration of crystallinity in the ion implantation region can be recovered.

In the method for manufacturing the semiconductor device 200 of the present embodiment, after the heat treatment step, a sputtering method and an atomic layer deposition method are performed on the n-type semiconductor layer 212 and on the p-type semiconductor region 213 which is an ion injection region. At least one of them comprises a step of forming an insulating film 253 from at least one selected from the group consisting of silicon dioxide, aluminum oxide, and silicon nitride. Since the p-type semiconductor region 213 is restored to its crystallinity by the heat treatment step, leakage current at the interface with the insulating film 253 can be prevented. Therefore, in the method for manufacturing the semiconductor device 200 of the present embodiment, a good semiconductor is used. You can get the device.

C. Third Embodiment FIG. 10 is a cross-sectional view schematically showing the configuration of the semiconductor device 300 according to the third embodiment. In the present embodiment, the semiconductor device 300 is a GaN-based semiconductor device formed by using gallium nitride (GaN), and is a vertical trench MOSFET (Metal-Oxide-Semiconductor Field-Effect Transistor). In this embodiment, the semiconductor device 300 is used for power control.

The semiconductor device 300 includes a substrate 310, an n-type semiconductor layer 312, a p-type semiconductor region 313, a p-type semiconductor layer 314, and an n-type semiconductor layer 316. The semiconductor device 300 has a trench 322 and a recess 324 as a structure formed in these semiconductor layers. The semiconductor device 300 further includes an insulating film 330, a gate electrode 342, a body electrode 344, a source electrode 346, and a drain electrode 348.

Also in the method for manufacturing the semiconductor device 300 of the present embodiment, similarly to the first embodiment, the n-type semiconductor layer 312 containing the n-type impurity (i) has an integrated dose amount D satisfying the above-mentioned equation (1). The ion implantation step of ion-implanting the p-type impurity and (ii) the p-type semiconductor region 313, which is the ion-implanted region in which the p-type impurity is ion-implanted, are subjected to the above-mentioned equation (1) in an atmosphere containing nitrogen. A heat treatment step of performing heat treatment at a temperature T and a time t to be satisfied is provided. Therefore, even in the manufacturing method of the semiconductor device 300 of the present embodiment, the deterioration of crystallinity in the ion implantation region can be recovered.

In the method for manufacturing the semiconductor device 300 of the present embodiment, after the heat treatment step, the organic metal vapor phase growth method and the molecular beam epitaxy method are performed on the p-type semiconductor region 313, which is an ion implantation region, by at least one of them. A step of forming a p-type semiconductor layer 314 containing a p-type impurity is provided. Since the crystallinity of the p-type semiconductor region 313 is restored, the crystallinity of the p-type semiconductor layer 314 formed on the flat surface of the p-type semiconductor region 313 is improved. Therefore, in the method of manufacturing the semiconductor device 300 of the present embodiment, a good semiconductor device can be obtained.

D. Other Embodiments The present invention is not limited to the above-described embodiments, and can be realized by various configurations within a range not deviating from the gist thereof. For example, the technical features in the embodiments, examples, and modifications corresponding to the technical features in each embodiment described in the column of the outline of the invention may be used to solve some or all of the above-mentioned problems. , It is possible to replace or combine as appropriate in order to achieve some or all of the above effects. Further, if the technical feature is not described as essential in the present specification, it can be appropriately deleted.

In the above-described embodiment, the material of the semiconductor layer is not limited to gallium nitride (GaN), but other group III nitride semiconductors such as aluminum nitride (AlN), for example, silicon (Si), silicon carbide (SiC), and the like. It may be gallium oxide (Ga ₂ O ₃ ), gallium arsenide (GaAs), diamond (C) or the like. The material of the substrate may be, for example, sapphire (Al ₂ O ₃ ) in addition to the material of the semiconductor layer described above.

100 ... Semiconductor device 110 ... Substrate 112 ... n-type semiconductor layer 113 ... p-type semiconductor region (ion implantation region)
124 ... recess 130 ... insulating film 142 ... anode electrode 144 ... cathode electrode 150 ... coating layer 152 ... through film 154 ... cap layer 200 ... semiconductor device 210 ... substrate 212 ... n-type semiconductor layer 213 ... p-type semiconductor region 222 ... recess 251 ... Anode electrode 252 ... Cathode electrode 253 ... Insulation film 300 ... Semiconductor device 310 ... Substrate 312 ... n-type semiconductor layer 313 ... p-type semiconductor region 314 ... p-type semiconductor layer 316 ... n-type semiconductor layer 322 ... Insulation film 342 ... Gate electrode 344 ... Body electrode 346 ... Source electrode 348 ... Drain electrode D ... Integrated dose amount T ... Temperature t ... Time

Claims (7)

It is a manufacturing method of semiconductor devices.
On the substrate, an n-type semiconductor layer containing an n-type impurity and formed of a group III nitride semiconductor and a through film formed of an element whose main component is not a donor element in the n-type semiconductor layer are formed. The process of forming in order and
The n-type semiconductor layer containing n-type impurity in a state where the through film is formed, an ion implantation step of implanting p-type impurities at a cumulative dose of D,
After the ion implantation, a step of forming a cap layer on the through film and
A heat treatment in which the ion-implanted region in which the p-type impurities are ion-implanted is covered with a coating layer composed of the through film and the cap layer, and heat treatment is performed at a temperature T and a time t in a nitrogen-containing atmosphere. With process,
A method for manufacturing a semiconductor device, wherein the integrated dose amount D, the temperature T, and the time t satisfy the following equation (1).

The method for manufacturing a semiconductor device according to claim 1.
A method for manufacturing a semiconductor device, wherein in the ion implantation step, the p-type impurity contains at least one selected from the group consisting of magnesium, beryllium, and calcium. The method for manufacturing a semiconductor device according to claim 1 or 2.
A method for manufacturing a semiconductor device, wherein the implantation temperature in the ion implantation step is 20 ° C. or higher and 900 ° C. or lower. The method for manufacturing a semiconductor device according to any one of claims 1 to 3.
A method for manufacturing a semiconductor device, wherein the implantation angle in the ion implantation step is 0 ° or more and 15 ° or less. The method for manufacturing a semiconductor device according to any one of claims 1 to 4.
A method for manufacturing a semiconductor device, which uses at least one selected from the group consisting of nitrogen, ammonia, and hydrazine as a nitrogen source in the heat treatment step. The method for manufacturing a semiconductor device according to any one of claims 1 to 5.
A method for manufacturing a semiconductor device, wherein the pressure in the heat treatment step is 10 kPa or more and 110 kPa or less. It is a manufacturing method of semiconductor devices.
An ion implantation step of ion-implanting a p-type impurity into an n-type semiconductor layer containing an n-type impurity and formed from a group III nitride semiconductor with an integrated dose amount D.
A heat treatment step in which the ion-implanted region in which the p-type impurities are ion-implanted is heat-treated at a temperature T and a time t in an atmosphere containing nitrogen using a heating device.
With
The control device for setting the temperature T and the time t in the heating device further includes a step of setting the temperature T and the time t based on the following equation (1) using the integrated dose amount D. , Manufacturing method of semiconductor device.

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