JP2014007389A - Hetero-junction type fet - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a hetero-junction type FET which is improved in both current leakage characteristic and current collapse characteristic.SOLUTION: The hetero-junction type FET includes: a GaN channel layer; an AlGaN barrier layer laminated on the channel layer; a source electrode and a drain electrode ohmically connected to the channel layer; and a gate electrode formed on the barrier layer between the source electrode and the drain electrode. The boundary surface of the channel layer touching the barrier layer has, between the drain electrode and the gate electrode, a relatively high sheet carrier concentration in a first region of 5% or more but not exceeding 30% close to the drain electrode and a relatively low sheet carrier concentration in a second region close to the gate electrode, not including the first region.

Description

  The present invention relates to a heterojunction field effect transistor (heterojunction FET), and more particularly to improvement of both current leakage characteristics and current collapse characteristics in a heterojunction FET.

  Heterojunction FETs using nitride semiconductors are characterized by having a high breakdown voltage and high carrier mobility, and are expected to be used in applications such as power devices.

  Heterojunction FETs used for applications such as power devices are desired to have the characteristics that current leakage is small in the off state and that current collapse phenomenon does not easily occur when used at a high voltage. Here, the current collapse means a phenomenon in which the on-resistance during the high voltage operation is higher than the on-resistance during the low voltage operation of the heterojunction FET.

  That is, current leakage and current collapse in a heterojunction FET both significantly reduce the efficiency of the heterojunction FET, so that both the current leakage characteristics and current collapse characteristics of the heterojunction FET improved. Development is desired.

JP 2010-251456 A

  Japanese Patent Laid-Open No. 2010-251456 of Patent Document 1 reduces the electron concentration in the vicinity of the gate electrode in the channel layer between the gate electrode and the drain electrode in order to improve the current collapse characteristics of the heterojunction FET. Propose that.

  However, in the heterojunction FET disclosed in Patent Document 1, it is not sufficient to consider the electron concentration in the vicinity of the gate electrode, and even if the current collapse characteristic can be improved, the current leakage characteristic may be deteriorated. obtain.

  Accordingly, an object of the present invention is to provide a heterojunction FET in which both current leakage characteristics and current collapse characteristics are improved.

  The heterojunction FET according to the present invention includes a GaN channel layer, an AlGaN barrier layer stacked on the channel layer, a source electrode and a drain electrode that are ohmically connected to the channel layer, and the source electrode and the drain electrode. Between the drain electrode and the gate electrode, the interface between the drain electrode and the gate electrode is within 30% close to the drain electrode and 0.5% or more. It has a relatively high sheet carrier concentration in the first region (hereinafter also referred to as “Ns” in the present specification and drawings), and is relatively close to the second region except the first region near the gate electrode. It is characterized by having a low sheet carrier concentration.

In such a heterojunction FET, a sheet carrier having a sheet carrier concentration of 6.3 × 10 ¹² / cm ² or more in the first region and 5.6 × 10 ¹² / cm ² or less in the second region. It is desirable to have a concentration. The AlGaN barrier layer may further include a GaN cap layer, the cap layer having a thickness reduced or removed above the first region as compared to above the second region at the interface of the channel layer. Preferably it is. Furthermore, the semiconductor surface may contain a higher concentration of oxygen in the first region than in the second region. Thus, the first region containing a relatively high concentration of oxygen can be formed by exposing the first region to oxygen plasma while the second region is covered with a resist.

  According to the present invention as described above, it is possible to provide a heterojunction FET in which both current leakage characteristics and current collapse characteristics are improved.

It is typical sectional drawing which shows an example of the laminated structure of heterojunction type FET relevant to this invention. 2 is a graph showing the relationship between a collapse value and a distance X (distance from a drain end) of a first region where a sheet carrier concentration Ns in a channel layer is increased in the heterojunction FET of FIG. 1. 2 is a graph showing the relationship between the leakage current and the distance X of the first region where the sheet carrier concentration Ns in the channel layer is increased in the heterojunction FET of FIG. 1. 2 is a graph showing the relationship between the sheet carrier concentration Ns in the channel layer and the collapse value in the first region from the drain electrode to the distance X in the heterojunction FET of FIG. 1. 2 is a graph showing the relationship between the sheet carrier concentration Ns in the channel layer and the leakage current in the second region from the point of distance X to the gate end in the heterojunction FET of FIG. 1. 2 is a graph showing the relationship between the oxygen concentration on the surface of the barrier layer and the sheet carrier concentration Ns in the heterojunction FET of FIG. 1. 2 is a graph showing the influence on the sheet carrier concentration Ns in the channel layer when the barrier layer is exposed to oxygen plasma in the heterojunction FET of FIG. FIG. 5 is a schematic cross-sectional view showing a part of an example of a heterojunction FET that additionally includes a GaN cap layer on an AlGaN barrier layer.

<Basic structure of heterojunction FET>
FIG. 1 is a schematic cross-sectional view showing an example of a laminated structure of heterojunction FETs related to the present invention. In this heterojunction FET, the source electrode S and the drain electrode D are ohmically connected to the GaN channel layer 1. An AlGaN barrier layer 2 is stacked between the source electrode S and the drain electrode D, and a gate electrode G is formed on a partial region of the AlGaN barrier layer 2. Then, between each of the source electrode S, the gate electrode G, and the drain electrode D, the collapse suppression film 3 and the insulating film 4 are laminated on the AlGaN barrier layer 2 in this order.

  The GaN channel layer 1 can have any necessary and sufficient thickness. The AlGaN barrier layer 2 forming a heterojunction with the GaN channel layer 1 may have a thickness of 34 nm, for example. A two-dimensional electron gas based on a heterojunction tends to be formed at the interface of the GaN channel layer 1 in contact with the AlGaN barrier layer 2, and this can act as a carrier in the FET.

  The insulating film 4 functions as a passivation film, and the collapse suppression film 3 functions to suppress the occurrence of current collapse due to carrier traps at the interface between the insulating film 4 and the AlGaN barrier layer 2.

The collapse suppression film 3 is a silicon nitride film rich in Si as compared with Si ₃ N ₄ having a stoichiometric composition. On the other hand, the insulating film 4 is a silicon nitride film close to Si ₃ N ₄ having a stoichiometric composition.

  The collapse suppression film 3 and the insulating film 4 are not limited to the above. That is, it is possible to use a Si-rich silicon nitride film as the collapse suppression film 3 and a silicon oxide film as the insulating film 4. In addition, the thickness of each film can be set to an arbitrary thickness.

Alternatively, a SiON film or a SiOC film can be used as the collapse suppression film 3. At this time, the insulating film 4 may not be formed, and as the insulating film 4, any one of a Si-rich silicon film, a silicon nitride film close to the stoichiometric composition of Si ₃ N ₄ , or a silicon oxide film is used. May be. Each film thickness can be set to an arbitrary thickness.

Furthermore, an AlN film can be used as the collapse suppression film 3. However, since the single crystal AlN film affects the two-dimensional electron gas, the AlN film used for the collapse suppression film 3 is preferably polycrystalline or amorphous. When an AlN film is used as the collapse suppression film 3, it is not necessary to form the insulating film 4 on the AlN film. The insulating film 4 may be a Si-rich silicon film or a stoichiometric Si ₃ N ₄ film. Either a silicon nitride film or a silicon oxide film close to the above may be used. It is also possible to use either a Si-rich silicon film, a silicon nitride film close to the stoichiometric composition of Si ₃ N ₄ , or a silicon oxide film as the collapse suppression film 3 and an AlN film as the insulating film 4. It is.

Furthermore, as the collapse suppression film 3, any one of a Si-rich silicon film, a silicon nitride film close to the stoichiometric composition of Si ₃ N ₄ , or a silicon oxide film is used, and the AlN film, SiON film is used as the insulating film 4. A combination of two or more of a film, a SiOC film, a silicon oxide film, or a silicon nitride film can also be used.

  In the heterojunction FET according to the present invention, the interface of the GaN channel layer 1 in contact with the AlGaN barrier layer 2 in the first region at the distance X from the drain electrode D to the gate electrode G is larger than in the remaining second region. The sheet carrier concentration Ns is increased. The distances between the source electrode S, the gate electrode G, and the drain electrode D can be set to 2 μm and 10 μm, for example. Further, the width of the gate electrode G in contact with the AlGaN barrier layer 2 can be set to 1 μm, for example.

<Influence of distance X of first region>
FIG. 2 is a graph showing the relationship between the distance X of the first region where the sheet carrier concentration Ns in the channel layer is higher than that of the second region and the collapse value in the heterojunction FET of FIG. That is, the horizontal axis of this graph represents the distance X (μm) of the portion (first region) where Ns is high from the drain end, and the vertical axis represents the collapse value. On the other hand, FIG. 3 is a graph showing the relationship between the leakage current and the distance X of the first region where Ns is relatively high in the channel layer. That is, the horizontal axis of the graph of FIG. 3 represents the distance X (μm) of the portion (first region) where Ns is high from the drain end, and the vertical axis represents the leakage current (A / μm).

2 and 3, the sheet carrier concentration in the first region from the drain end to the distance X is relatively high, Ns = 6.53 × 10 ¹² / cm ² , Ns = 5.47 × 10 ¹² / cm ² , where the sheet carrier concentration in the second region exceeding the gate electrode end to the gate electrode end is relatively low.

  In the graph of FIG. 2, the drain voltage Vd at the time of OFF is set to 400V, the drain voltage Vd is set to 1V at the time of ON, and the resistance value / initial resistance value after 5 μs after switching from OFF to ON. ) Is defined as the collapse value. On the other hand, in the graph of FIG. 3, in the off state, the gate voltage Vg is set to −10V, and the drain voltage Vd is set to 600V.

  From the graph of FIG. 2, it can be seen that when the distance X of the first region having relatively high Ns is 0.5 μm or more, the collapse value becomes small and the collapse characteristic of the heterojunction FET is improved. On the other hand, FIG. 3 shows that when the distance X of the first region having a relatively high Ns is 3 μm or less, the leakage current is reduced and the leakage current characteristics of the heterojunction FET are improved. That is, both the collapse characteristics and the leakage current characteristics of the heterojunction FET can be improved when the distance X is in the range of 0.5% to 30% of the distance between the gate electrode G and the drain electrode D. I understand that. In this embodiment, as an example, the distance between the gate electrode G and the drain electrode D is 10 μm. However, even if the distance between the gate electrode G and the drain electrode D is shorter or longer than 10 μm, The same effect as when the distance from the drain electrode D is 10 μm can be obtained.

  2 and 3, black diamonds indicate the case where silicon nitride is used as the collapse suppression film 3 and silicon nitride is used as the insulating film 4, and the white triangles indicate Si-rich silicon nitride as the collapse suppression film 3. A case where a silicon oxide film is used as the insulating film 4 is shown, and an oblique cross indicates a case where an AlN film is used as the collapse suppression film 3 and a silicon oxide film is used as the insulating film 4.

<Influence of Ns in first and second regions>
FIG. 4 is a graph showing the relationship between the sheet carrier concentration Ns in the first region from the drain end to the distance X and the collapse value in the heterojunction FET of FIG. That is, the horizontal axis of this graph represents Ns (× 10 ¹² / cm ² ) of the high Ns portion (first region), and the vertical axis represents the collapse value. On the other hand, FIG. 5 is a graph showing the relationship between the sheet carrier concentration Ns in the second region and the leakage current. That is, the horizontal axis of the graph of FIG. 5 represents Ns (× 10 ¹² / cm ² ) of the low Ns portion (second region), and the vertical axis represents the leakage current (A / μm).

  In both graphs of FIGS. 4 and 5, the distance X, which is the length of the first region, is set to 2.5 μm. Similarly to the case of FIG. 2, in the graph of FIG. 4, the drain voltage Vd at the time of off is set to 400 V, and the drain voltage Vd is set to 1 V at the time of on. Resistance value / initial resistance value) is defined as a collapse value. On the other hand, similarly to the case of FIG. 3, in the graph of FIG. 5, the gate voltage Vg is set to −10V and the drain voltage Vd is set to 600V in the off state.

From the graph of FIG. 4, when the Ns is 6.3 × 10 ¹² / cm ² or more in the first region from the drain end to the distance X, the collapse value becomes small and the collapse characteristic of the heterojunction FET is improved. I understand that. On the other hand, FIG. 5 shows that in the second region from the point of the distance X to the gate end, when Ns is 5.6 × 10 ¹² / cm ² or less, the leakage current becomes small, and the leakage current characteristics of the heterojunction FET It can be seen that is improved. That is, the sheet carrier concentration is 6.3 × 10 ¹² / cm ² or more in the first region from the drain end to the distance X, and the sheet carrier concentration is 5.6 × in the second region from the point of the distance X to the gate end. It can be seen that both the collapse characteristics and the leakage current characteristics of the heterojunction FET can be improved when the density is 10 ¹² / cm ² or less.

  4 and 5, black diamonds indicate the case where silicon nitride is used as the collapse suppression film 3 and silicon nitride is used as the insulating film 4, and the white triangles indicate Si-rich silicon nitride as the collapse suppression film 3. A case where a silicon oxide film is used as the insulating film 4 is shown, and an oblique cross indicates a case where an AlN film is used as the collapse suppression film 3 and a silicon oxide film is used as the insulating film 4.

<Influence of oxygen concentration in semiconductor layer>
FIG. 6 is a graph showing the influence of the oxygen concentration contained in the GaN channel layer 1 on the sheet carrier concentration in the heterojunction FET of FIG. That is, the horizontal axis of the graph of FIG. 6 represents the atomic concentration (%) of oxygen with respect to Ga, and the vertical axis represents the sheet carrier concentration ratio with the sheet carrier concentration Ns at an oxygen concentration of 0.37% as a reference. Yes. FIG. 6 shows that the sheet carrier concentration can be increased by increasing the oxygen concentration in the GaN channel layer 1. Therefore, Ns in the second region near the gate electrode can be set to a desired value by adjusting the Al concentration of the AlGaN layer, and Ns in the first region near the drain electrode can be increased by increasing the oxygen concentration. .

  FIG. 7 is a bar graph showing the effect of exposing the AlGaN barrier layer surface of the heterojunction FET of FIG. 1 to oxygen plasma. The bar A in this graph indicates the sheet carrier concentration in the channel layer when not exposed to oxygen plasma as a reference 1, and the bar B indicates the ratio of the sheet carrier concentration when exposed to oxygen plasma. . FIG. 7 shows that the sheet carrier concentration in the GaN channel layer can be increased by exposing the surface of the semiconductor layer of the heterojunction FET to oxygen plasma.

  That is, between the drain electrode D and the gate electrode G, the first region close to the drain electrode is exposed and the second region close to the gate electrode is covered with a protective mask and exposed to oxygen plasma in the first region. The oxygen concentration in the channel layer 1 can be increased, whereby the sheet carrier concentration Ns can be increased.

  In the following, an example of a method for manufacturing a heterojunction FET in which the sheet carrier concentration Ns is adjusted using oxygen plasma will be described.

(Formation of nitride semiconductor laminate)
First, an undoped GaN layer 1 and an undoped AlGaN layer 2 are formed in this order on a Si substrate not shown in FIG. 1 using MOCVD (metal organic chemical vapor deposition). These undoped GaN layer 1 and undoped AlGaN layer 2 constitute a nitride semiconductor stacked body.

(Plasma exposure)
A photoresist layer (not shown) is formed on the undoped AlGaN layer 2, and the photoresist layer on the region to be exposed to oxygen plasma is removed by exposure and development. Thereafter, the surface of the undoped AlGaN layer 2 is exposed to oxygen plasma. At this time, a plasma output of 1000 W and an exposure time of 4 minutes can be adopted as a preferred example, but the plasma output and the exposure time are appropriately adjusted and set according to the desired oxygen concentration.

(Formation of surface film and electrode)
A collapse suppression film 3 is formed on the undoped AlGaN layer 2 using a plasma CVD method. A preferred example of the growth temperature of the collapse suppression film 3 is 225 ° C., but can be set within a range of 200 ° C. to 400 ° C. Moreover, although a preferable example of the collapse suppression film | membrane 3 is 30 nm, it can set within the range of 20 nm-250 nm.

The collapse suppression film 3 is any one of a silicon nitride film rich in Si compared to Si ₃ N ₄ having a stoichiometric composition, a silicon nitride film close to Si ₃ N ₄ having a stoichiometric composition, or a silicon oxide film. Can be used. Alternatively, a SiON film or a SiOC film can be used as the collapse suppression film 3. Furthermore, an AlN film can be used as the collapse suppression film 3. However, since the single crystal AlN film affects the two-dimensional electron gas, the collapse suppression film 3 is preferably a polycrystalline AlN film or an amorphous AlN film. Here, current collapse is particularly noticeable in a GaN-based semiconductor device, and is a phenomenon in which the on-resistance of a transistor in high-voltage operation is significantly higher than the on-resistance of the transistor in low-voltage operation. It is.

On the collapse suppression film 3, the insulating film 4 can be formed by plasma CVD. The insulating film 4 is either a silicon nitride film rich in Si compared to Si ₃ N ₄ having a stoichiometric composition, a silicon nitride film close to Si ₃ N ₄ having a stoichiometric composition, or a silicon oxide film. Can be used. Alternatively, a SiON film or a SiOC film can be used as the insulating film 4. Furthermore, an AlN film can be used as the insulating film 4. Alternatively, a combination of two or more of an AlN film, a SiON film, a SiOC film, a silicon oxide film, or a silicon nitride film can be used as the insulating film 4.

  A photoresist layer (not shown) is formed on the insulating film 4, and the photoresist layer on the region where the gate electrode G is to be formed is removed by exposure and development, and the remaining photoresist layer is removed. Dry etching is performed as a mask. Thus, in the region where the gate electrode G is to be formed, the insulating film 4 and the collapse suppression film 3 are removed, and the undoped AlGaN layer 2 is exposed.

  Thereafter, the insulating film 4 is heat-treated. This heat treatment can be performed, for example, at 500 ° C. for 30 minutes. In addition, the temperature of this heat processing can be set within the range of 500 degreeC-750 degreeC, and the heat processing time can also be set suitably.

  After the heat treatment, a TiN film is formed on the entire surface by sputtering, and a resist pattern (not shown) is formed by photolithography in a region where the gate electrode G is to be formed. Using this resist pattern as a mask, dry etching or wet etching is performed to remove the TiN film other than the formation region of the gate electrode G, and the gate electrode G made of TiN is formed as shown in FIG.

  Thereafter, openings are formed in regions where the source electrode S and the drain electrode D are to be formed by photolithography and etching, and the undoped AlGaN layer 2 is exposed. Subsequently, a photoresist (not shown) having an opening in a region where the source electrode S and the drain electrode D are to be formed (a region where the undoped AlGaN layer 2 is exposed) is formed by photolithography. Ti and Al are vapor-deposited in this order so as to cover the opening, and a source electrode S and a drain electrode D are formed by Ti / Al lamination on the undoped AlGaN layer 2 by lift-off. The source electrode S and the drain electrode D are made ohmic electrodes by heat treatment. A preferable example of the heat treatment conditions for the ohmicization is 30 minutes at 500 ° C., but the heat treatment temperature can be set within a range of 400 ° C. to 600 ° C., and the heat treatment time can be appropriately set.

<Influence of GaN cap layer>
The heterojunction FET as shown in FIG. 1 can additionally include a GaN cap layer on the AlGaN barrier layer 2. Such a GaN cap layer can act to suppress oxidation of the AlGaN barrier layer 2 containing Al or prevent impurities from being taken in.

  FIG. 8 shows a part of an example of the heterojunction FET in a schematic cross-sectional view similar to FIG. 1, but the heterojunction FET of FIG. 8 is additionally provided between the AlGaN barrier layer 2 and the collapse suppression film 3. A GaN cap layer 5 is included. The GaN cap layer 5 can be typically set to a thickness of 1 nm.

  Thus, in the heterojunction FET including the GaN cap layer 5, the thickness of the GaN cap layer 5 can be reduced as a method for increasing the sheet carrier concentration Ns in the first region from the drain end to the distance X. It is.

  Table 1 shows the influence of the thickness of the GaN cap layer 5 on the sheet carrier concentration Ns in the GaN channel layer 1. Regarding Table 1, the Ns value was obtained by a relatively simple calculation based on a so-called capacitance model in which the dielectric constant and thickness of each semiconductor layer are variables. Also, in Table 1, the Ns ratio in the GaN channel layer 1 depending on the thickness of the cap layer, with the Ns value in the GaN channel layer 1 when the thickness of the cap layer is 10 mm (1 nm) as a reference 1. Is shown.

  As apparent from Table 1, it can be seen that the sheet carrier concentration Ns in the GaN channel layer can be increased by reducing the thickness of the GaN cap layer. Therefore, as shown in FIG. 8, by reducing or removing the thickness of the GaN cap layer 5 in the first region indicated by the oval mark near the drain electrode D, The sheet carrier concentration Ns can be increased compared to the second region on the gate electrode side.

  In the following, an example of a method for manufacturing a heterojunction FET in which the sheet carrier concentration Ns is adjusted using a cap layer will be described.

(Formation of semiconductor stack)
First, an undoped GaN layer 1 and an undoped AlGaN layer 2 are formed in this order on a Si substrate (not shown) using MOCVD. Subsequently, a GaN cap layer 5 is formed on the undoped AlGaN layer 2. A preferred example of the thickness of the GaN cap layer 5 is 1 nm, but can be set within a range of 0.5 nm to 5 nm. These undoped GaN layer 1, undoped AlGaN layer 2 and GaN cap layer 5 constitute a nitride semiconductor multilayer body.

(Adjustment of cap layer thickness)
A photoresist layer (not shown) is formed on the GaN cap layer, exposed and developed to remove the photoresist layer on the first region from the drain end to the distance X, and the remaining photoresist layer Is used as a mask to reduce or remove the thickness of the GaN cap layer 5 on the first region.

  Thereafter, the surface film and the electrodes can be formed in the same manner as in the case of the heterojunction FET manufactured using the oxygen plasma described above.

  In the above description of the embodiment, the Si substrate is used as the substrate, but a sapphire substrate or a SiC substrate may be used. A nitride semiconductor layer may be grown on a substrate made of a nitride semiconductor, such as growing an AlGaN layer on a GaN substrate. If desired, a buffer layer may be formed between the substrate and the nitride semiconductor stack. Further, a heterojunction improving layer made of an AlN layer having a thickness of, for example, about 1 nm may be formed between the GaN layer and the AlGaN layer.

  In the description of the above embodiment, the gate electrode G is made of TiN. However, the gate electrode G may be made of WN, or may be made of a stacked layer of Pt / Au or Ni / Au. Although the gate electrode G has been described as having a Schottky junction with respect to the AlGaN barrier layer 2, it may be fabricated as a MIS (metal / insulator / semiconductor) structure including a gate insulating film. Furthermore, the heterojunction FET can also be manufactured to have a recessed gate structure including a gate electrode formed in a recess on the surface of the semiconductor stacked body.

  In the above embodiment, the source electrode S and the drain electrode D as ohmic electrodes have been described as Ti / Al electrodes in which a Ti layer and an Al layer are sequentially stacked. However, a Ti layer, an Al layer, and a TiN layer are sequentially stacked. A / Al / TiN electrode may be used. An AlSi layer or an AlCu layer may be used instead of the Al layer. Further, the source electrode S and the drain electrode D may be Hf / Al electrodes, or Ni / Au may be laminated on Ti / Al or Hf / Al, and Pt / Au on Ti / Al or Hf / Al. It may be a laminate of Au and a laminate of Au on Ti / Al or Hf / Al.

  Although specific embodiments of the present invention have been described above, the present invention is not limited to the above-described embodiments, and various modifications can be made within the scope of the present invention.

  As described above, according to the present invention, it is possible to provide a heterojunction FET in which both current leakage characteristics and current collapse characteristics are improved.

  1 GaN channel layer, 2 AlGaN barrier layer, 3 collapse suppression film, 4 insulating film, 5 GaN cap layer, D drain electrode, G gate electrode, S source electrode.

Claims (5)

A heterojunction FET,
A GaN channel layer;
An AlGaN barrier layer stacked on the channel layer;
A source electrode and a drain electrode that are in ohmic contact with the channel layer;
A gate electrode formed on the barrier layer between the source electrode and the drain electrode,
The interface of the channel layer in contact with the barrier layer has a relatively high sheet carrier between the drain electrode and the gate electrode within the first region of 0.5% or more within 30% close to the drain electrode. A heterojunction FET having a concentration and having a relatively low sheet carrier concentration in a second region excluding the first region close to the gate electrode. It has a sheet carrier concentration of 6.3 × 10 ¹² / cm ² or more in the first region, and a sheet carrier concentration of 5.6 × 10 ¹² / cm ² or less in the second region. The heterojunction FET according to claim 1.   The method further comprises a GaN cap layer stacked on the barrier layer, wherein the cap layer has a thickness reduced or removed above the first region as compared to above the second region. The heterojunction FET according to claim 1 or 2.   3. The heterojunction FET according to claim 1, wherein the first region contains a higher concentration of oxygen than the second region. 4. A method for producing a heterojunction FET according to claim 4,
A method of manufacturing a heterojunction FET, wherein the first region is exposed to oxygen plasma while the second region is covered with a resist.

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