JP2017037672A5 - - Google Patents

Download PDF

Info

Publication number
JP2017037672A5
JP2017037672A5 JP2016207724A JP2016207724A JP2017037672A5 JP 2017037672 A5 JP2017037672 A5 JP 2017037672A5 JP 2016207724 A JP2016207724 A JP 2016207724A JP 2016207724 A JP2016207724 A JP 2016207724A JP 2017037672 A5 JP2017037672 A5 JP 2017037672A5
Authority
JP
Japan
Prior art keywords
state update
address space
management unit
memory management
entry
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP2016207724A
Other languages
English (en)
Other versions
JP2017037672A (ja
JP6378733B2 (ja
Filing date
Publication date
Priority claimed from US13/191,327 external-priority patent/US9916257B2/en
Application filed filed Critical
Publication of JP2017037672A publication Critical patent/JP2017037672A/ja
Publication of JP2017037672A5 publication Critical patent/JP2017037672A5/ja
Application granted granted Critical
Publication of JP6378733B2 publication Critical patent/JP6378733B2/ja
Expired - Fee Related legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Claims (13)

  1. スレッドをアクティベートするステート更新リクエストをメモリ管理ユニットに発行するデバイスを備え、
    前記メモリ管理ユニットは、前記スレッドに対応するアドレス空間のエントリの修正を実行し、前記ステート更新リクエストに対しデバイス同期フラグを設定する、システム。
  2. 前記メモリ管理ユニットはIOMMUである、請求項1に記載のシステム。
  3. 前記メモリ管理ユニットは、ステート更新応答を用いて前記ステート更新リクエストに応答する、請求項1または2に記載のシステム。
  4. 前記デバイスは、非中央処理ユニットデバイスである、請求項1〜3の何れか一項に記載のシステム。
  5. 前記アドレス空間は、プロセスアドレス空間識別子(PASID)を用いて識別される、請求項1〜4の何れか一項に記載のシステム。
  6. 前記アドレス空間のエントリはIOTLB内のエントリに対応する、請求項1〜5の何れか一項に記載のシステム。
  7. 前記デバイスは、前記スレッドのアクティベーションの前に、前記ステート更新応答に応じてTLBエントリを同期する、請求項3、または、請求項3に従属する請求項4〜6の何れか一項に記載のシステム。
  8. スレッドを非アクティベートするステート更新リクエストをメモリ管理ユニットに発行するデバイスを備え、
    前記メモリ管理ユニットは、前記スレッドに対応するアドレス空間のエントリの修正を実行し、前記ステート更新リクエストに対しデバイス同期フラグを設定する、システム。
  9. 前記メモリ管理ユニットはIOMMUである、請求項8に記載のシステム。
  10. 前記メモリ管理ユニットは、ステート更新応答を用いて前記ステート更新リクエストに応答する、請求項8または9に記載のシステム。
  11. 前記デバイスは、非中央処理ユニットデバイスである、請求項8〜10の何れか一項に記載のシステム。
  12. 前記アドレス空間は、プロセスアドレス空間識別子(PASID)を用いて識別される、請求項8〜11の何れか一項に記載のシステム。
  13. 前記アドレス空間のエントリはIOTLB内のエントリに対応する、請求項8〜12の何れか一項に記載のシステム。
JP2016207724A 2011-07-26 2016-10-24 共有仮想メモリをサポートする異種コンピュータシステムにおけるtlbシュートダウンの方法および装置 Expired - Fee Related JP6378733B2 (ja)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US13/191,327 US9916257B2 (en) 2011-07-26 2011-07-26 Method and apparatus for TLB shoot-down in a heterogeneous computing system supporting shared virtual memory
US13/191,327 2011-07-26

Related Parent Applications (1)

Application Number Title Priority Date Filing Date
JP2014522944A Division JP6032855B2 (ja) 2011-07-26 2012-07-24 共有仮想メモリをサポートする異種コンピュータシステムにおけるtlbシュートダウンの方法および装置

Publications (3)

Publication Number Publication Date
JP2017037672A JP2017037672A (ja) 2017-02-16
JP2017037672A5 true JP2017037672A5 (ja) 2017-03-23
JP6378733B2 JP6378733B2 (ja) 2018-08-22

Family

ID=47425977

Family Applications (2)

Application Number Title Priority Date Filing Date
JP2014522944A Expired - Fee Related JP6032855B2 (ja) 2011-07-26 2012-07-24 共有仮想メモリをサポートする異種コンピュータシステムにおけるtlbシュートダウンの方法および装置
JP2016207724A Expired - Fee Related JP6378733B2 (ja) 2011-07-26 2016-10-24 共有仮想メモリをサポートする異種コンピュータシステムにおけるtlbシュートダウンの方法および装置

Family Applications Before (1)

Application Number Title Priority Date Filing Date
JP2014522944A Expired - Fee Related JP6032855B2 (ja) 2011-07-26 2012-07-24 共有仮想メモリをサポートする異種コンピュータシステムにおけるtlbシュートダウンの方法および装置

Country Status (9)

Country Link
US (1) US9916257B2 (ja)
JP (2) JP6032855B2 (ja)
KR (1) KR101604929B1 (ja)
CN (2) CN103827839B (ja)
DE (1) DE202012007252U1 (ja)
GB (1) GB2506788B (ja)
IN (1) IN2014CN00386A (ja)
TW (1) TWI489278B (ja)
WO (1) WO2013016345A2 (ja)

Families Citing this family (32)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20150149446A1 (en) * 2012-07-27 2015-05-28 Freescale Semiconductor, Inc. Circuitry for a computing system and computing system
CN104956347B (zh) * 2013-02-28 2018-05-22 英特尔公司 将一种互连协议的枚举和/或配置机制用于不同的互连协议
US9223690B2 (en) * 2013-10-04 2015-12-29 Sybase, Inc. Freeing memory safely with low performance overhead in a concurrent environment
US9411745B2 (en) 2013-10-04 2016-08-09 Qualcomm Incorporated Multi-core heterogeneous system translation lookaside buffer coherency
US9785554B2 (en) 2014-05-30 2017-10-10 International Business Machines Corporation Synchronizing updates of page table status indicators in a multiprocessing environment
US9384133B2 (en) * 2014-05-30 2016-07-05 International Business Machines Corporation Synchronizing updates of page table status indicators and performing bulk operations
US20160098203A1 (en) * 2014-12-18 2016-04-07 Mediatek Inc. Heterogeneous Swap Space With Dynamic Thresholds
CN105846859B (zh) * 2015-01-12 2019-05-24 芋头科技(杭州)有限公司 一种嵌入式操作系统实现蓝牙从设备功能的系统及方法
EP3054384B1 (en) * 2015-02-04 2018-06-27 Huawei Technologies Co., Ltd. System and method for memory synchronization of a multi-core system
WO2016206012A1 (en) * 2015-06-24 2016-12-29 Intel Corporation Systems and methods for isolating input/output computing resources
WO2017049590A1 (en) * 2015-09-25 2017-03-30 Intel Corporation Systems and methods for input/output computing resource control
US9898226B2 (en) * 2015-10-28 2018-02-20 International Business Machines Corporation Reducing page invalidation broadcasts in virtual storage management
US10942683B2 (en) 2015-10-28 2021-03-09 International Business Machines Corporation Reducing page invalidation broadcasts
US9892024B2 (en) * 2015-11-02 2018-02-13 Sony Interactive Entertainment America Llc Backward compatibility testing of software in a mode that disrupts timing
US10386904B2 (en) 2016-03-31 2019-08-20 Qualcomm Incorporated Hardware managed power collapse and clock wake-up for memory management units and distributed virtual memory networks
US10120814B2 (en) * 2016-04-01 2018-11-06 Intel Corporation Apparatus and method for lazy translation lookaside buffer (TLB) coherence
US10067870B2 (en) 2016-04-01 2018-09-04 Intel Corporation Apparatus and method for low-overhead synchronous page table updates
US10540292B2 (en) 2016-06-08 2020-01-21 Google Llc TLB shootdowns for low overhead
GB2551226A (en) * 2016-06-08 2017-12-13 Google Inc TLB shootdowns for low overhead
US10282308B2 (en) * 2016-06-23 2019-05-07 Advanced Micro Devices, Inc. Method and apparatus for reducing TLB shootdown overheads in accelerator-based systems
US20180276175A1 (en) 2017-03-22 2018-09-27 National Instruments Corporation Direct Network Access by a Memory Mapped Peripheral Device for Scheduled Data Transfer on the Network
CN108932213A (zh) * 2017-10-10 2018-12-04 北京猎户星空科技有限公司 多操作系统间的通讯方法、装置、电子设备和存储介质
US10725932B2 (en) 2017-11-29 2020-07-28 Qualcomm Incorporated Optimizing headless virtual machine memory management with global translation lookaside buffer shootdown
US10990436B2 (en) * 2018-01-24 2021-04-27 Dell Products L.P. System and method to handle I/O page faults in an I/O memory management unit
US11106613B2 (en) 2018-03-29 2021-08-31 Intel Corporation Highly scalable accelerator
US10846235B2 (en) 2018-04-28 2020-11-24 International Business Machines Corporation Integrated circuit and data processing system supporting attachment of a real address-agnostic accelerator
DE102018004086A1 (de) 2018-05-18 2019-11-21 Singulus Technologies Ag Durchlaufanlage und Verfahren zum Beschichten von Substraten
KR102655094B1 (ko) * 2018-11-16 2024-04-08 삼성전자주식회사 메모리를 공유하는 이종의 프로세서들을 포함하는 스토리지 장치 및 그것의 동작 방법
US11036649B2 (en) 2019-04-04 2021-06-15 Cisco Technology, Inc. Network interface card resource partitioning
CN110968530B (zh) * 2019-11-19 2021-12-03 华中科技大学 一种基于非易失性内存的键值存储系统和内存访问方法
US12086082B2 (en) 2020-09-21 2024-09-10 Intel Corporation PASID based routing extension for scalable IOV systems
CN116594925B (zh) * 2023-04-24 2024-09-27 上海天数智芯半导体有限公司 一种地址转换系统、处理器、地址转换方法及电子设备

Family Cites Families (19)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH02183849A (ja) * 1989-01-11 1990-07-18 Fujitsu Ltd アドレス対応表無効化処理方式
JPH06139149A (ja) * 1992-10-29 1994-05-20 Mitsubishi Electric Corp 多重仮想空間制御装置
US6175876B1 (en) 1998-07-09 2001-01-16 International Business Machines Corporation Mechanism for routing asynchronous state changes in a 3-tier application
US6779049B2 (en) * 2000-12-14 2004-08-17 International Business Machines Corporation Symmetric multi-processing system with attached processing units being able to access a shared memory without being structurally configured with an address translation mechanism
US7111145B1 (en) 2003-03-25 2006-09-19 Vmware, Inc. TLB miss fault handler and method for accessing multiple page tables
US7073043B2 (en) * 2003-04-28 2006-07-04 International Business Machines Corporation Multiprocessor system supporting multiple outstanding TLBI operations per partition
US7552254B1 (en) * 2003-07-30 2009-06-23 Intel Corporation Associating address space identifiers with active contexts
US7093100B2 (en) * 2003-11-14 2006-08-15 International Business Machines Corporation Translation look aside buffer (TLB) with increased translational capacity for multi-threaded computer processes
US7069389B2 (en) 2003-11-26 2006-06-27 Microsoft Corporation Lazy flushing of translation lookaside buffers
US7562179B2 (en) * 2004-07-30 2009-07-14 Intel Corporation Maintaining processor resources during architectural events
US7376807B2 (en) 2006-02-23 2008-05-20 Freescale Semiconductor, Inc. Data processing system having address translation bypass and method therefor
US7555628B2 (en) * 2006-08-15 2009-06-30 Intel Corporation Synchronizing a translation lookaside buffer to an extended paging table
US7917725B2 (en) 2007-09-11 2011-03-29 QNX Software Systems GmbH & Co., KG Processing system implementing variable page size memory organization using a multiple page per entry translation lookaside buffer
US8386745B2 (en) * 2009-07-24 2013-02-26 Advanced Micro Devices, Inc. I/O memory management unit including multilevel address translation for I/O and computation offload
US9535849B2 (en) 2009-07-24 2017-01-03 Advanced Micro Devices, Inc. IOMMU using two-level address translation for I/O and computation offload devices on a peripheral interconnect
US8364902B2 (en) 2009-08-07 2013-01-29 Via Technologies, Inc. Microprocessor with repeat prefetch indirect instruction
US8719547B2 (en) 2009-09-18 2014-05-06 Intel Corporation Providing hardware support for shared virtual memory between local and remote physical memory
US20130179971A1 (en) 2010-09-30 2013-07-11 Hewlett-Packard Development Company, L.P. Virtual Machines
JP5956754B2 (ja) 2012-01-06 2016-07-27 株式会社荏原製作所 真空排気システム

Similar Documents

Publication Publication Date Title
JP2017037672A5 (ja)
JP2015127901A5 (ja)
MY188909A (en) Programmable memory transfer request processing units
WO2017117321A3 (en) Systems, methods, and apparatuses for range protection
WO2016044270A3 (en) Paging of external memory
CL2015000917A1 (es) Método de aprendizaje de hardware de dirección mac, que comprende calcular clave hash en base a id de mensaje y mac origen, buscar clave en memoria ternaria (tcam), determinar si la bandera de datos tcam está establecida, comparar valores de puertos de conmutador virtual, actualizar el puerto del conmutador virtual tcam, determinar si la bandera de datos hash está establecida, almacenar la dirección mac de origen del mensaje, comparar id y dirección mac; sistema asociado
WO2016033039A3 (en) Routing direct memory access requests in a virtualized computing environment
GB2555340A (en) Protection of sensitive data
BR112017002136A2 (pt) ?sistema de dispositivo eletrônico?
WO2014001913A3 (en) Systems and methods for multi-path control signals for media presentation devices
JP2016520892A5 (ja)
TW201612755A (en) Hybrid memory cube system interconnect directory-based cache coherence methodology
JP2015053052A5 (ja)
JP2013257911A5 (ja) プロセッサ
WO2013016345A3 (en) Method and apparatus for tlb shoot-down in a heterogeneous computing system supporting shared virtual memory
JP2013065296A5 (ja) 領域記述子グローバル化制御を有するメモリ管理ユニット
EP3480702A4 (en) MEMORY ACCESS TECHNOLOGY AND COMPUTER SYSTEM
WO2016167980A3 (en) Virtual machine systems
WO2014150815A3 (en) System and method to dynamically determine a timing parameter of a memory device
EP3899719A4 (en) VIRTUALIZATION OF PROCESS ADDRESS SPACE IDENTIFIERS USING HARDWARE PALL INDICATORS
WO2015066423A3 (en) Systems, apparatus, and methods for providing state updates in a mesh network
WO2014182314A3 (en) Acceleration of memory access
JP2019176306A5 (ja)
JP2016054788A5 (ja)
JP2018501609A5 (ja)