IN2014CN00386A - - Google Patents

Info

Publication number
IN2014CN00386A
IN2014CN00386A IN386CHN2014A IN2014CN00386A IN 2014CN00386 A IN2014CN00386 A IN 2014CN00386A IN 386CHN2014 A IN386CHN2014 A IN 386CHN2014A IN 2014CN00386 A IN2014CN00386 A IN 2014CN00386A
Authority
IN
India
Prior art keywords
state
entries
pasid
tlb
management unit
Prior art date
Application number
Inventor
Rajesh M Sankaran
Altug Koker
Philip Lantz
Asit K Mallick
James B Crossland
Aditva Navale
Gilbert Neiger
Andrew V Anderson
Original Assignee
Intel Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Intel Corp filed Critical Intel Corp
Publication of IN2014CN00386A publication Critical patent/IN2014CN00386A/en

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/10—Address translation
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/10—Address translation
    • G06F12/1027—Address translation using associative or pseudo-associative address translation means, e.g. translation look-aside buffer [TLB]
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F15/00—Digital computers in general; Data processing equipment in general
    • G06F15/76—Architectures of general purpose stored program computers
    • G06F15/80—Architectures of general purpose stored program computers comprising an array of processing units with common control, e.g. single instruction multiple data processors
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/10—Address translation
    • G06F12/1081—Address translation for peripheral access to main memory, e.g. direct memory access [DMA]
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2212/00—Indexing scheme relating to accessing, addressing or allocation within memory systems or architectures
    • G06F2212/10—Providing a specific technical effect
    • G06F2212/1016—Performance improvement
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2212/00—Indexing scheme relating to accessing, addressing or allocation within memory systems or architectures
    • G06F2212/10—Providing a specific technical effect
    • G06F2212/1048—Scalability
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2212/00—Indexing scheme relating to accessing, addressing or allocation within memory systems or architectures
    • G06F2212/30—Providing cache or TLB in specific location of a processing system
    • G06F2212/303—In peripheral interface, e.g. I/O adapter or channel
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2212/00—Indexing scheme relating to accessing, addressing or allocation within memory systems or architectures
    • G06F2212/68—Details of translation look-aside buffer [TLB]
    • G06F2212/682—Multiprocessor TLB consistency
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2212/00—Indexing scheme relating to accessing, addressing or allocation within memory systems or architectures
    • G06F2212/68—Details of translation look-aside buffer [TLB]
    • G06F2212/683—Invalidation

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Computing Systems (AREA)
  • Memory System Of A Hierarchy Structure (AREA)

Abstract

Methods and apparatus are disclosed for efficient TLB (translation look aside buffer) shoot downs for heterogeneous devices sharing virtual memory in a multi core system. Embodiments of an apparatus for efficient TLB shoot downs may include a TLB to store virtual address translation entries and a memory management unit coupled with the TLB to maintain PASID (process address space identifier) state entries corresponding to the virtual address translation entries. The PASID state entries may include an active reference state and a lazy invalidation state. The memory management unit may perform atomic modification of PASID state entries responsive to receiving PASID state update requests from devices in the multi core system and read the lazy invalidation state of the PASID state entries. The memory management unit may send PASID state update responses to the devices to synchronize TLB entries prior to activation responsive to the respective lazy invalidation state.
IN386CHN2014 2011-07-26 2012-07-24 IN2014CN00386A (en)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US13/191,327 US9916257B2 (en) 2011-07-26 2011-07-26 Method and apparatus for TLB shoot-down in a heterogeneous computing system supporting shared virtual memory
PCT/US2012/047991 WO2013016345A2 (en) 2011-07-26 2012-07-24 Method and apparatus for tlb shoot-down in a heterogeneous computing system supporting shared virtual memory

Publications (1)

Publication Number Publication Date
IN2014CN00386A true IN2014CN00386A (en) 2015-04-03

Family

ID=47425977

Family Applications (1)

Application Number Title Priority Date Filing Date
IN386CHN2014 IN2014CN00386A (en) 2011-07-26 2012-07-24

Country Status (9)

Country Link
US (1) US9916257B2 (en)
JP (2) JP6032855B2 (en)
KR (1) KR101604929B1 (en)
CN (2) CN106776379B (en)
DE (1) DE202012007252U1 (en)
GB (1) GB2506788B (en)
IN (1) IN2014CN00386A (en)
TW (1) TWI489278B (en)
WO (1) WO2013016345A2 (en)

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Also Published As

Publication number Publication date
TW201333700A (en) 2013-08-16
KR101604929B1 (en) 2016-03-18
JP6378733B2 (en) 2018-08-22
CN106776379A (en) 2017-05-31
GB201400358D0 (en) 2014-02-26
CN106776379B (en) 2021-09-07
TWI489278B (en) 2015-06-21
US9916257B2 (en) 2018-03-13
GB2506788B (en) 2020-05-27
CN103827839A (en) 2014-05-28
JP6032855B2 (en) 2016-11-30
JP2017037672A (en) 2017-02-16
JP2014526102A (en) 2014-10-02
WO2013016345A2 (en) 2013-01-31
US20130031333A1 (en) 2013-01-31
GB2506788A (en) 2014-04-09
KR20140028137A (en) 2014-03-07
CN103827839B (en) 2016-12-21
DE202012007252U1 (en) 2012-11-29
WO2013016345A3 (en) 2013-04-11

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