JPH02183849A - Invalidation processing system for address correspondence table - Google Patents

Abstract

PURPOSE:To invalidate a correspondence table at a high speed by securing such a constitution where a processor received an inter-CPU instruction invalidates the correspondence table based on the contents of an invalidated address memory area as long as all action state display flags are kept in pause. CONSTITUTION:The action state display flags 170 corresponding to each CPU and an invalidated address memory area 108 for a correspondence table and added to a specific area of a main storage. The instructions which are carried out by the CPU include a correspondence invalidating instruction which invalidates a part or the whole of the correspondence stored in the correspondence table without stopping the operations of other CPUs and an inter-CPU instruction which instructs the pause of operations to other CPU. Then the correspondence is immediately invalidated with a correspondence invalidating instruction in case other CPUs have no possibility of application. Only in case other CPU have possibility of application, the invalidation is performed after the CPU are set in pause with use of an inter-CPU instruction. As a result, the executing time is shortened for a correspondence invalidating instruction and the overall system process efficiency is improved.

Description

[Detailed Description of the Invention] [Summary] Regarding an information processing system that has a main memory that is commonly accessed by a plurality of central processing units and a correspondence table that stores correspondence between logical addresses and real addresses, invalidation of the correspondence table is provided. For the purpose of quickly performing
a correspondence invalidation instruction that provides an operating state display flag corresponding to each central processing unit and an invalidation address storage area for the correspondence table, and invalidates the correspondence table without stopping the processing of other central processing units; In addition to defining an inter-central processing unit command that instructs other central processing units to pause, each central processing unit invalidates the contents of the correspondence table regarding areas that cannot be used by other central processing units. in case of,
When executing the correspondence invalidation instruction to invalidate the contents of the correspondence table regarding areas that may be used by other central processing units, information regarding the address to be invalidated is stored in the invalidation address storage area. , suspends its own central processing unit and displays the corresponding flag in a stopped state, and sends the inter-central processing unit command to another predetermined central processing unit, and the other processing unit that has received the command Then, my 'Wt8
and display the corresponding flag in the dormant state, and if all the operating status display flags are not in the dormant state,
If the inter-device command is further sent to another predetermined central processing unit, and all the operating state display flags are in the dormant state,
The correspondence table is invalidated according to the contents of the invalidation address storage area.

[Industrial application field]

The present invention relates to a method for invalidating entries in an address correspondence table (such as a page table) that stores the correspondence between logical addresses and real addresses used in dynamic address translation.

[Conventional technology]

In an information processing system in which multiple central processing units (hereinafter referred to as CPUs) use a common main storage unit (hereinafter referred to as MSU), a certain CPU conventionally stores a logical address and an MSU.
The instruction to invalidate the page table entry (hereinafter abbreviated as PTE) in the page table (hereinafter abbreviated as PT) that stores the correspondence with the above real address is l f
There is only the li class, and when executing the instruction, other CPUs
The PTE was disabled after stopping all processes being performed by the PTE. This means that other CPUs can use that P T [!
.

This is because there is a possibility that the data of the address corresponding to is being used. Also, at that time, for all CPUs, the P
Translation lookaside for TE
Entries in the buffer (hereinafter abbreviated as TLB) are also invalidated.

Therefore, the processing of the CPU is stopped at the end of an instruction, that is, after the execution of the current instruction is finished and before the next instruction is executed.

FIG. 3 is a block diagram of a conventional device for disabling PTE, and FIG. 4 is a processing flowchart of a PTE disabling command (hereinafter abbreviated as IPTE command).

In Figure 3, 31 is the operating system (hereinafter referred to as
32 is an instruction analysis unit, 33 is a specified data change unit, 34 is another CPU stop request control unit, 35 is an entry invalidation control unit, 36 is 1゛LB, 37 is MSIJ, 3
8 is a main memory control unit (hereinafter abbreviated as MCU), 39 is C
Inter-PU communication section, 301 to 304 are CPUs
, 307 is l) T. Although any number of CPUs may be installed, here, it is assumed that the system is composed of four CPUs.

The conventional technology will be described below with reference to the drawings.

When an event requiring invalidation of PTH occurs, an IPTE command is issued to the command analysis unit 32 from 0331.

When the PTE instruction is analyzed by the instruction analysis unit 32, the designated data check unit 33 checks whether the address of the page to be invalidated stored in the instruction is correct (see the flowchart in FIG. 4). 41). Here, it is checked whether the address points to the top of the page.

Next, the other CPU stop request control unit 34
In order to stop CPUs 02 to 304, other CPUs
302, 303, and 304 (see flowchart 42 in FIG. 4).

After that, it is checked whether there is a notification of stoppage from the CPUs 302, 303, and 304 (Fig. 4 Flowchart
(see 2). At this time, each CPU finishes the current instruction,
Stop before executing the next instruction.

After all CPUs have stopped, the entry invalidation control unit 35 invalidates the PTE specified by the IPTE instruction in Pr2O3. Furthermore, in each of the CPUs 301 to 304, the entry in the TLB corresponding to the PTE that has been invalidated by each CPU is also invalidated.

[Problem to be solved by the invention]

Conventionally, in an information processing system in which a plurality of CPUs use a common MSU, when an entry is invalidated, all CPUs are always stopped before the invalidation process is performed.

This is because there is a possibility that another CPU is using the data at the address corresponding to the specified PTE, and if the PTE is invalidated while that CPU is executing an instruction, the This is because the process may end abnormally and be interrupted.

However, depending on the instructions being executed by the CPU, some instructions take a considerable amount of time, and other CPUs are forced to wait until the instructions are completed. Furthermore, if the number of CPUs increases, it will take a long time for all CPUs to stop.

In recent years, there has been a strong demand for improving the processing execution speed of information processing systems, and therefore, it is important to perform PTH invalidation processing quickly.Therefore, the present invention This method solves all problems and provides a means for speeding up the invalidation process of PT entries.

[Means to solve problems]

A specific area of the main storage device is provided with an operating state display flag corresponding to each central processing unit and an invalidation address storage area of the correspondence table, and as an instruction executed by the central processing unit, an operation status display flag corresponding to each central processing unit is provided. A correspondence invalidation instruction that invalidates some or all of the correspondence stored in the correspondence table without stopping processing, and an inter-central processing unit instruction that instructs another central processing unit to stop operation. In addition, in each central processing unit, if you want to invalidate the contents of the correspondence table regarding areas that cannot be used by other central processing units,
When executing the correspondence invalidation instruction to invalidate the contents of the correspondence table regarding areas that may be used by other central processing units, information regarding the address to be invalidated is stored in the invalidation address storage area. , suspending its own central processing unit and displaying the corresponding operating state display flag in a stopped state, and sending the inter-central processing unit command to another predetermined central processing unit, and transmitting the inter-central processing unit command The other central processing unit that has received the request suspends its own central processing unit and displays the corresponding operating state display flag in the inactive state, and if all the operating state display flags are not in the inactive state, the other central processing unit The instruction is further sent to another predetermined central processing unit, and if all the operating state display flags are in the dormant state, the correspondence table is invalidated according to the contents of the invalidation address storage area.

[Operation] There are several types of events that require invalidation of a page table entry, and depending on the type, there may be no possibility that the page to be invalidated is being used by another central processing unit. Therefore, if there is no possibility of use in other central processing units, the corresponding invalidation command is used to immediately invalidate the other central processing units without stopping the other central processing units, and if there is possibility of use in other central processing units, In this case, all central processing units are put into a hibernation state using inter-central processing unit instructions, and then invalidation is performed.

As a result, the average execution time of the correspondence table invalidation process is significantly shortened.

[Embodiment] Fig. 1 is a block diagram of an embodiment of the present invention, Fig. 2 is a flowchart explaining the operation of the embodiment, and Fig. 5 is a 031
FIG. 1 is an explanatory diagram of issuing a first instruction.

In FIG. 1, 11 is an O8, 12 is an instruction analysis section, 13 is a specified data check section, 14 is another CPU stop request control section, 1
5 is entry invalidation control unit, 16 is TLB, 17 is MSU
, 18 is an MCU, 19 is an inter-CPU communication unit, 101 to 103 are CPUs, 107 is a PT, 10B is an invalidation address storage area for storing information regarding the address of the PT to be invalidated, and 170 is an indication of the operating status of each CPU. The flags 171 to 173 are cputot to 1 respectively.
03, 109 is a pointer area for identifying the cause of requiring PTE invalidation.

-a-wise, there are the following three types of events that require invalidation of PTH.

j) When the user returns the virtual area and the corresponding real page is no longer needed. This is the case when the job/task ends and the allocated area in real memory is released.

11) When expelling the entire job to an external dataset (
swap out). This is a case where the memory used by a certain job is stored in an external data center when it will not be executed for a while, and when the real memory allocated for a terminal etc. will not be used for a while, the page This is a case where the information is stored in a data set (10-DASD, etc.).

111) This is a case where there is a shortage of real pages and real pages that are rarely referenced are forcibly paged out. This means that when a task attempts to reference memory, but the page does not exist in real memory (page vault), a certain page is forcibly stored in the external storage device, and other data is This is a case where it is brought onto the located real memory.

Among the three cases above, in case of i and 11, other C
There is no possibility that PUs are using the same page. This is because the same job/task is not processed in parallel by multiple CPUs.

It is only in case ii that there is a possibility of invalidating pages used by other CPLIs, and only in this case
It is necessary to invalidate it after stopping PU processing.

In the present invention, the above IPTE instruction is an instruction to immediately invalidate the PTE without stopping other CPUs, and this IPTE instruction is used in the above cases i-ii, and in the above jj case. is a conventionally known inter-central processing unit instruction, so-called SIGP (SI
Gnal Processor) instructions to create other C
The invalidation process is performed after the PU is suspended.

FIG. 5 is an explanatory diagram of issuing the 0811 command.

Each of the above 1xij events is controlled by 03II itself, and it is naturally possible for 03II itself to understand which event it is. An example of how to understand this is shown below.

03II constantly monitors the status of each task, job, etc. Then, O8 includes an i detection routine 51, an ii detection routine 52. iii detection routine 53;
Each of cases i, ii, and iii above is detected. When any of the cases i, ii, and iii is detected, the pointer 108 of the MSU 17 (see FIG. 1)
Write to . If i or 11 is detected,
Writes “0” to the pointer 109 (54, 5
5). If 1i is detected, "1" is written (56). Then each routine
The PTE processing routine 57 is activated. Said I PTE
In the processing routine 57, the pointer 109 in the MSU 17
is read (58), and when the content is “O”, the I
Issue PTE command (60) L, 5IG when “1”
The P processing routine is activated (61).

Reference will now be made to FIGS. 1 and 2.

The I PTE instruction or the 5 IGP instruction is first executed by the CPU.
The command is input to the instruction analysis unit 12 in 10I.

When the instruction analysis section 12 detects that it is an IPTE instruction, the specified data check section 13 checks whether the address to be invalidated stored in the instruction is correct (see FIG. 2(C)). Flowchart 211). Here, it is checked whether the address points to the top of the page.

Thereafter, the entry invalidation control unit 15 controls the I P of the page table 107 in the MSU 17 via the MCUI 8.
Invalidates the PTE specified by the TE command. In addition, the entry invalidation control unit 15 issues a TLB entry invalidation request to each CPU through the inter-CPU communication unit 19. Furthermore, in each CPUI O1 to 103, the entries corresponding to the above-mentioned P T and E in the TLB of each CPU are invalidated (FIG. 2 (C) flowchart 212).

FIG. 2(a) is a flowchart of the 5IGP processing routine. First, the flag 170 in the MSU 17 is checked (21
), if it is not all “°0”°, there is a possibility that another CPU has already started the invalidation process, so all
Wait until it reaches "0°°. If all "O++", write "l" to the flag corresponding to the own CPU (22)
, stores information regarding the PTE to be invalidated in the invalidation address area 108 (23), and sends the 5 IGP command to another predetermined CPU.
9 (24). Furthermore, which CPU is which C?
It is assumed that whether or not to send the data to the PU is determined in advance according to a predetermined relationship. After that, the CPU waits until the flag 170 becomes all “0°” (25), and
When this happens, it is assumed that the PTE invalidation process has ended, and the process proceeds to the next process.

FIG. 2(b) is a processing flowchart in the CPU receiving the 5IGP instruction. 5. What is IGP command?
U is a general term for instructions for instructing other CPUs to perform processing such as reset, IPL, and stop, and in the present invention, as a type of these 5 IGP instructions, it has the function as shown in FIG. 2(b). Define the command. That is, the CPU that receives the 5IGP instruction first generates an external interrupt (201). In the case of the 5IGP instruction according to the present invention, write ``1'' to the bit corresponding to the own CPU in the flag 170 (202).
Then, it is checked whether the flags 170 are all "1" (203), and if all "11", the PTE is invalidated according to the contents of the invalidation address area 108 (203).
04L Then the flag! 70 are all cleared to "0" (205). If the flags 170 are all "0", the 5IGP command is sent to other predetermined CPUs in the same manner as described above (206), and the CPU waits until the flags 170 are all "0".

The state of waiting until the flags 170 become all "0" in this manner is called a dormant state.

As can be seen from the above, in the present invention, in the case of j11,
The CPU itself that requires PTE invalidation only suspends other CPUs using the 5IGP instruction, but does not perform any invalidation processing, and the CPU that finally receives the 5IGP instruction executes the invalidation processing. This is because the CPU that requires the invalidation itself confirms that all other CPUs have paused or stopped and then performs the invalidation process. This has the advantage of shortening the time required for invalidation processing.

In the above embodiment, invalidation of a page table entry was explained as an example, but it is of course applicable to invalidation of a segment table. In particular, the above 1 to 3 in O3
Many other methods can be considered for determining each case of j:, and the present invention is not limited to the above-mentioned determination method.

〔Effect of the invention〕

According to the present invention, when executing the correspondence invalidation instruction in the correspondence table, the processing of other CPUs is stopped only when necessary, so the execution time of the correspondence invalidation instruction itself is shortened, and Since the number of cases in which the CPU of
The processing efficiency of the entire system is significantly improved.

[Brief explanation of the drawing]

Fig. 1 is a block diagram of an embodiment of the present invention, Fig. 2 is a processing flowchart of the embodiment, Fig. 3 is a block diagram of a conventional device for disabling PTH, and Fig. 4 is a conventional IPTE
The instruction flowchart, FIG. 5, is an explanatory diagram of the issuance of the 0811 instruction. l ・ ・ ・O3 2...Instruction analysis unit 3...Specified data check unit 4...Other CPU stop request control unit 5...Entry invalidation control unit 6...TLB 7...MSU 8.・・MCU 9・・・CPU communication section O1~103・
...CPU O7...Page table 08...Invalidated address area 09...Pointer 70...Operating status display flag (a) 1st flowchart *z12] Tenmankei first row pro-tsuku diagram zprrQ command (C) Example cuff flow chart Figure 2

Claims (1)

[Scope of Claims] A plurality of central processing units (101 to 104), a main memory (17) that is commonly accessed by each of the central processing units, and a logical address corresponding to a virtual space and a memory on the main memory. In an information processing system, the information processing system has a correspondence table (107) that stores correspondences with real addresses, and converts logical addresses into real addresses by indexing the correspondence table when the central processing unit accesses a main storage device. , an operating state display flag (17) corresponding to each central processing unit is stored in a specific area of the main memory
0) and the invalidation address storage area (108
), and as an instruction executed by the central processing unit, a correspondence invalidation that invalidates part or all of the correspondence stored in the correspondence table without stopping the processing of other central processing units. In addition to defining commands and inter-central processing unit commands that instruct other central processing units to suspend operation, each central processing unit defines the contents of a correspondence table regarding areas that cannot be used by other central processing units. If you want to disable the
When executing the correspondence invalidation instruction to invalidate the contents of the correspondence table regarding areas that may be used by other central processing units, information regarding the address to be invalidated is stored in the invalidation address storage area. , suspending its own central processing unit and displaying the corresponding operating state display flag in a stopped state, and sending the inter-central processing unit command to another predetermined central processing unit, and transmitting the inter-central processing unit command The other central processing unit that has received the request suspends its own central processing unit and displays the corresponding operating state display flag in the inactive state, and if all the operating state display flags are not in the inactive state, the other central processing unit Address correspondence characterized in that the instruction is further sent to another predetermined central processing unit, and if all the operation state display flags are in a dormant state, the correspondence table is invalidated according to the contents of the invalidation address storage area. Table invalidation processing method.