JPH07105091A - Device and method for controlling cache - Google Patents

Abstract

PURPOSE:To provide a virtual computer system in the computer of multi- processor configuration, whereby the invalidation instruction of a cache issued by an operating system(OS) in the virtual computer is efficiently executed, and to provide the virtual computer system capable of efficiently control the cache at the time of switching of running (OS) in the processor. CONSTITUTION:When OS in the virtual computer issues the invalidation instruction of the cache in a processor 100-1, a control circuit 250-1 permits a cache memory 270-1 to be an invalid state and, then, requests cache invalidation to the cache 300-2. In the cache 300-2, a cache invalidating signal is transmitted to a control circuit 250-2 only when OS issuing the invalidation instruction coincides with OS running in the processor 100-2 and permits the cache memory 270-2 to be invalidated. Thus, the virtual computer system whereby IS efficiently utilizes the cache is provided.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a cache control device and control method, and more particularly to a cache control device and control method that enables a virtual computer to use the cache efficiently.

[0002]

2. Description of the Related Art Virtual computer system (VMS: Virtual
Machine System), as described in Japanese Patent Application Laid-Open No. 57-212680, generates a plurality of virtual machines (VM: Virtual Machines) which are logical machines on one machine, and each of these virtual machines is created. It is a system that enables each computer to run one operating system (OS).

In a virtual computer system, a plurality of OSs can be operated in parallel on one computer. For this reason, the virtual computer system uses a plurality of OSs for different purposes.
Operating on one computer, operating two OSs old and new on one computer at the time of OS transition from the old OS to the new OS,
It is mainly used as a tool for executing the S test in parallel on one computer.

In this virtual computer system, the virtual machine monitor (VMM) is
It allocates computer resources to each virtual computer, schedules and activates the virtual computer, and performs simulation processing of instructions issued by the OS that cannot be directly executed by the real computer. In this virtual computer system, each OS is provided with an environment as if it occupies an independent computer.

In a virtual computer system, a central processor (hereinafter referred to as a processor) that constitutes a real computer
The number may be one or plural.
A real computer having a plurality of processors is called a multiprocessor real computer. A virtual computer having a plurality of logical processors (hereinafter referred to as virtual processors) is called a virtual computer having a virtual multiprocessor configuration. In a virtual computer having a virtual multiprocessor configuration on a real computer having a multiprocessor configuration, the same OS can run on a plurality of processors at the same time.

Conventionally, virtual computer systems have been widely used in the field of general-purpose large-scale computers. However, due to the improvement in the performance of the microprocessor, there is a demand for a workstation to run a plurality of OSs depending on the application, and a virtual computer system on the workstation is becoming necessary.

In the field of this microprocessor, a reduced instruction set computer (RISC: Reduced) has recently been developed.
Instruction Set Computer) architecture is popular. For example, the Hewlett-Packard Journal August 1986 issue (HEWLETT-PACKARD JOURNAL, A
UGUST 1986), pages 16 and 17 include RI
The cache architecture in the SC processor is introduced. The cache is a memory buffer that holds part of the main memory and that can be accessed by the processor at high speed.

In this RISC processor, writing to the cache and main memory is performed as follows. First, if a copy of the block of main memory that the processor has requested to write is in the cache, this cache memory is updated. If the block is not in the cache, the block in the main memory is copied to the cache, and the copied block in the cache is updated.

Further, when there is no empty block in the cache at the time of write request, first, the block of the cache selected according to a predetermined algorithm is copied to the main memory, and the block of the cache is made empty. Then, the block of the main memory to which the writing is requested is copied to the block in the empty state, and the writing is performed to the block in this cache.

As described above, in the RISC processor, the cache and the main memory are not updated synchronously. That is, when the cache is updated, the main memory is not always updated at the same time. Therefore, the contents of the cache and the contents of the main memory do not always match.

Further, this RISC processor has a PURGE CA as an instruction for controlling the cache.
There are CHE and FLUSH CACHE instructions.
When a PURGECACHE instruction is issued in one processor of a computer system having a multiprocessor configuration, this request is broadcast to all the processors, and the cache contents of all the processors are invalidated. In addition, one of the computer systems of multiprocessor configuration
When a FLUSH CACHE instruction is issued in one processor, this request is broadcast to all the processors, and the cache contents are invalidated after the cache contents are copied to the main memory for all the processors.

[0012]

When attempting to construct a virtual computer system on the computer of the RISC processor described above, there are the following problems regarding cache control.

(1) The first problem is that when a real computer has a multiprocessor configuration (a plurality of real processors, each processor has a cache and a main memory is shared), the cache issued by the OS on the virtual machine is invalidated. Regarding execution of instructions.

The real computer has a multiprocessor configuration,
It is assumed that the first and second OSs are running on the first and second processors, respectively. At this time, if the cache invalidation instruction issued by the first OS is executed as it is, the cache of the second processor is also invalidated inappropriately. As a result, the contents of the memory of the second OS do not match, and the second OS cannot perform the correct processing. That is, there is a problem of how to execute a cache invalidation instruction issued by an OS on a virtual computer in a computer having a multiprocessor configuration.

(2) The second problem relates to switching of the running OS in the processor. This is a problem that exists in both the case where the real computer has one processor and the case where the real computer has a plurality of processors.

It is assumed that after the first OS runs, the second OS runs in the same processor, and the second OS issues a cache content invalidation instruction. At this time, if the invalidation instruction is executed as it is, the contents of the cache formed while the first OS was running last time are invalidated and lost. As a result, when the first OS is run next time, a mismatch occurs in the memory contents, and the first OS cannot perform correct processing. That is, when a plurality of virtual computers run on a computer having one processor, there is a problem of how to control the cache.

It is an object of the present invention to provide a virtual computer system capable of efficiently executing a cache invalidation instruction issued by an OS on a virtual computer in a multiprocessor computer.

Another object of the present invention is to provide a virtual computer system capable of efficiently controlling a cache when switching a running OS in a processor.

[0019]

In order to achieve the above object, the present invention provides a single unit having a plurality of processors, a main memory shared by the plurality of processors, and a cache provided for each processor. And a method of controlling a cache in a virtual computer system in which a plurality of operating systems run on a computer, the operating system running in a first processor among the plurality of processors, Whether or not the running operating system is running in each processor other than the first processor, the contents of the cache of the first processor are invalidated in response to issuance of an instruction to invalidate Content of the cache of the processor for which the determination is positive Characterized by being adapted to disable.

A cache control device and method in a virtual computer system in which a plurality of operating systems run on one computer having a processor, a main memory, and a cache. The first operating system that is to be run is the same as the second operating system last run on the processor, and in response to the positive result of the determination, the cache The first operating system is run on the processor without copying the contents to the main memory, or the contents of the cache are copied to the main memory in response to a negative result of the determination. The first operating system Characterized in that so as to travel in the processor.

Further, the present invention relates to a cache control device in a virtual computer system in which a plurality of operating systems run on one computer having a processor, a main memory and a cache having a plurality of entries, wherein: A storage unit for storing, for each entry, an identifier indicating which operating system each entry of the cache is using, and when registering a part of the main memory in the entry of the cache memory, Means for writing the identifier of the operating system running in the processor into the area of the corresponding entry of the storage means, and in response to the operating system running in the processor issuing an instruction to invalidate the contents of the cache. The operating Characterized in that the identifier of the computing system and means for invalidating an entry in the cache memory granted.

Further, according to the present invention, a plurality of programs are executed on one computer having a plurality of processors, a main memory shared by the plurality of processors, and a cache provided for each processor. A cache control device and method thereof in a computer system, wherein the first program among the plurality of processors executes a program in response to an instruction to invalidate the contents of the cache issued. To invalidate the cache contents of each processor, determine whether or not the program is being executed in each processor except the first processor, and invalidate the cache contents of the processor for which the determination is positive. It is characterized by having done.

A cache control apparatus and method in a computer system in which a plurality of programs are executed on a single computer having a processor, a main memory and a cache, and the processor executes the program next. Determines whether the first program is the same as the second program executed last by the processor, and if the result of the determination is positive, the content of the cache is stored in the main memory. The first program is executed in the processor without copying, or the contents of the cache are copied to the main memory in response to a negative result of the determination, and the first program is executed. It is characterized in that the program is executed in the processor.

Further, the present invention is a cache control device in a computer system in which a plurality of programs are executed on one computer having a processor, a main memory, and a cache having a plurality of entries. A storage unit for storing, for each entry, an identifier indicating which program is used for each entry, and a processor executing when a part of the main memory is registered in the entry of the cache memory. Means for writing the identifier of the program in the corresponding entry area of the storage means, and the program being executed in the processor issuing a command for invalidating the contents of the cache, A means for invalidating the cache memory entry to which an identifier is assigned Characterized by comprising a.

[0025]

The typical operation of the present invention will be described below.

An operating system (hereinafter referred to as OS) running on the first processor among the plurality of processors
But in response to issuing the cache invalidation instruction,
Invalidate the cache of the first processor. further,
In each of the processors except the first processor, it is determined whether or not the OS is running, and the contents of the cache of the processor for which the determination is positive are invalidated.

As described above, by executing the cache invalidation instruction issued by the OS on the virtual machine only on the processor on which the OS is running, another OS is executed.
It is possible to prevent it from affecting the running of. In this way, in a computer with a multiprocessor configuration,
There is provided a virtual computer system capable of efficiently executing a cache invalidation instruction issued by an OS on a virtual computer.

Further, the virtual machine monitor (VMM) determines whether or not the first OS of the plurality of processors to be run in the processor is the same as the second OS last run in the processor. If the determination result is affirmative, the virtual machine monitor (VMM) causes the first OS to run on the processor without copying the cache contents to the main memory. On the other hand, if the determination result is negative, the virtual machine monitor (VMM) copies the cache contents of the processor to the main memory, further invalidates all the cache contents, and then executes the first
Of OS is run on the processor.

In this way, when the first OS starts running, the cache does not hold the contents of the other OS's memory. Therefore, the first OS
Issuing a cache invalidation command during running does not affect the memory contents of other OSs. further,
When the first OS different from the second OS that was run last time is run, all caches are invalidated and all the memory contents of the first OS are saved in the main memory. Therefore, while the first OS is running, another OS in the cache
You will not accidentally use the memory contents of.

In this way, a virtual computer system capable of efficiently controlling the cache when switching the running OS in the processor is provided.

[0031]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Two embodiments of the present invention will be described in detail below with reference to the drawings.

(First embodiment)

1. Configuration of Computer System FIG. 1 is a configuration diagram of a computer system according to a first embodiment of the present invention. In FIG. 1, each processor 100-i
(I = 1, 2) shares the main memory 200. Further, each processor 100-i has a cache 30.
0-i are connected. In addition, the main memory 200
Includes a virtual machine monitor (VMM) 210 and an OS-
k (k = 1, 2, 3, 4) is loaded.

In this embodiment, the PURGE CACH issued by the OS on the virtual machine in the processor 100-i is used.
The E instruction and the FLUSH CACHE instruction are characterized in that the same OS as the running OS in the processor 100-i executes only in the cache 300-j of the running processor 100-j. The present embodiment is also characterized in that the cache 300 is initialized and the next OS is started when the OS is switched in the processor 100-i.

2. Execution of Cache Control Instruction Next, the execution operation of the cache control instruction issued by the OS on the virtual machine of this embodiment will be described with reference to FIG. FIG. 2 shows a detailed configuration of the cache 300-i (i = 1, 2) shown in FIG.

In FIG. 2, the request VM register 210-
i (i = 1, 2) is a register that holds the identifier of the OS that issued the PURGECACHE command or the FLUSH CACHE command. Running VM register 220-
i is a register that holds the identifier of the OS running in the processor 100-i.

The virtual machine monitor (VMM) 210 gives each OS a value of 1 or more as an identifier, and when the OS is started, the cache 30 is passed through the data line 400-i.
The identifier of this OS is sent to 0-i. The sent OS identifier is stored in the running VM register 220-i. Further, when the virtual machine monitor (VMM) 210 itself is executing, 0 is sent to the data line 400-i, and the running V
0 is stored in the M register 220-i.

Comparator 230-in cache 300-i
The operations of i, the selector 240-i, and the control circuit 250-i will be described in detail later.

Tag 260-i and cache memory 2
Each 70-i is composed of a plurality of entries.
Each entry of tag 260-i and cache memory 270
There is a one-to-one correspondence with each entry of -i.
Each entry of the tag 260-i is composed of a valid bit (V) and an address field. When the valid bit (V) is 1 (valid), the buffer in the main memory 200 indicated by the address stored in the address field of this entry is held in the entry of the cache memory 270 corresponding to the entry. Indicates that When the valid bit (V) is 0 (invalid), it indicates that the corresponding entry in the cache memory 270 is empty.

(A) Execution of PURGE CACHE instruction In the processor 100-1, the running OS-1 is PU
The operation when the RGE CACHE instruction is issued will be described.

First, the processor 100-1 uses the signal line 4
A purge request signal is sent to the control circuit 250-1 via 10-1. Control circuit 250 that received the purge request signal
-1 stores 0 (invalid) in the valid bit (V) of all entries of the tag 260-1, and the cache memory 270
All the entries of -1 are made empty. Thereafter, the control circuit 250-1 sends a purge request signal to the signal line 420-1.
In addition to sending to the data line 400-1, the OS-1 identifier 1 received via the data line 400-1 is sent to the data line 430-1.

As a result, 1 which is the identifier of OS-1 which issued the PURGE CACHE instruction in the processor 100-1 is sent to the data line 440-2 in the cache 300-2 and stored in the request VM register 210-2. To be done. Further, a signal line 450 is connected to the cache 300-2.
The purge request signal is sent via -2.

The comparator 230-2 is a PURGE CAC.
A request VM register 210-2 holding the identifier of the OS that issued the HE instruction and an O running on the processor 100-2.
The value of the running VM register 220-2 holding the identifier of S is compared, and the comparison result is output. Selector 240-2
Sends the purge request signal input from the signal line 450-2 to the control circuit 250-2 only when the comparison result by the comparator 230 indicates the same OS.

The control circuit 250 to which the purge request signal is sent
-2 stores 0 (invalid) in the valid bit (V) of all the entries of the tag 260-2 to make all the entries of the cache memory 270-2 empty.

(B) Execution of FLUSH CACHE instruction The OS-1 running on the processor-1 is FLUSH
The operation when the CACHE instruction is issued will be described.

First, as in the case of the above-mentioned PURGE CACHE instruction, the processor 100-1 has the signal line 41.
A flash request signal is sent to the control circuit 250-1 via 0-1. Upon receiving the flush request signal, the control circuit 250-1 places the cache memory 270-in the area on the main memory 200 indicated by the address field of the entry in which the valid bit (V) of the entry of the tag 260-1 indicates 1 (valid). The contents of the buffer held by 1 are stored via the data line 460-1. At the same time, 0 is set in the valid bit (V) of all the entries of the tag 260-1.
(Invalid) is stored and all the entries in the cache memory 270-1 are made empty. After that, the control circuit 250
-1 sends the flash request signal to the signal line 420-1 and receives the OS via the data line 400-1.
-1, which is the identifier of -1, is sent to the data line 430-1.

As a result, the identifier 1 of the OS-1 that issued the FLUSHCACHE instruction in the processor 100-1 is sent to the data line 440-2 in the cache 300-2 and stored in the request VM register 210-2. To be done. Further, a signal line 450 is connected to the cache 300-2.
The flash request signal is sent via -2.

The comparator 230-2 is a FLUSH CAC.
A request VM register 210-2 holding the identifier of the OS that issued the HE instruction and an O running on the processor 100-2.
The value of the running VM register 220-2 holding the identifier of S is compared, and the comparison result is output. Selector 240-2
Sends the flash request signal input from the signal line 450-2 to the control circuit 250-2 only when the comparison result by the comparator 230 indicates the same OS.

Control circuit 2 to which the flash request signal is sent
50-2 stores the contents of the buffer held by the cache memory 270-2 in the area on the main memory 200 indicated by the address field of the entry in which the valid bit (V) of the entry of the tag 260-2 indicates 1 (valid). , Through the data line 460-2. Also, the tag 260-
By storing 0 (invalid) in the valid bit (V) of all entries of No. 2, all entries of the cache memory 270-2 are made empty.

3. Switching Processing of Running OS FIG. 3 shows a virtual machine monitor (VMM) 210 of this embodiment.
5 is a flowchart of a traveling OS switching process by the.

When the running of the OS-k (step 3000) in the processor 100-i is interrupted (step 3010) due to the end of the time slice or the like (step 3010), the virtual machine monitor (VMM) 210 is generated due to the occurrence of a timer interrupt or the like.
Control over. The virtual machine monitor (VMM) 210 is
OS to run next based on the scheduling
-M is selected (step 3020). Then, it is determined whether the selected OS-m is the same as the OS-k last run on the processor 100-i (step 3030).

As a result of the judgment, if the OSs are the same, the selected OS-m is started (step 3050). Same O
Since S, the cache remains unchanged.

As a result of the determination, if the OS is different,
The FLUSH CACHE instruction is executed to execute the processor 1
After copying the contents of the cache 300-i of 00-i to the main memory 200, it is invalidated (step 304
0), start the selected OS-m (step 3050).

With the above arrangement, the processor 100-
At the start of booting OS-m in i, the cache 30
The contents of 0-i are either all invalid or the original O
It will have only S-m memory information. That is, the cache 300-i has no memory information other than OS-m. Therefore, the running OS-m is FLUSH

CACHE instruction or PURGE CA
Issuing the CHE command does not affect the contents of the memory of other OSs.

As described above, according to this embodiment,
In a computer having a multiprocessor configuration, it is possible to provide a virtual computer system that can efficiently execute a cache invalidation instruction issued by an OS on a virtual computer.

Further, according to this embodiment, it is possible to provide a virtual computer system capable of efficiently controlling the cache when switching the running OS in the processor.

It will be apparent that the present invention can be applied not only to the virtual computer system but also to a computer system in which a plurality of OSs can run on one computer. Also,
It will be apparent that the present invention can be applied to not only the virtual computer system but also a general computer system in which a plurality of programs are executed on one computer.

Further, in the present embodiment, the purging and flushing of the cache is executed for the entire cache, but even when it is executed for a part of the cache (for example, a specific page), It will be clear that the invention is applicable.

(Second Embodiment) Next, a second embodiment of the present invention will be described. The present embodiment also assumes the configuration of the computer system shown in FIG. However, in this embodiment,
A PUR issued by the OS on the virtual machine in the processor 100-i by sharing the cache 300-i between the OSs
It is characterized in that the GE CACHE instruction and the FLUSH CACHE instruction are executed only in the entry of the cache 300-i to which the identifier of the OS running in the processor 100-i is given.

The execution operation of the cache control instruction issued by the OS on the virtual machine will be described with reference to FIG. Figure 4
Is a cache 300-i (i = 1, 1 in this embodiment.
The detailed configuration of 2) is shown.

In FIG. 4, a virtual computer monitor (VM
M) 210 gives each OS a value of 1 or more as an identifier, and sends the identifier of this OS to the cache 300-i through the data line 400-i when the OS is activated.
Further, when the virtual machine monitor (VMM) 210 itself is executing, 0 is sent to the data line 400-i. The operation of the control circuit 250-i will be described in detail later.

Tag 260-i and cache memory 2
Each 70-i is composed of a plurality of entries.
Each entry of tag 260-i and cache memory 270
There is a one-to-one correspondence with each entry of -i.
Each entry of the tag 260-i is composed of a valid bit (V), an address field and a virtual machine identifier (VMID) field.

When the valid bit (V) is 1 (valid), the buffer in the main memory 200 pointed to by the address stored in the address field of this entry becomes the entry of the cache memory 270 corresponding to the entry. Indicates that it is held. In addition, the control circuit 2
50-i writes the identifier of the OS running on the processor 100-i when this entry is written (this is input to the control circuit 250-i from the data line 400-i) to that entry. Store in the VMID field. Further, when the valid bit (V) is 0 (invalid), it indicates that the corresponding entry in the cache memory 270 is empty.

(A) Execution of PURGE CACHE instruction In the processor 100-1, the running OS-1 is PU
The operation when the RGE CACHE instruction is issued will be described.

First, the processor 100-1 uses the signal line 4
A purge request signal is sent to the control circuit 250-1 via 10-1. Control circuit 250 that received the purge request signal
-1 stores 0 (invalid) in the valid bit (V) of the entry in which the value of the VMID field of the tag 260-1 is 1 sent from the data line 400-1. This allows
The entry of the cache memory 270-1 used by the OS-1 is made empty. After that, the control circuit 25
0-1 sends a purge request signal to the signal line 420-1 and receives OS- received via the data line 400-1.
The identifier 1 of 1 is sent to the data line 430-1.

As a result, the identifier 1 of the OS-1 that issued the PURGE CACHE instruction in the processor 100-1 is sent to the data line 440-2 in the cache 300-2. In addition, in the cache 300-2,
A purge request signal is sent via the signal line 450-2.

The control circuit 250 to which the purge request signal is sent
-2 stores 0 (invalid) in the valid bit (V) of the entry whose VMID field value of the tag 260-2 is 1 sent from the data line 440-2. This allows
The entry of the cache memory 270-2 used by the OS-1 becomes empty.

(B) Execution of FLUSH CACHE instruction When OS-1 running on processor-1 is FLUSH
The operation when the CACHE instruction is issued will be described.

First, as in the case of the above-mentioned PURGE CACHE instruction, the processor 100-1 uses the signal line 41
A flash request signal is sent to the control circuit 250-1 via 0-1. The control circuit 250-1 which has received the flush request signal has the valid bit (V) of the entry of the tag 260-1 being 1 (valid) and the value of the VMID field being 1 sent from the data line 400-1. The contents of the buffer held by the cache memory 270-1 are stored in the area on the main memory 200 indicated by the address field of the entry via the data line 460-1. At the same time, 0 (invalid) is stored in the valid bit (V) of this entry, and the entry of the cache memory 270-1 used by OS-1 is made empty. After that, the control circuit 250-1 sends the flash request signal to the signal line 42.
0-1 which is the identifier of OS-1 received via the data line 400-1 while being sent to the data line 430-.
Send to 1.

As a result, 1 which is the identifier of OS-1 which issued the FLUSHCACHE instruction in the processor 100-1 is sent to the data line 440-2 in the cache 300-2. In addition, in the cache 300-2,
A flash request signal is sent via the signal line 450-2.

Control circuit 2 to which the flash request signal is sent
50-2 is a main pointed to by the address field of the entry whose valid bit (V) of the tag 260-2 is 1 (valid) and whose VMID field value is 1 sent from the data line 440-2. The contents of the buffer held by the cache memory 270-2 are stored in the area on the memory 200 via the data line 460-2.
Further, by storing 0 (invalid) in the valid bit (V) of this entry, the entry of the cache memory 270-2 used by OS-1 is made empty.

As described above, according to this embodiment, it is possible to provide a virtual computer system in which a cache can be efficiently shared among a plurality of OSs.

[0074]

According to the present invention, there is provided a virtual computer system capable of efficiently executing a cache invalidation instruction issued by an OS on a virtual computer in a computer having a multiprocessor configuration. Further, there is provided a virtual computer system capable of efficiently controlling the cache when switching the running OS in each processor.

[Brief description of drawings]

FIG. 1 is a configuration diagram of a computer system according to an embodiment.

FIG. 2 is an execution circuit diagram of a cache control instruction according to the first embodiment.

FIG. 3 is a flowchart of a traveling OS switching process according to the first embodiment.

FIG. 4 is an execution circuit diagram of a cache control instruction in the second embodiment.

[Explanation of symbols]

100-i: processor, 200: main memory, 21
0: virtual machine monitor, 300-i: cache.

 ─────────────────────────────────────────────────── ─── Continuation of the front page (72) Inventor Yoshihide Kami 5030 Totsuka-cho, Totsuka-ku, Yokohama-shi, Kanagawa Prefecture Hitachi Ltd. Software Development Division

Claims (10)

[Claims] 1. A virtual computer system in which a plurality of operating systems run on one computer having a plurality of processors, a main memory shared by the plurality of processors, and a cache provided for each processor. In the first processor of the plurality of processors, the first controller responsive to an instruction for invalidating the contents of the cache issued by an operating system running in the first processor.
Means for invalidating the cache contents of the processor, a means for determining whether or not the running operating system is running in each processor except the first processor, and the determination is positive. And a means for invalidating the contents of the cache of the processor. 2. A cache control device in a virtual computer system in which a plurality of operating systems run on one computer having a processor, a main memory and a cache, wherein the processor attempts to run next. First to do
Means for determining whether the operating system of the second operating system is the same as the second operating system last run on the processor, and the content of the cache is stored in the main memory in response to a positive result of the determination. Means for running the first operating system on the processor without copying to memory, and copying the contents of the cache to the main memory in response to a negative result of the determination, And a means for running a first operating system on the processor. 3. A cache controller in a virtual computer system in which a plurality of operating systems run on one computer having a processor, a main memory, and a cache having a plurality of entries, each entry of the cache A storage unit for storing, for each entry, an identifier indicating which operating system is used, and when a part of the main memory is registered in the entry of the cache memory, the processor is running. Means for writing the identifier of the operating system in the area of the corresponding entry of the storage means, and the operating system running in the processor issuing a command to invalidate the contents of the cache. Operating system in Controller cache, wherein a beam identifier and means for invalidating an entry in the cache memory granted. 4. A virtual computer system in which a plurality of operating systems run on a single computer having a plurality of processors, a main memory shared by the plurality of processors, and a cache provided for each processor. In the first processor of the plurality of processors, wherein the operating system running in the first processor issues a command for invalidating the contents of the cache.
Invalidating the contents of the cache of the processor, the step of determining whether or not the running operating system is running in each processor except the first processor, and the determination is positive. And a step of invalidating the contents of the cache of the processor. 5. A cache control method in a virtual computer system in which a plurality of operating systems run on one computer having a processor, a main memory, and a cache, wherein the processor attempts to run next. First to do
The operating system of the processor determines whether it is the same as the second operating system last run on the processor, and if the result of the determination is positive, the contents of the cache are stored in the main memory. Running the first operating system on the processor without copying to memory; copying the contents of the cache to the main memory in response to a negative determination result; A step of running a first operating system on the processor. 6. A cache in a computer system in which a plurality of programs are executed on a single computer having a plurality of processors, a main memory shared by the plurality of processors, and a cache provided for each processor. Of the cache of the first processor in response to the program being executed in the first processor of the plurality of processors issuing an instruction to invalidate the contents of the cache. Means for invalidating, means for determining whether or not the program is being executed in each processor except the first processor, and means for invalidating the cache contents of the processor for which the determination is positive. A cache control device characterized by being provided. 7. A cache control device in a computer system in which a plurality of programs are executed on one computer having a processor, a main memory, and a cache, wherein the processor intends to execute the program next. 1
The second program last executed by the processor
Determining whether or not the program is the same as the above program, and executing the first program in the processor without copying the contents of the cache to the main memory in response to the affirmative result. And a means for causing the processor to execute the first program by copying the contents of the cache to the main memory in response to a negative result of the determination. Control unit for cache. 8. A cache control device in a computer system in which a plurality of programs are executed on one computer having a processor, a main memory, and a cache having a plurality of entries, wherein each entry of the cache is Storage means for storing, for each entry, an identifier indicating whether it is used in the program, and an identifier of the program being executed by the processor when a part of the main memory is registered in the entry of the cache memory In a region of the corresponding entry of the storage means, and in response to the program running in the processor issuing an instruction to invalidate the contents of the cache,
And a means for invalidating an entry in the cache memory to which the identifier of the program being executed is added. 9. A cache in a computer system in which a plurality of programs are executed on a single computer having a plurality of processors, a main memory shared by the plurality of processors, and a cache provided for each processor. The method of controlling the cache content of the first processor in response to a program being executed in the first processor of the plurality of processors issuing an instruction to invalidate the content of the cache. A step of invalidating, a step of determining whether or not the program is being executed in each processor except the first processor, and a step of invalidating the cache contents of the processor for which the determination is positive. A method for controlling a cache, which comprises: 10. A cache control method in a computer system in which a plurality of programs are executed on a single computer having a processor, a main memory, and a cache, wherein the processor attempts to execute the program next. 1
The second program last executed by the processor
Determining whether or not the program is the same as the above program, and executing the first program in the processor without copying the contents of the cache to the main memory in response to the affirmative result. And a step of causing the processor to execute the first program by copying the contents of the cache to the main memory in response to a negative result of the determination. How to control cache.