JP2008293472A - Computer device and its cache recovery method - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To prevent a cache error in environment where a plurality of virtual computers are operated. <P>SOLUTION: This computer device 1 has a high-speed cache 2; a storage section 3 for storing data 3a transferred to the high-speed cache 2; a history information storage section 5 for storing history information 4 with an address 4b related to an identifier 4a uniquely identifying the virtual computer; a determining section 6 for determining the presence of the identifier 4a included in the history information 4 coinciding with the identifier of the virtual computer after switching, referring to the history information storage section 5; and a transfer instructing section 7 for specifying data 3a stored in the storage section 3 based on the address 4b related to the coincident identifier 4a and transferring the specified data 3a to the high-speed cache 2. <P>COPYRIGHT: (C)2009,JPO&INPIT

Description

  The present invention relates to a computer apparatus and its cache recovery method, and more particularly to a computer apparatus and its cache recovery method in an environment in which a plurality of virtual machines are operated by switching.

  Conventionally, computer virtualization has been mostly used in a host computer (host computer) which is the center of a network. Recently, however, familiar IA (Intel architecture) processors such as Intel (registered trademark) processors and AMD (registered trademark) processors have begun to adopt hardware virtualization technology, and at the PC (Personal Computer) level, Virtual machine (VM) environments are becoming rare. As a result, it is expected that the use of virtual machines will increase from the use in large enterprises to the use at the individual level.

  Conventionally, high-speed and small-capacity buffers (caches) have been used in computers for speed buffering between a CPU (Central Processing Unit) and a main memory. The CPU has obtained a large performance improvement by temporarily placing frequently used data in a cache by utilizing the characteristics of locality of reference and temporal locality regarding data use.

  However, the cache of the processor so far can be highly effective in an environment where one virtual machine operates, but in an environment where multiple virtual machines operate by switching, virtual machine mutual cache contamination occurs, The effect cannot be fully exhibited.

  Here, cache pollution refers to cache data read (= fetched) during the operation of a virtual machine in an environment where a plurality of virtual machines are switched and operated while another virtual machine is operating. Even if the cache data is temporarily invalidated at the time of virtual machine switching and the original virtual machine is switched again, cache misses occur frequently immediately after switching.

Due to this cache contamination, there is a problem that the cache cannot be used effectively and the original role of the cache cannot be achieved.
On the other hand, a method for suppressing adverse effects on other virtual machines by using a means for identifying a virtual machine is known (for example, see Patent Document 1).

Also, a method is known in which a plurality of caches are prepared and banked, and each bank is individually assigned to a virtual machine to maintain the original effect of the cache (see, for example, Patent Document 2).
JP-A-7-105091 JP 61-034643 A

However, the conventional techniques have the following problems.
For example, in Patent Document 1, there is a problem that there is no effect of preventing performance degradation other than a cache invalidation instruction.

  Also, in Patent Document 2, since the cache is very expensive, if the capacity of the entire cache is increased in order to prepare a plurality of banks, the cost increases, which is not practical. On the other hand, if the entire capacity is left as it is, the cache capacity allocated to each virtual machine will be reduced, and there will be an increase in capacity cache misses. . Furthermore, since the number of banks prepared in advance is fixed, there is a problem that the number of virtual machines that can be handled is limited.

  The present invention has been made in view of these points, and an object of the present invention is to provide a computer apparatus capable of preventing a cache miss in an environment in which a plurality of virtual machines are operating, and a cache recovery method thereof. To do.

In the present invention, a computer apparatus 1 as shown in FIG. 1 is provided to solve the above problem.
The computer apparatus 1 according to the present invention is an apparatus that switches and operates a plurality of virtual machines.
The computer apparatus 1 includes a high-speed cache 2, a storage unit 3 that stores data 3a to be transferred to the high-speed cache 2, and history information that stores history information 4 in which an address 4b is associated with an identifier 4a that uniquely identifies the virtual computer. When there is a switch between the storage unit 5 and the operating virtual machine, the determination unit 6 refers to the history information storage unit 5 and determines whether or not there is an identifier 4a included in the history information 4 that matches the identifier of the virtual machine after the switch. And a transfer instructing unit 7 for specifying the data 3a stored in the storage unit 3 based on the address 4b associated with the matched identifier 4a and transferring the specified data 3a to the high-speed cache 2.

  According to such a computer apparatus 1, when there is a switching of operating virtual machines, the history information storage unit 5 is referred to by the determination unit 6 and is included in the history information 4 that matches the identifier of the virtual computer after the switching. The presence or absence of the identifier 4a is determined. Then, the transfer instruction unit 7 outputs a transfer request for the data 3a based on the address 4b associated with the matched identifier, and specifies the data 3a stored in the storage unit 3 and the high speed of the specified data 3a. Transfer to the cache 2 is executed.

  According to the present invention, since the data required by the virtual machine after switching can be transferred to the high-speed cache in advance by referring to the history information storage unit, the cache has an original effect, that is, locality of reference, particularly Temporal locality can be exhibited.

Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings.
First, an outline of the present invention will be described, and then an embodiment will be described.
FIG. 1 is a diagram showing an outline of the present invention. In the following description, it is assumed that an environment in which a plurality of virtual machines are operating on one computer apparatus 1 is assumed. In this case, it is assumed that each virtual machine is operating while switching one by one.

The computer apparatus 1 includes a high-speed cache 2, a storage unit 3, a history information storage unit 5, a determination unit 6, and a transfer instruction unit 7.
The high speed cache 2 is, for example, a cache memory inside the CPU.

The storage unit 3 stores data 3 a to be transferred to the high speed cache 2. This data 3a is, for example, data previously stored in the high-speed cache 2.
The history information storage unit 5 stores history information 4 in which an address 4b is associated with an identifier 4a that uniquely identifies a virtual machine. The address 4b is an address of data required by the virtual machine specified by the identifier 4a during operation. For example, an address of memory data fetched (captured) into the cache is taken out and associated with the identifier 4a as the address 4b. Yes. One or a plurality of the history information 4 is stored.

  When the operating virtual machine is switched, the determination unit 6 refers to the history information storage unit 5 to determine whether or not there is an identifier 4a included in the history information 4 that matches the identifier of the virtual computer after the switching.

  The transfer instruction unit 7 specifies the data 3a stored in the storage unit 3 based on the address 4b associated with the matched identifier 4a, and transfers the specified data 3a to the high-speed cache 2. For example, when the transfer instructing unit 7 outputs a data transfer request corresponding to the address 4b to a cache controller (not shown) of the high-speed cache 2, the cache controller receives data corresponding to the address on the memory that matches the address 4b. 3a is specified, and the data 3a is taken into the high speed cache 2 from the storage unit 3.

  According to such a computer apparatus 1, when there is a switching of operating virtual machines, the history information storage unit 5 is referred to by the determination unit 6 and is included in the history information 4 that matches the identifier of the virtual computer after the switching. The presence or absence of the identifier 4a is determined. Then, the transfer instruction unit 7 outputs a transfer request for the data 3a based on the address 4b associated with the matched identifier 4a, and specifies the data 3a stored in the storage unit 3 and the specified data 3a. Transfer to the high speed cache 2 is executed.

Embodiments of the present invention will be described below.
FIG. 2 is a diagram illustrating a hardware configuration example of the computer apparatus.
The entire computer apparatus 10 is controlled by the CPU 101. A random access memory (RAM) 102, a hard disk drive (HDD) 103, a graphics processing device 104, an input interface 105, a communication interface 106, and a recovery controller 15 are connected to the CPU 101 via a bus 107. .

  The RAM 102 temporarily stores at least part of an OS (Operating System) program and application programs to be executed by the CPU 101. The RAM 102 stores various data necessary for processing by the CPU 101. The HDD 103 stores an OS and application programs. A program file is stored in the HDD 103.

  A monitor 31 is connected to the graphic processing device 104. The graphic processing device 104 displays an image on the screen of the monitor 31 in accordance with a command from the CPU 101. A keyboard 32 and a mouse 33 are connected to the input interface 105. The input interface 105 transmits a signal sent from the keyboard 32 and the mouse 33 to the CPU 101 via the bus 107.

  The communication interface 106 is connected to the network 30. The communication interface 106 can send and receive data to and from other computers via the network 30.

The recovery controller 15 will be described later.
With the hardware configuration as described above, the processing functions of the present embodiment can be realized. In order to perform cache recovery in the computer apparatus 10 having such a hardware configuration, the following functions are provided in the computer apparatus 10.

FIG. 3 is a block diagram illustrating functions of the computer apparatus.
The computer apparatus 10 includes a cache 11, a memory 12, a cache history table 13, a VM-ID register 14, a recovery controller 15, and an AND circuit 16.

  The cache 11 is provided, for example, inside the CPU 101 for buffering the speed between the arithmetic unit of the CPU 101 and the memory 12, and temporarily stores data frequently used by the CPU 101. Data input / output of the cache 11 is performed by a cache controller (not shown).

  The memory 12 is composed of, for example, a RAM 102 (main storage unit) that is slower than the cache 11 and a lower cache layer. The main memory stores data to be fetched (captured) into the cache 11.

  FIG. 4 is a diagram illustrating data stored in the cache. The cache 11 stores data (Data) to be fetched from the memory 12 into the cache 11. Each fetched data (Data) also has a valid bit (address bit) and an address (address) for determining the necessity of the data, and a set of each of these elements is set as cache data or a cache entry. Call.

Returning to FIG. 3, the description will be continued.
The cache history table 13 includes, for example, a part of the RAM 102, the high-speed memory in the CPU 101, and a register, and has a plurality of history entries 21, 21,.

  One history entry 21 is an area (entry) that stores a valid bit that determines whether data is necessary, a VM-ID that serves as an ID tag for identifying a virtual machine, and a data address (address). ). Hereinafter, the valid bit, VM-ID, and data address (data address stored in the cache) are collectively referred to as “history data”.

The VM-ID register 14 is configured by a part of the register in the CPU 101, for example, and stores the VM-ID of the currently operating virtual machine.
The recovery controller 15 performs a recovery operation (described later) for recovering cache data to the cache 11 when a VM switching signal generated by the CPU 101 is triggered by switching of virtual machines. In other cases, a recording operation (described later) is performed in which valid entries, VM-IDs, and cache data addresses are associated with the history entries 21, 21,.

The AND circuit 16 is provided to determine whether the VM-ID register 14 matches the VM-ID of the history data stored in the history entry 21.
Next, a recording method (fetch address recording method) of history data stored in the history entries 21, 21,.

FIG. 5 is a diagram for explaining a recording method of history data. In FIG. 5, the same step numbers are assigned to the operations performed at the same time.
The recovery controller 15 observes fetching of cache data from the memory 12 to the cache 11 (step S1).

  When the cache data is fetched, the recovery controller 15 sends the address of the fetched data (the location of the main storage where the data is stored = address) and the VM-ID of the virtual machine that is operating at that time. Are simultaneously read (step S2).

Then, the read address and VM-ID are recorded as history data in the history entry 21, and the valid bit is set to 1 (valid) (step S3).
The recovery controller 15 repeats steps S1 to S3. Thereby, the history data is stored in the history entries 21, 21,.

Next, the recovery operation of the computer apparatus 10 (recovery controller 15) will be described.
FIG. 6 is a diagram for explaining the recovery operation.
As preprocessing, the CPU 101 stores a new VM-ID in the VM-ID register 14 and generates a VM switching signal. At this time, the operation by the new virtual machine has not started.

The recovery controller 15 starts the recovery operation using the VM switching signal as a trigger (step S11).
The recovery controller 15 sequentially checks each history entry 21, 21,... On the cache history table 13 (step S12).

  More specifically, the AND circuit 16 inputs the valid bit and ID tag (= VM-ID) in the history entries 21, 21,... A comparison is made with the VM-ID of the virtual machine that is about to operate, which is input from the ID register 14, and the result is output to the recovery controller 15. The AND circuit 16 outputs “1” if these VM-IDs match and the valid bit is “1”, and outputs “0” otherwise (step S13).

  When “1” is output from the AND circuit 16, the recovery controller 15 determines that the addresses match, and checks the address stored in the history entry 21 that is checked (stores the matching VM-ID). Reference is made (step S14).

Then, the recovery controller 15 issues a fetch request to the cache controller using the referenced address as a fetch address (step S15).
The data at the referenced address is fetched from the memory 12 (step S16) and stored in the cache 11 again, thereby completing the restoration of the cache data.

This completes the recovery operation.
Next, an example in which a history entry is expanded is shown as a modification.
<Modification>
FIG. 7 is a diagram illustrating an example in which the history entry is expanded.

  The history entry 21a is configured to be able to cope with a case where the structure of the cache 11 is an instruction cache or a data cache, or a multi-level cache configuration such as a secondary cache or a tertiary cache.

  The history entry 21a is provided to correspond to the area 211 storing the type flag indicating whether the recorded address is the instruction address (I) or the data address (D), and the multi-level cache. It further has an area (Level Index) 212 for storing a hierarchy flag indicating the hierarchy. In FIG. 7, the area 211 stores the instruction address (I).

  The recovery controller 15 refers to the history entry 21a type flag during the recovery operation, and fetches it to the instruction cache when the history is the instruction address (I), and fetches it to the data cache when the history is the data address (D). Make a request to

  For example, if the history entry 21a referred to during the recovery operation is a secondary cache history, the recovery controller 15 refers to the hierarchy flag and issues a request to the cache controller to fetch the secondary cache.

  As described above, according to the computer apparatus 10 of this embodiment, when the virtual computer is switched, the recovery controller 15 refers to the cache history table 13 for the cache data effective for the virtual computer to be operated from now on. Judgment is made so that the corresponding cache data is read from the memory before the cache data is needed (so as to overlap with the switching operation of the virtual machine that proceeds in an operation different from the recovery operation) and fetched to the cache 11. I made it. As a result, cache data corresponding to a specific virtual machine (used by the virtual machine last time) can be restored when the virtual machine operates.

  As a result, cache misses after switching virtual machines can be prevented, and the cache can exhibit its original effects (locality of reference and especially temporal locality), so multiple virtual machines in operation It is expected to improve the performance (including the entire virtual machine environment).

  Further, not only invalidation instructions but also cache contamination from other virtual machines due to cache data rewriting in general can be prevented. In addition, there is an advantage that not only a specific virtual machine but also all virtual machines operating simultaneously on the computer apparatus 10 can receive the benefit.

In addition, since the structure of the cache 11 need not be changed, an existing cache can be used.
Further, since the recovery controller 15 has a hardware configuration, the processing speed is high, and processing can be performed in parallel with switching of virtual machines. Also, no software support is required.

  In addition, since the cache data is managed using a simple VM-ID (using a tagging method), the number of operating virtual machines is not particularly limited, and the number of operating virtual machines increases dynamically. Can also respond.

  In the present embodiment, the AND circuit 16 is provided outside the recovery controller 15. However, the present invention is not limited to this, and the AND circuit 16 may be provided in the recovery controller 15, for example.

Next, a computer apparatus according to the second embodiment will be described.
FIG. 8 is a diagram illustrating a computer apparatus according to the second embodiment.
Hereinafter, the computer apparatus 10a according to the second embodiment will be described with a focus on differences from the first embodiment described above, and description of similar matters will be omitted.

The computer apparatus 10a according to the second embodiment is the same as the first embodiment except for the configuration of the cache history table 13a.
The cache history table 13a of the computer device 10a manages history data by associating a recording location in the table with a virtual computer. Specifically, the history data is managed in units of banks in which the table is divided into areas for each virtual computer in order from the upper side in FIG. One bank 21b has an ID (VM # 0, VM # 1,...) That is equal to (or corresponds to) the VM-ID of the virtual machine. Each bank 21b stores a valid bit and an address, respectively. Is done.

Next, the recovery operation of the computer apparatus 10a according to the second embodiment will be described.
The recovery controller 15 starts the recovery operation using the VM switching input signal as a trigger (step S21).

The recovery controller 15 checks the VM-ID stored in the VM-ID register 14 (step S22).
The recovery controller 15 searches for the bank 21b on the cache history table 13a having the VM-ID that matches the checked VM-ID (step S23).

  As a result of the search, it is determined whether or not the corresponding entry is valid by referring to the valid bit of each entry in the corresponding bank 21b (in FIG. 8, the bank 21b of VM # 1) (step S24). The address stored in the determined entry is referred to (step S25).

Then, a fetch request is issued to the cache controller using the referenced address as a fetch address (step S26).
The data at the referenced address is fetched from the memory 12 (step S27) and stored again in the cache 11, thereby completing the restoration of the cache data.

This completes the recovery operation of the second embodiment.
According to the computer apparatus 10a of the second embodiment, the same effect as that of the computer apparatus 10 of the first embodiment can be obtained.

  According to the computer apparatus 10a of the second embodiment, the area for storing the valid bits and addresses for each virtual machine is fixedly determined on the cache history table 13a. Since only the fixed area needs to be referred to and it is not necessary to search all over the cache history table 13a, it is possible to reduce unnecessary scanning of the cache history table 13a during the recovery operation, and thus, faster recovery processing. It can be performed. Thereby, even if there is an overhead of recovery processing, useless scanning can be reduced.

Next, a computer apparatus according to the third embodiment will be described.
Hereinafter, the computer apparatus according to the third embodiment will be described with a focus on differences from the first embodiment described above, and description of similar matters will be omitted.

  The computer apparatus of the third embodiment is different from the computer apparatus 10 of the first embodiment in the form of cache data and the method of recording the cache data in the cache history table 13.

FIG. 9 is a diagram illustrating an internal structure of the cache of the computer apparatus according to the third embodiment.
The cache 11 is provided with a cache entry 11a as a data storage area.

  The cache entry 11a has a VM-ID storage area in addition to a valid bit, address, and data storage area. This VM-ID can be added by, for example, a cache controller.

Next, a history data recording method (ejected address recording method) of the computer apparatus of the third embodiment will be described.
FIG. 10 is a diagram for explaining a history data recording method according to the third embodiment. Note that the computer apparatus 10b shown in FIG. 10 omits the same portions as those of the computer apparatus 10, and the same step numbers are assigned to the operations performed at the same time.

The recovery controller 15 observes data ejection (Eject) and data invalidation (Invalidate) from the cache 11 (step S1a).
When data eviction or data invalidation occurs, the address recorded in the cache entry 11a that has been evicted (Ejected) or invalidated (invalidated) from the cache 11 and in the same cache entry 11a. The recorded VM-ID is read (step S2a).

  Then, the read address and VM-ID are recorded as history data in the history entry 21 of the cache history table 13, and the valid bit of the history entry is made valid (1) (step S3a).

Also by such a method, history data is stored in the history entries 21, 21,.
According to the computer apparatus 10b of the third embodiment, the same effect as that of the computer apparatus 10 of the first embodiment can be obtained.

  And according to the computer apparatus 10b of the third embodiment, only cache data that needs to be recovered is recorded in the cache history table 13, so there is no need to restore useless data, and more efficient recovery, That is, since the cache can be used more effectively, the performance of the entire virtual machine environment can be further improved.

  In the following fourth to ninth embodiments, for example, a concept such as temporal locality is introduced to make the role of valid bits concrete, and cache data having a higher priority is restored. Reduce the amount of restoration.

Hereinafter, the computer apparatus according to the fourth embodiment will be described focusing on the differences from the first embodiment described above, and description of similar matters will be omitted.
The computer apparatus of the fourth embodiment is different from the computer apparatus 10 of the first embodiment in the form of history data stored in the history entry and its control method.

FIG. 11 is a diagram illustrating history data according to the fourth embodiment.
The history data stored in the history entry 21 of this embodiment is composed of a VM-ID, an A bit (access bit), and a data address (address). In FIG. 11, the cache history table 13 and the like are not shown.

  The A bit embodies a valid bit (recovery control bit) and serves as an index indicating the frequency with which history data stored in the history entry 21 is used. Specifically, history data whose A bit is ON (1) is data having a relatively high use frequency, and history data whose A bit is OFF (0) is data having a relatively low use frequency. It is. Hereinafter, a method of turning on the A bit, a method of turning off the A bit, and a control method of the computer apparatus using the history data will be described in order.

FIG. 12 is a diagram illustrating a method of turning on the A bit.
The computer apparatus according to the present embodiment includes an access monitoring unit 41 and AND circuits 42 to 44.

The access monitoring unit 41 monitors access from the CPU 101 to the cache 11. If there is an access, the address is output to the AND circuit 43.
The AND circuit 42 is provided separately from the AND circuit 16, and the VM-ID of the currently operating virtual machine stored in the VM-ID register 14 and the VM-ID of the history data stored in the history entry 21. A match with the ID is determined.

The AND circuit 42 outputs “1” when these VM-IDs match, and outputs “0” otherwise.
The AND circuit 43 is provided to determine whether the address monitored by the access monitoring unit 41 matches the address in the history entry 21.

The AND circuit 43 outputs “1” when these addresses match, and outputs “0” otherwise.
The AND circuit 44 turns on the A bit only when both the output of the AND circuit 42 and the output of the AND circuit 43 are “1”.

FIG. 13 is a diagram illustrating a method of turning off the A bit.
The computer apparatus according to the present embodiment includes a program execution unit 101a, a timer 101b, AND circuits 45 and 47, an OR circuit 46, and an A bit clear execution unit 48.

Each of the program execution unit 101a and the timer 101b is a function of the CPU 101, and periodically outputs an A-bit clear signal.
The timing for outputting the clear signal is not particularly limited, but is preferably set according to, for example, the allocation time of the virtual machine. For example, when the allocation time of the virtual machine is 5 ms to 15 ms, every 100 μm Or every 1 ms. Further, the timer 101b does not output a new clear signal, but may use an existing signal as it is if a signal of the above timing exists.

  The AND circuit 45 has the same function as the AND circuit 42 described above. The AND circuit 42 may also serve as the AND circuit 45. In that case, the output of the AND circuit 42 is also output to the AND circuit 47.

The OR circuit 46 outputs “1” when a clear signal is output from either the program execution unit 101a or the timer 101b.
The AND circuit 47 outputs “1” when both the output of the AND circuit 45 and the output of the OR circuit 46 are “1”.

The A bit clear execution unit 48 turns off the A bit when the output of the AND circuit 47 is “1”.
Thus, apart from the recovery operation, the A bit is turned ON or OFF according to the usage frequency of the history data.

FIG. 14 is a diagram for explaining the recovery operation of the computer apparatus according to the fourth embodiment.
Differences from the recovery operation of the computer apparatus 10 according to the first embodiment shown in FIG. 6 will be described, and description of similar points will be omitted.

  The recovery controller 15 of the computer apparatus 10c according to the fourth embodiment sequentially checks the history entries 21, 21,... On the cache history table 13 (step S12).

  Specifically, the AND circuit 16 receives the A bit and ID tag (= VM-ID) in the history entries 21, 21,... Sequentially input according to the instruction of the recovery controller 15, and the VM when the VM switching signal is input. A comparison is made with the VM-ID of the virtual machine which is going to operate from the ID register 14 and the result is output to the recovery controller 15 (step S13a).

  As a result, the recovery controller 15 refers to and refers only to the history data in which “1” is output from the AND circuit 16, that is, the address of the history data in which the VM-ID matches and the A bit is ON. A fetch request is issued to the cache controller using the address as a fetch address (step S15).

According to the computer apparatus 10c of the fourth embodiment, the same effect as the computer apparatus 10 of the first embodiment can be obtained.
According to the computer apparatus 10c of the fourth embodiment, a mechanism for turning ON or OFF the A bit is provided, and recovery and prefetching are performed only for history data in which the A bit is ON. The selection criteria can be made highly accurate. As a result, useless cache recovery can be prevented, and the use of cache as a resource can be made more efficient. In addition, quick cache recovery can be performed.

Next, a computer apparatus according to a fifth embodiment will be described.
Hereinafter, the computer apparatus according to the fifth embodiment will be described with a focus on differences from the fourth embodiment described above, and description of similar matters will be omitted.

The computer apparatus according to the fifth embodiment is different from the computer apparatus 10c according to the fourth embodiment in the form of history data stored in the history entry and the recovery operation.
FIG. 15 is a diagram illustrating history data according to the fifth embodiment.

  The history data stored in the history entry 21 of this embodiment is composed of a VM-ID, a reference bit, a change bit, and a data address (address). In FIG. 15, the cache history table 13 and the like are not shown.

  The reference bit and the change bit are subdivided functions of the A bit, and, like the A bit, serve as an index indicating the frequency with which the history data stored in the history entry 21 is used. Specifically, if there is a reference (read) request from the CPU 101 to the cache 11, the reference bit of the history data of the corresponding history entry 21 is turned on, and if there is an update (write) request from the CPU 101 to the cache 11, Turn on the update bit of the history data of the corresponding history entry. Also, as in the fourth embodiment, unused reference bits and update bits are periodically turned off.

Furthermore, the computer apparatus of the fifth embodiment has a function for controlling the history data.
FIG. 16 illustrates a computer apparatus according to the fifth embodiment.

The computer apparatus 10 d includes a priority target setting unit 51, an effective rank setting unit 52, and an effective rank control unit 53.
The priority target setting unit 51 is set to prioritize the reference request or the update request.

The effective rank setting unit 52 is set with a rank indicating the priority of history data to be recovered during the recovery operation.
FIG. 17 is a diagram showing ranks.

  The rank is stored in a table, for example, and the rank table 52a indicates a rank that prioritizes reference bits. The rank is determined by the combination of the reference bit and the update bit, rank 1 has the highest priority, and rank 4 has the lowest priority.

Returning to FIG.
The effective rank control unit 53 determines whether the reference bit and the change bit included in the history data satisfy the setting criterion based on the setting criterion set by the priority target setting unit 51 and the effective rank setting unit 52. . For example, when priority is set to the priority target setting unit 51 and rank 2 is set to the effective rank setting unit 52, the rank table 52a shown in FIG. It is determined that only history data whose update bits are both “1”, or history data whose reference bits are “1” and update bits are “0” satisfies the setting criteria. The effective rank control unit 53 outputs “1” when the setting criterion is satisfied, and outputs “0” when the setting criterion is not satisfied.

Next, the recovery operation of the computer apparatus 10d will be described. Differences from the recovery operation of the fourth embodiment will be described, and description of similar points will be omitted.
The recovery controller 15 sequentially checks each history entry 21, 21,... On the cache history table 13 (step S12).

  Specifically, the AND circuit 16 receives the ID tag (= VM-ID) in the history entries 21, 21,... That are sequentially input according to the instruction of the recovery controller 15, and the VM-ID register when the VM switching signal is input. 14 is compared with the VM-ID of the virtual machine to be operated. Further, the output of the effective rank control unit 53 is checked. Then, the result is output to the recovery controller 15 (step S13b).

  As a result, the recovery controller 15 refers only to the history data in which “1” is output from the AND circuit 16, that is, the history data that matches the VM-ID and satisfies the setting criteria, and refers to the referenced address. A fetch request is issued to the cache controller as a fetch address (step S15).

According to the computer apparatus 10d of the fifth embodiment, the same effect as the computer apparatus 10c of the fourth embodiment can be obtained.
According to the computer apparatus 10d of the fifth embodiment, the history data to be recovered can be narrowed down by providing finer stepwise judgment criteria such as reference bits and update bits. The use of cache resources can be made more efficient.

<Modification>
Although not shown, instead of a valid bit, the counter value of a monotonically increasing counter such as a “time stamp counter” or “CPU cycle counter” provided in the CPU or system is used as history data without using a bit. It may be recorded together with a more specific use time. In this case, the periodic bit clear operation can be omitted. In this case, an effective number or a specific time can also be used as a criterion for selecting history data to be recovered during the recovery operation.

Next, a computer apparatus according to the sixth embodiment will be described.
Hereinafter, the computer apparatus according to the sixth embodiment will be described focusing on the differences from the above-described fourth embodiment, and description of similar matters will be omitted.

The computer apparatus of the sixth embodiment is different from the computer apparatus 10c of the fourth embodiment in the form of history data stored in the history entry and the recovery operation.
FIG. 18 illustrates a computer apparatus according to the sixth embodiment.

  The history data stored in the history entry 21 of the computer apparatus 10e of this embodiment is composed of a VM-ID, a counter, and a data address (address). The counter represents the usage frequency of the history data and is composed of at least two bits.

  The method of incrementing the counter is the same as the method of turning on the A bit shown in FIG. However, in this embodiment, every time “1” is output from the AND circuit 44, the counter is incremented.

The computer apparatus 10 e includes an effective threshold value setting unit 61 and a counter comparison unit 62.
In the effective threshold value setting unit 61, a threshold value of a counter to be compared by the counter comparison unit 62 (for example, 10 times or more) is set.

  The counter comparison unit 62 compares the counter threshold set by the effective threshold setting unit 61 with the counter value of the history data counter stored in the history entry 21. Then, it is determined whether or not the condition of the counter threshold is satisfied. If it is satisfied, “1” is output, and if it is not satisfied, “0” is output.

Next, the recovery operation of the computer apparatus 10e will be described. Differences from the recovery operation of the fourth embodiment will be described, and description of similar points will be omitted.
The recovery controller 15 sequentially checks each history entry 21, 21,... On the cache history table 13 (step S12).

  Specifically, the AND circuit 16 receives the ID tag (= VM-ID) in the history entries 21, 21,... That are sequentially input according to the instruction of the recovery controller 15, and the VM-ID register when the VM switching signal is input. 14 is compared with the VM-ID of the virtual machine to be operated. Also, the output of the counter comparison unit 62 is checked. Then, the result is output to the recovery controller 15 (step S13c).

  As a result, the recovery controller 15 refers to only the history data for which “1” is output from the AND circuit 16, that is, the address of the history data that matches the VM-ID and satisfies the threshold condition of the counter. A fetch request is issued to the cache controller using the address thus obtained as a fetch address (step S15).

According to the computer apparatus 10e of the sixth embodiment, the same effect as the computer apparatus 10c of the fourth embodiment can be obtained.
According to the computer device 10e of the sixth embodiment, since the counter is used, it is possible to narrow down the history data to be recovered more finely, and further to improve the efficiency of recovery and cache resource use.

<Modification 1>
In the present embodiment, the counter is incremented for each access regardless of the access type of the cache. However, the present invention is not limited to this, for example, once according to the access type (reference, update). The counter increment may be weighted so that the reference is prioritized over the update or only the reference is valid.

<Modification 2>
In this embodiment, a monotonically increasing counter is used. However, the present invention is not limited to this, and for example, an aging counter (aging counter) can be used.

FIG. 19 is a diagram showing the transition of the aging counter.
The aging counter of all data stored in each history entry 21 is updated according to the following rule at the time of clock interrupt or memory access instruction.

(1) The aging counter of the same history data as the data accessed by the cache shifts to the right and then increments the leftmost bit.
(2) The aging counter of history data that has not been accessed is only shifted to the right.

  As a result, the history data having a higher access frequency recently has a larger counter value. Then, the counter comparison unit 62 outputs “1” when the counter value is equal to or larger than the value set in the effective threshold setting unit 61.

By providing such an aging counter, a periodic clear operation can be omitted.
Next, a computer apparatus according to a seventh embodiment will be described.

Hereinafter, the computer apparatus according to the seventh embodiment will be described with a focus on differences from the second embodiment described above, and description of similar matters will be omitted.
The computer apparatus of the seventh embodiment is different from the computer apparatus 10a of the second embodiment in the history data storage method and retrieval method.

FIG. 20 is a diagram illustrating (a part of) the computer apparatus according to the seventh embodiment.
The computer apparatus according to the seventh embodiment further includes a FIFO control unit 71 that performs first in first out (FIFO) control for each bank 21b. .

Hereinafter, the operation of the computer apparatus of the seventh embodiment will be described by taking as an example the case where the VM-ID of the VM-ID register 14 is VM # 1.
First, if the corresponding history data does not exist in the bank 21b of the VM # 1 at the time of cache access, the FIFO control unit 71 enqueues the cache history as history data on the entrance en1 side (upper side in FIG. 20) of the bank 21b. To do.

On the other hand, when the corresponding history data exists in the cache history table 13a at the time of cache access, the history data is extracted and enqueued again.
When the bank 21b becomes full, the FIFO control unit 71 discards the history data closest to the queue exit ex1 side (the lower side in FIG. 20).

Further, the FIFO control unit 71 designates a predetermined number of history data to be recovered during the recovery operation from the entrance en1 side of the bank 21b.
At the time of recovery, the recovery controller 15 performs recovery using the history data for the number specified by the FIFO control unit 71. That is, the computer apparatus (recovery controller 15) of the present embodiment performs LIFO (Last In First Out) control.

According to the computer apparatus of the seventh embodiment, the same effect as that of the computer apparatus 10a of the second embodiment can be obtained.
According to the computer apparatus of the seventh embodiment, since the FIFO control is performed for the record management of the history entry and the LIFO control is performed during the recovery operation, the access between the CPU 101 and the cache 11 is monitored. In addition, since it is not necessary to turn on / off bits, recovery and cache resource use can be made more efficient without greatly expanding the configuration of the computer apparatus. Further, by changing the number of history data to be recovered, processing according to the performance of the computer device can be executed.

  In the present embodiment, the FIFO control unit 71 specifies the number of history data to be recovered, but the recovery controller 15 may specify the number of history data to be recovered.

Next, a computer apparatus according to an eighth embodiment will be described.
Hereinafter, the computer apparatus according to the eighth embodiment will be described focusing on the differences from the above-described fourth embodiment, and description of similar matters will be omitted.

The computer apparatus of the eighth embodiment is different from the computer apparatus 10c of the fourth embodiment in the management method of history data.
FIG. 21 is a diagram illustrating a computer apparatus according to the eighth embodiment.

The computer apparatus according to the eighth embodiment further includes a write back monitoring unit 81, an invalidation signal monitoring unit 82, an OR circuit 83, and a history data deleting unit 84.
The write-back monitoring unit 81 writes back data from the cache 11 to the memory 12 (even if data is written from the CPU 101 to the memory 12, only the data on the cache 11 is updated, and unless the condition is satisfied, the memory 12 When the write back is detected, the address of the cache data is output to the OR circuit 83.

The invalidation signal monitoring unit 82 monitors an invalidation instruction to the cache 11 and outputs an address of cache data of the invalidation instruction to the OR circuit 83 when detecting the invalidation instruction.
When an address is output from either the write-back monitoring unit 81 or the invalidation signal monitoring unit 82, the OR circuit 83 outputs the address.

The AND circuit 43 a is provided to determine whether the address output from the OR circuit 83 matches the address in the history entry 21.
The AND circuit 43a outputs “1” when these addresses match, and outputs “0” otherwise.

When “1” is output from the AND circuit 44, the history data deleting unit 84 deletes history data having the corresponding VM-ID from the cache history table 13.
According to the computer apparatus of the eighth embodiment, the same effect as the computer apparatus 10c of the fourth embodiment can be obtained.

  According to the computer apparatus of the eighth embodiment, the cache data invalidation information and the like in the currently operating virtual machine can be reflected in the history data of the cache history table 13. Thereby, compared with the fourth to seventh embodiments, it is possible to further improve the efficiency of cache recovery.

Next, a computer apparatus according to a ninth embodiment will be described.
Hereinafter, the computer apparatus according to the ninth embodiment will be described focusing on differences from the above-described fourth embodiment, and description of similar matters will be omitted.

  The computer apparatus of the ninth embodiment is different from the computer apparatus 10c of the fourth embodiment in the management method of history data. Specifically, the computer apparatus according to the ninth embodiment uses a set associative method as a method for allocating memory data to a cache, and further uses a LRU (Least Recently Used) as a data replacement method within the set. The method is used.

FIG. 22 is a diagram illustrating (a part of) the computer apparatus according to the ninth embodiment.
The computer apparatus 10f according to the ninth embodiment includes a cache 11b instead of the cache 11, and history data stored in the cache history table 13 is set according to LRU information (described later) of the cache 11b. Has a bit.

  Further, the computer apparatus 10 f has an LRU information reflecting unit 15 a for setting the U bit separately from the recovery controller 15. In FIG. 22, the recovery controller 15 and the like are not shown.

FIG. 23 is a diagram illustrating a cache according to the ninth embodiment.
The cache 11 b includes a cache address / data storage unit 111 and an LRU information storage unit 112.

  The cache address / data storage unit 111 has SET # n (n = 1, 2,..., K) indicating a storage area including a plurality of cache lines (Way # 0 to Way # 3 in FIG. 23). is doing.

  The LRU information storage unit 112 stores LRU information including numerical values indicating the priority order of the cache lines Way # 0 to Way # 3 in the SET # n. “1” is the newest (most recently used), and “4” is the oldest (the most time has elapsed since it was used).

Information arranged in the horizontal direction of the information in the cache address / data storage unit 111 and the information in the LRU information storage unit 112 are associated with each other.
Here, when the cache data in SET # n is rewritten, the oldest data is discarded and replaced with newly cached data. That is, in FIG. 23, the cache data of the cache line Way # 2 in SET # n is the next replacement target (replacement target) in SET # n.

Next, a method for controlling the U bit of the computer apparatus according to the ninth embodiment will be described.
FIG. 24 is a diagram illustrating a U bit control method of the computer apparatus according to the ninth embodiment.
This process is performed before the recovery operation.

  First, the LRU information reflecting unit 15a starts the operation with a switch signal to another VM among VM switching as a trigger (step S31). Specifically, in order to find out its own history data from the cache history table 13, all the records that match the VM-ID of the current virtual machine (not the new virtual machine) stored in the VM-ID register 14. The VM-ID of the history entry 21 is checked (steps S32 and S33), and the address of the matching history entry 21 is referred to (step S34).

Then, the cache 11b having the address is searched from the cache 11b (step S35).
Next, the LRU information reflecting unit 15a extracts the LRU information from the LRU information storage unit 112 corresponding to the found cache address / data storage unit 111 (step S36).

  Then, the LRU information reflecting unit 15a reflects the extracted LRU information in the U bit of the history entry 21 of the address referred in step S34 (step S37). For example, if the LRU information is “4”, the U bit is OFF (0), and if the LRU information is “1” to “3”, the U bit is set to ON (1). Alternatively, the U bit of the history entry that matches at the end of step S33 may be set to ON (1) and set to OFF (0) only when the extracted LRU information is “4”. .

  As a result, during the recovery operation, the recovery controller 15 controls to restore only the data in which the U bit is set to ON among the history data stored in the cache history table 13. Since this control method is the same as the method using the A bit in the fourth embodiment described above, the description thereof is omitted.

According to the computer apparatus 10f of the ninth embodiment, the same effect as that of the computer apparatus 10c of the fourth embodiment can be obtained.
According to the computer apparatus 10f of the ninth embodiment, by adding a minimum function to the cache, cache recovery efficiency can be improved without setting a bank in the cache history table 13. The structure of the computer device can be simplified.

<Modification>
As a variation of the U bit, a concept such as the rank described in the computer apparatus 10d of the fifth embodiment can be introduced.

  For example, in the case of the cache 11b (4 way set associative), means for holding numerical values of 1 to 4 indicating four levels of priority is provided in the history data, and the priority order used in the recovery operation is determined. At that time, a means for specifying the effective recovery number and priority is also provided. For example, if the priority is specified up to 2, control is performed so that history data having priorities 3 and 4 is not targeted for recovery.

  As mentioned above, although the computer apparatus of this invention and its cache recovery method were demonstrated based on embodiment of illustration, this invention is not limited to this, The structure of each part is arbitrary which has the same function. It can be replaced with that of the configuration. Moreover, other arbitrary structures and processes may be added to the present invention.

Further, the present invention may be a combination of any two or more configurations (features) of the above-described embodiments.
Regarding the above first to ninth embodiments, the following additional notes are further disclosed.

(Supplementary note 1) In a computer device that operates by switching a plurality of virtual machines,
With fast cache,
A storage unit for storing data to be transferred to the high-speed cache;
A history information storage unit for storing history information in which a predetermined address is associated with an identifier for uniquely identifying a virtual machine;
When there is a switching of the operating virtual machine, a determination unit that determines the presence or absence of the identifier included in the history information that matches the identifier of the virtual computer after switching with reference to the history information storage unit;
A transfer instruction unit for specifying the data stored in the storage unit based on the predetermined address associated with the matched identifier, and transferring the specified data to the high-speed cache;
A computer apparatus comprising:

(Supplementary Note 2) An identifier acquisition unit that acquires the identifier of the virtual machine being executed;
A history information generation unit that generates the history information by associating the address of the data with the identifier acquired by the identifier acquisition unit;
Further comprising
The history information storage unit has a history information storage area defined for each identifier,
The computer apparatus according to appendix 1, wherein the determination unit refers to the history information storage area specified by the identifier of the virtual machine after switching.

(Supplementary Note 3) The history information storage unit includes a plurality of history information storage areas in which a plurality of the history information is associated with one identifier.
The computer apparatus according to appendix 1 or 2, wherein the determination unit refers to the history information storage area specified by the identifier of the virtual computer after switching.

(Appendix 4) The identifier is included in the data,
A monitoring unit that monitors the eviction or invalidation of the data from the high-speed cache;
When the data is evicted or invalidated, the history information generating unit that generates the history information by associating the evicted or invalidated data with the identifier included in the data;
The computer apparatus according to appendix 1 or 2, further comprising:

(Additional remark 5) The addition part which adds the access frequency information which shows the frequency of access to the said log | history information,
An access frequency increasing unit that observes access to the high-speed cache and increases the access frequency of the access frequency information of the history information corresponding to the accessed data;
The determination unit according to claim 1 or 2, wherein the determination unit determines the presence or absence of the identifier included in the history information in which the access frequency indicated by the access frequency information satisfies a predetermined condition at the time of the determination. Computer equipment.

  (Supplementary Note 6) The access frequency increasing unit includes the identifier that matches the identifier of the virtual machine that is currently operating, and includes the address that matches the address of the accessed data. The computer apparatus according to appendix 5, wherein the access frequency of the access frequency information is increased.

  (Supplementary Note 7) The access frequency information is composed of 1 bit, and the access frequency increasing unit validates the bit of the access frequency information of the history information corresponding to accessed data, and the determination unit The computer apparatus according to claim 5, wherein the presence or absence of the identifier included in the history information in which the bit is valid is determined.

(Supplementary note 8) The computer apparatus according to supplementary note 5, wherein the adding unit adds the access frequency information when the history information is stored.
(Supplementary note 9) The computer apparatus according to supplementary note 5, further comprising a history deletion execution unit that deletes an access history of the access frequency information that has not been accessed for a predetermined time.

(Additional remark 10) The said log | history deletion execution part deletes the said access log | history regularly, The computer apparatus of Additional remark 9 characterized by the above-mentioned.
(Supplementary Note 11) The access frequency information includes a counter, the access frequency increase unit increments the counter of the history information corresponding to accessed data, and the determination unit has a predetermined value or more. The computer apparatus according to appendix 5 or 9, wherein the presence / absence of the identifier included in the history information having the counter value is determined.

(Supplementary Note 12) The history information storage unit includes a plurality of history information storage areas in which a plurality of the history information is associated with one identifier.
A FIFO control unit for storing the history information in the history information storage area by a FIFO method;
The FIFO control unit observes access to the high-speed cache, determines whether the history information corresponding to the accessed data is stored in the history information storage area, and stores the history information The history information corresponding to the accessed data is taken out and re-queued in the history information storage area,
The computer apparatus according to appendix 1 or 2, wherein the determination unit refers to the history information storage area specified by the identifier of the virtual computer after switching.

(Additional remark 13) The said FIFO control part discards the said historical information output from the exit side of the said historical information storage area, The computer apparatus of Additional remark 12 characterized by the above-mentioned.
(Additional remark 14) The computer apparatus of Additional remark 12 characterized by the predetermined number of the said history information made into the judgment object of the said judgment part being designated from the entrance side of the said history information storage area.

(Supplementary Note 15) A monitoring unit that monitors information for invalidating data in the high-speed cache;
The computer apparatus according to appendix 1 or 2, further comprising: a history information deleting unit that deletes the history information corresponding to the data to be invalidated obtained from the monitoring unit from the history information storage unit.

  (Supplementary Note 16) The history information deletion unit includes the identifier that matches the identifier of the virtual machine that is currently operating, and the history information that includes an address that matches the address of the accessed data. The computer apparatus according to appendix 15, wherein the computer apparatus is deleted from the history information storage unit.

(Supplementary Note 17) An assigning unit that assigns the data to the high-speed cache using a set associative method as a method of assigning the data stored in the storage unit to the high-speed cache;
An adding unit for adding access frequency information indicating the frequency of access to the history information;
When the virtual machine is switched, the access frequency of the access frequency information of the history information corresponding to the LRU information indicating whether or not the data stored in the high-speed cache is to be discarded is increased. An access frequency increasing unit
The determination unit according to claim 1 or 2, wherein the determination unit determines the presence or absence of the identifier included in the history information in which the access frequency indicated by the access frequency information satisfies a predetermined condition at the time of the determination. Computer equipment.

  (Supplementary Note 18) The access frequency increasing unit includes the identifier that matches the identifier of the virtual machine that is currently operating, and includes the address that matches the address of the accessed data. 18. The computer device according to appendix 17, wherein the access frequency of the access frequency information is increased.

  (Supplementary Note 19) The supplementary note 17 is characterized in that the access frequency increasing unit increases the access frequency of the access frequency information of the history information other than the LRU information indicating that the data is to be discarded next. The computer apparatus described.

(Supplementary note 20) The access frequency information is composed of 1 bit,
The access frequency increasing unit validates the bits of the access frequency information other than the LRU information indicating that the data is to be discarded next,
18. The computer apparatus according to appendix 17, wherein the determination unit determines the presence or absence of the identifier included in the history information in which the bit is valid.

(Supplementary note 21) The computer apparatus according to supplementary note 17, wherein the addition unit adds the access frequency information when the history information is stored.
(Supplementary Note 22) The access frequency information includes a counter, the access frequency increasing unit increments the counter of the history information corresponding to accessed data, and the determination unit is greater than or equal to a predetermined value. 18. The computer device according to appendix 17, wherein the presence or absence of the identifier included in the history information having a counter value of is determined.

(Supplementary Note 23) In a cache recovery method for a computer device that operates by switching a plurality of virtual machines,
When there is a switching of operating virtual machines, the determination unit refers to a history information storage unit that stores history information in which a predetermined address is associated with an identifier that uniquely identifies the virtual machine, and the virtual machine after switching Determining the presence or absence of the identifier included in the history information matching the identifier;
A transfer instruction unit, based on the predetermined address associated with the matched identifier, causes the data stored at the address on the storage unit to be transferred to the high-speed cache;
And a cache recovery method for a computer apparatus.

It is a figure which shows the outline | summary of this invention. It is a figure which shows the hardware structural example of a computer apparatus. It is a block diagram which shows the function of a computer apparatus. It is a figure which shows the data stored in the cache. It is a figure explaining the recording method of history data. It is a figure explaining recovery operation. It is a figure which shows the example which expanded the log | history entry. It is a figure which shows the computer apparatus of 2nd Embodiment. It is a figure which shows the internal structure of the cache of the computer apparatus of 3rd Embodiment. It is a figure explaining the recording method of the historical data of 3rd Embodiment. It is a figure which shows the historical data of 4th Embodiment. It is a figure which shows the method of turning ON A bit. It is a figure which shows the method of turning off A bit. It is a figure explaining the recovery operation | movement of the computer apparatus of 4th Embodiment. It is a figure which shows the historical data of 5th Embodiment. It is a figure which shows the computer apparatus of 5th Embodiment. It is a figure which shows a rank. It is a figure which shows the computer apparatus of 6th Embodiment. It is a figure which shows transition of an aging counter. It is a figure which shows the computer apparatus of 7th Embodiment. It is a figure which shows the computer apparatus of 8th Embodiment. It is a figure which shows the computer apparatus of 9th Embodiment. It is a figure which shows the cache of 9th Embodiment. It is a figure which shows the control method of the U bit of the computer apparatus of 9th Embodiment.

Explanation of symbols

1, 10, 10a, 10b, 10c, 10d, 10e, 10f Computer device 2 High-speed cache 3 Storage unit 3a Data 4 History information 4a Identifier 4b Address 5 History information storage unit 6 Judgment unit 7 Transfer instruction unit 11, 11b Cache 11a Cache Entry 12 Memory 13, 13a Cache history table 14 VM-ID register 15 Recovery controller 15a LRU information reflection unit 16, 42, 43, 43a, 44, 45, 47 AND circuit 21, 21a History entry 21b bank
41 access monitoring unit 46, 83 OR circuit 48 bit clear execution unit 51 priority target setting unit 52 effective rank setting unit 52a rank table 53 effective rank control unit 61 effective threshold setting unit 62 counter comparison unit 71 FIFO control unit 81 write back monitoring unit 82 Invalidation signal monitoring unit 84 History data deletion unit 101a Program execution unit 101b Timer 111 Cache address / data storage unit 112 LRU information storage unit 211 Area

Claims (10)

In a computer device that operates by switching a plurality of virtual machines,
With fast cache,
A storage unit for storing data to be transferred to the high-speed cache;
A history information storage unit for storing history information in which a predetermined address is associated with an identifier for uniquely identifying a virtual machine;
When there is a switching of the operating virtual machine, a determination unit that determines the presence or absence of the identifier included in the history information that matches the identifier of the virtual computer after switching with reference to the history information storage unit;
A transfer instruction unit for specifying the data stored in the storage unit based on the predetermined address associated with the matched identifier, and transferring the specified data to the high-speed cache;
A computer apparatus comprising: An identifier acquisition unit for acquiring the identifier of the virtual machine being executed;
A history information generation unit that generates the history information by associating the address of the data with the identifier acquired by the identifier acquisition unit;
Further comprising
The history information storage unit has a history information storage area defined for each identifier,
The computer apparatus according to claim 1, wherein the determination unit refers to the history information storage area specified by the identifier of the virtual computer after switching. The data includes the identifier;
A monitoring unit that monitors the eviction or invalidation of the data from the high-speed cache;
When the data is evicted or invalidated, the history information generating unit that generates the history information by associating the evicted or invalidated data with the identifier included in the data;
The computer apparatus according to claim 1, further comprising: An adding unit for adding access frequency information indicating the frequency of access to the history information;
An access frequency increasing unit that observes access to the high-speed cache and increases the access frequency of the access frequency information of the history information corresponding to the accessed data;
3. The determination unit according to claim 1, wherein the determination unit determines whether or not the identifier is included in the history information satisfying a predetermined condition for an access frequency indicated by the access frequency information in the determination. The computer apparatus described.   5. The computer apparatus according to claim 4, further comprising a history erasure execution unit that erases an access history of the access frequency information that has not been accessed for a predetermined time.   The access frequency information includes a counter, the access frequency increase unit increments the counter of the history information corresponding to accessed data, and the determination unit sets a counter value equal to or greater than a predetermined value. 6. The computer apparatus according to claim 4, wherein the presence / absence of the identifier included in the history information is determined. The history information storage unit has a plurality of history information storage areas in which a plurality of the history information is associated with one identifier.
A FIFO control unit for storing the history information in the history information storage area by a FIFO method;
The FIFO control unit observes access to the high-speed cache, determines whether the history information corresponding to the accessed data is stored in the history information storage area, and stores the history information The history information corresponding to the accessed data is taken out and re-queued in the history information storage area,
The computer device according to claim 1, wherein the determination unit refers to the history information storage area specified by the identifier of the virtual computer after switching. A monitoring unit that monitors information for invalidating data in the high-speed cache;
The computer apparatus according to claim 1, further comprising: a history information deleting unit that deletes the history information corresponding to the data to be invalidated obtained from the monitoring unit from the history information storage unit. . An assigning unit for assigning the data to the high-speed cache using a set associative method as a method for assigning the data stored in the storage unit to the high-speed cache;
An adding unit for adding access frequency information indicating the frequency of access to the history information;
When the virtual machine is switched, the access frequency of the access frequency information of the history information corresponding to the LRU information indicating whether or not the data stored in the high-speed cache is to be discarded is increased. An access frequency increasing unit
3. The determination unit according to claim 1, wherein the determination unit determines whether or not the identifier is included in the history information satisfying a predetermined condition for an access frequency indicated by the access frequency information in the determination. The computer apparatus described. In a cache recovery method for a computer device that operates by switching a plurality of virtual machines,
When there is a switching of operating virtual machines, the determination unit refers to a history information storage unit that stores history information in which a predetermined address is associated with an identifier that uniquely identifies the virtual machine, and the virtual machine after switching Determining the presence or absence of the identifier included in the history information matching the identifier;
A transfer instruction unit, based on the predetermined address associated with the matched identifier, causes the data stored at the address on the storage unit to be transferred to the high-speed cache;
And a cache recovery method for a computer apparatus.

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