CN108351800A - Pre-install the page table cache circuit of virtual machine - Google Patents
Pre-install the page table cache circuit of virtual machine Download PDFInfo
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- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F12/00—Accessing, addressing or allocating within memory systems or architectures
- G06F12/02—Addressing or allocation; Relocation
- G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
- G06F12/12—Replacement control
- G06F12/121—Replacement control using replacement algorithms
- G06F12/123—Replacement control using replacement algorithms with age lists, e.g. queue, most recently used [MRU] list or least recently used [LRU] list
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F12/00—Accessing, addressing or allocating within memory systems or architectures
- G06F12/02—Addressing or allocation; Relocation
- G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
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- G06F12/00—Accessing, addressing or allocating within memory systems or architectures
- G06F12/02—Addressing or allocation; Relocation
- G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
- G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
- G06F12/0862—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches with prefetch
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- G06F12/00—Accessing, addressing or allocating within memory systems or architectures
- G06F12/02—Addressing or allocation; Relocation
- G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
- G06F12/10—Address translation
- G06F12/1009—Address translation using page tables, e.g. page table structures
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- G06F12/02—Addressing or allocation; Relocation
- G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
- G06F12/10—Address translation
- G06F12/1027—Address translation using associative or pseudo-associative address translation means, e.g. translation look-aside buffer [TLB]
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- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/44—Arrangements for executing specific programs
- G06F9/455—Emulation; Interpretation; Software simulation, e.g. virtualisation or emulation of application or operating system execution engines
- G06F9/45533—Hypervisors; Virtual machine monitors
- G06F9/45558—Hypervisor-specific management and integration aspects
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- G—PHYSICS
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- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/44—Arrangements for executing specific programs
- G06F9/455—Emulation; Interpretation; Software simulation, e.g. virtualisation or emulation of application or operating system execution engines
- G06F9/45533—Hypervisors; Virtual machine monitors
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- G06F2212/00—Indexing scheme relating to accessing, addressing or allocation within memory systems or architectures
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Abstract
Here embodiment preloads the memory translation for performing the virtual to physical memory translation in computing systems for switching between virtual machine (VMs).Before processor is switched to the new virtual machine from execution current virtual machine, management program can retrieve the memory for the new virtual machine being previously saved and translate and load them into cache or main memory.Therefore, when new virtual machine starts to execute, corresponding memory translation is in the buffer rather than in memory.Therefore, when the translation of these memories of needs is come when performing the virtual to physical address translation, processor need not be waited for extract the memory translation for slow storage device (for example, hard disk drive).
Description
Background technology
The present invention relates to preheat computing system when switching between virtual machine (VM).More specifically, this disclosure relates to holding
The memory translation preserved is preloaded before the new VM of row.
Typically, processor includes at least one memory management unit for performing the virtual to physical address translation
(MMU).For example, virtual memory block can be distributed to the different processes executed on a processor (for example, operating system by processor
Or user application).Each virtual address corresponds to the physical memory addresses in memory.Between virtual address and physical address
Mapping be stored in page table as page table entries.Page table is generally stored inside in main memory.
When process reads data to process cores transmission request from particular virtual address or writes data into specific virtual
When address, MMU inquires page table (or translation look-aside buffer) to identify corresponding physical address.Then process kernel uses physics
Address executes reading or write-in by process requested.
Invention content
One embodiment of the present of invention is a kind of method, and this method is included in first time period and executes correspondence using processor
In the first operating system (OS) of the first VM.The method includes before the first time period expires, by by the page
Table clause is moved to higher level from the relatively low rank of memory hierarchical structure, preloads the page table of the 2nd OS corresponding to the 2nd VM
Entry, wherein the more relatively low rank of the higher level is closer to the processor in memory hierarchical structure.In the first time period
After expiring, the 2nd OS for corresponding to the 2nd VM is executed using processor in second time period.
Another embodiment of the present invention is a kind of computing system comprising is configured as corresponding in first time period execution
The processor and management program of the first OS of first VM.Management program is configured as before the first time period expires,
By the way that the page table entries are moved to higher level from the relatively low rank of memory hierarchical structure, preload corresponding to the 2nd VM's
The page table entries of 2nd OS, wherein the more relatively low rank of the higher level is closer to the processor in memory hierarchical structure.Institute
It states after first time period expires, management program, which also indicates the processor and starts to execute in second time period, corresponds to described the
The 2nd OS of two VM.
Another embodiment of the present invention is a kind of computer program product for being switched between VM, the calculating
Machine program product includes computer code, executable to indicate that processor executes the corresponding to the first VM in first time period
One OS, and before the first time period expires, pass through the relatively low rank by the page table entries from memory hierarchical structure
It is moved to higher level, the page table entries of the 2nd OS corresponding to the 2nd VM are preloaded, wherein the higher level is compared with lower level
Not closer to the processor in memory hierarchical structure.After the first time period expires, the computer code is executable
To indicate twoth OS of the processor in second time period using processor execution corresponding to the 2nd VM.
Description of the drawings
Fig. 1 is the computing system for preloading memory translation when switching virtual machine according to one embodiment described herein
Block diagram.
Fig. 2 is the flow for preloading memory translation in switching virtual machine according to one embodiment described herein
Figure.
Fig. 3 is the computing system translated according to the stored memory when switching out virtual machine of one embodiment described herein
Block diagram.
Fig. 4 is the block diagram according to the computing system of one embodiment described herein switched between different virtual machine.
Fig. 5 is the calculating system that memory translation is preloaded before switching virtual machine according to one embodiment described herein
The block diagram of system.
Fig. 6 is the block diagram according to the computing system of one embodiment described herein switched between different virtual machine.
In order to make it easy to understand, indicating to share in figure using identical reference numeral in the conceived case identical
Element.It is contemplated that disclosed element may be advantageously used with other embodiment without specific in one embodiment
Narration.
Specific implementation mode
Embodiment herein preloads in the computing system for switching between virtual machine (VM) and performs the virtual to object
Manage memory translation (or vice versa) memory translation.For example, processor (or CPU) in computing system can be when different
Between execute different VM.In other words, the processing time of processor can distribute or divide between multiple VM.In one embodiment
In, processor executes the instruction for the first VM during first time period, is then switched to execution during the second period
For the instruction of the 2nd VM.
In some cases, VM is uncorrelated.More specifically, it is translated by the memory that the process executed in the first VM uses
It can be different from the memory translation that the process executed in the 2nd VM uses.For example, the first and second VM can execute it is assigned
The different processes of different virtual memory address.In this case, the void of the process for being executed in the first VM is executed
Intend to needed for physical address translation page table entries with for executing needed for the address translation of the process executed in the 2nd VM
Page table entries are different.When processor switches between VM, executes the page table entries cached when previous VM and corresponded in the buffer
The page table entries of new VM are replaced.But do so the storage device (such as hard disk) that access speed may be needed slower, this meeting
Reduce the execution speed of new VM.
Embodiment herein preloads the memory for new VM to be performed and translates.In other words, processor from
Current VM is switched to before new VM, and management program can retrieve the memory for new VM being previously saved and translate and load them
Into cache or main memory.Therefore, when new VM starts to execute, corresponding memory translation is in the buffer rather than is depositing
Chu Zhong.It is translated when needing these memories come when performing the virtual to physical address translation, computing system need not be tens of from that can save
Slow storage device (for example, hard disk drive) the retrieval memory translation in ten thousand processor periods.
In one embodiment, computing system includes the translation look-aside buffer for performing the virtual to physical memory translation
(TLB).TLB is the cache used by MMU, to store the subset of page table entries.If address is not in TLB (that is, TLB
Miss), then computing system executes page traversal to search address in another cache or main memory.Because here
The memory being previously saved translation is pre-loaded in cache by embodiment, so when there are TLB miss, desired address
It can be saved in the caches.As described above, this saves the times needed for the search address information from storage.In other words
Say, when switching between VM, the translation of the memory that has stored in TLB may not be to new VM it is very useful, therefore, here
Embodiment will be pre-loaded to cache or main memory corresponding to the translation of the memory of new VM.After TLB miss, it is not necessary to from depositing
Page table entries are retrieved in reservoir, but can find this data in the caches.It in this way, will due to TLB miss
Memory translation, which is pre-loaded in cache " preheating ", may take less time for the TLB of new VM to parse.
Fig. 1 is the computing system 100 that memory translation is preloaded when switching VM according to one embodiment described herein
Block diagram.Specifically, leftmost computing system 100A is shown before memory translation is pre-loaded to cache 120
Computing system state, and the computing system 100B of rightmost show by memory translation be pre-loaded to cache 120
In after computing system state.
Computing system 100 includes management program 105, VM 107A, VM 107B, and processor 115 and is deposited at cache 120
Reservoir 125.Management program 105 (that is, virtual machine monitor) is to manage and execute VMs 107 in computing system 100 (also referred to as to patrol
Volume subregion or LPARs) software and/or hardware.In general, management program 105 is VMs 107 and the hardware in computing system 100
Medium between (for example, processor 115).As shown, OS 110A are the operating system of VM 107A, and OS 110B are VM
The operating system of 107B.
In one embodiment, it is (and its right to be currently executing which VM 107 for 105 control processor 115 of management program
The OS 110 answered).In other words, management program 105 can be with the processing time of dispatch processor 115 so that when different processing
Between block be assigned to the different VM 107 in computing system 100.In this example, VM 107A are currently scheduled as using processing
Device 115.In this way, as shown in the dotted line frame in processor 115, processor 115 is executed to be provided by the process operated in OS 110A
Instruction.Although Fig. 1 illustrates only two VM107, computing system 100 may include the dividing processing on processor 115
Any amount of VMs of time.
Processor 115 indicates that any amount of processing element, each processing element may include one or more process cores
The heart.If processor 115 includes multiple cores, in one embodiment, can dispatch VM107 is made with block in different times
With each core.For example, the OS 110A of VM 107A can be scheduled as using the first core in processor 115, and VM
The OS 110B of 107B are scheduled as using the second core in processor 115.Alternatively, within the period that they are scheduled,
VMs 107 can use entire processor 115 (it includes multiple cores).For example, all cores in processor 115 can be held
The instruction that row is issued by OS 110A.Although VM 107A are scheduled as using processor 115, the OS 110B of VM 107B can
To be idle, i.e., management program 105 stops at the process run on OS 110B until it is used scheduled in processor 115
Time.
Cache 120 can be any memory element between processor 115 and memory 125.Cache
120 and memory 125 formed for computing system 100A memory hierarchical structure a part.In one embodiment, high speed
Caching 120 is stored in the subdivision of the data in memory 125.When executing read or write request, processor 115 can
The data in cache 120 are searched for before data first in searching storage 125.Although cache 120 usually compares
Memory 125 is small, but the memory element for forming cache 120 can be accessed quickly.For example, cache 120 can be with
It is made of RAM or flash memory, and memory 125 can be hard disk drive, tape drive, external data storage server, cloud
Storage or other non-volatile memory devices.
In one embodiment, cache 120 can be the memory member in the integrated circuit (IC) for be formed processor 115
Part-such as L1 caches, L2 caches, L3 caches etc..In another embodiment, cache 120 can be
Be placed on the mainboard in computing system 100 main memory (e.g., including the random access memory (RAM) of DRAM or SRAM is set
It is standby).Although it is not shown, but cache 120 can store the page table including page table entries, the page table entries correspond to by OS
The process that 110A is executed.Processor 115 can using these page table entries come map virtual address to physical address (otherwise also
So).
In Fig. 1, memory 125 includes the memory translation 130 for OS 110B.That is, even if processor 115 is current just
OS 110A are being executed, computing system 100 has also prestored the memory translation 130 corresponding to OS 110B.As detailed below
Description, when processor 115 had previously been carrying out OS 110B, computing system 100 may save memory translation 130.
As shown in the computing system 100B of rightmost, management program 105 will be for 130 movement of the memory of OS 110B translation
Into cache 120.In one embodiment, management program 105 is in response to determining that VM 107A will using processor 115
Terminate and next VM 107B will move memory translation 130 using the scheduling time of processor 115.In other words, it is handling
Before device 115 is switched to OS 110B from execution OS 110A, management program 105 starts memory translation 130 being moved in memory
Closer to processor 115 in hierarchical structure.Since OS 110A and 110B can execute the difference using different virtual address spaces
Process, so before memory translation 130 is moved to cache 120 from memory, cache 120 can only store use
In the memory translation information of OS 110A.That is, during the time that OS 110A are executed on processor 115, it to be used for OS
Any memory translation of 110B may be removed from cache 120.
In one embodiment, which memory is computing system 100 can determine using least recently used (LRU) strategy
Translation to be retained in cache 120 and which to fail-be moved to memory 125.Because when OS 110A are being handled
When being carrying out in device 115, the memory translation corresponding to the virtual address used by OS 110B is not used, these memories turn over
It translates and is managed programming indicia and is removed from cache 120.Therefore, it is held when management program 105 is switched to from execution OS 110A
When row OS 110B, cache 120 can only include the memory translation for OS 110A.However, as shown in Figure 1, management journey
Sequence 105 will be pre-loaded to for the memory of the selection of OS 110B translation 130 in cache 120.Therefore, when OS 110B start
When being executed in processor 115,130 are translated in cache 120 corresponding at least some memories of OS 110B, and because
If this can must wait until that fetching memory translation from storage device 125 is quickly accessed than processor 115.Therefore,
Preload memory translation 130 can from execute OS 110A be switched to OS 110B when relative to not by memory translation be pre-loaded to
Computing system in cache 120 increases the handling capacity of processor 115.
Fig. 2 is the stream according to the method 200 for preloading memory translation when switching VM of one embodiment described herein
Cheng Tu.For the ease of explaining, discuss the different masses of method 200 in conjunction with Fig. 3-6, Fig. 3-6 show it is corresponding with method 200 not
Same example.In block 205, management program will be saved in journal file corresponding to the memory translation in the page table of the first VM.At one
In embodiment, management program preserves memory during the time of the processor in dispatching the first VM using computing device and translates.It is false
If the first VM is given predetermined time block to use processor, when management program determines the first VM only and has such as its residue
Between 10%, then management program start to preserve and be translated with the associated memories of OS for the first VM.
Fig. 3 is the computing system 300 translated according to the stored memory when switching out VM of one embodiment described herein
Block diagram.As shown in the example, processor 115 currently executes OS110B corresponding with VM107B.Because of the scheduling time of VM 107B
It will expire, so management program 105 starts to preserve some entries 310 of the page table of OS 110B.Specifically, management program 105
The page table entries 320 of one or more selections for OS 110B are saved in daily record 315.Although daily record 315 is shown in storage
In device 125, but daily record 315 can also be located in hierarchical structure from processor 115 compared to 120 farther high speed of cache
Caching.For example, cache 120 can be the special cache for storing page table, and daily record 315 is stored in main memory
In.In one embodiment, the selected page table entries 320 of the current OS for being executed are stored in by management program 105
When next VM starts to execute on processor 115, in the core position that will not be capped.
Computing system 300 further includes for executing the virtual TLB305 to physical address translation asked by processor 115.
In one embodiment, TLB 305 is considered a part of entry 310 in the page table for being stored only for OS 110B
The type of cache.For example, TLB305 can be the association memory above cache 120 in memory hierarchical structure
(for example, Content Addressable Memory (CAM))-that is, TLB305 than cache 120 closer to processor 115.So when execution
When memory is translated, whether processor 115 inquires TLB305 first virtually stored therein to physical mappings to determine.If no
It is that then then processor 115 traverses the page table entries mesh 310 in cache 120.However, cache 120 is (for example, in main
Deposit) memory element that may be not enough stores all page tables of the entire virtual address space corresponding to computing system 300.
For example, as TLB 305, cache 120 can be stored only for a part of page table entries of computing system 300.Therefore,
If cache 120 does not have desired mapping, processor 115 can retrieve virtual address from memory 125, store
Device 125 can include the copy of all page tables in computing system 300.
Management program 105 can be determined using various technologies before the time for being dispatched to VM 107B expires, page table
Which entry 310 should be stored in daily record 315.In one embodiment, the selection of management program 105 is stored in TLB 305
In page table entries as the page table entries 320 being stored in daily record 315.That is, because in many computing systems,
TLB 305 stores computing system and it is expected or predict to be likely to require the page table entries for executing memory translation in the future, then management program
105 can store the page table entries of TLB 305 to daily record 315.Therefore, when VM 107B are scheduled as using processor again
When 115, which is saved in daily record 315.
In another embodiment, when executing address translation to store in daily record 315, at 105 identification of management program
Manage the page table entries that device 115 uses (MRU) recently.For example, management program 105 can only select the page accessed by processor 115
List item in nearest 50 milliseconds to execute memory translation.Optionally, management program 105 can keep each page table entries 310
Counting, indicate while OS 110B are carrying out each entry be used to execute memory translation number.Management program
105 can only select to count the page table entries more than least count.In another example, management program 105 can will select
Page table entries 320 quantity be limited to fixed amount (for example, only five Mbytes) and select have highest count Xiang Zhi
To meet fixed amount-that is, selection have highest count entry first five Mbytes.
Example for being currently performed OS selection page table entries 320 provided above is intended as non-limiting show
Example.Those skilled in the art deposit it will be recognized that when corresponding VM is scheduled as executing on processor 115 again
In many different technologies for selecting the most possibly page table entries by operating system access.In addition, in one embodiment,
Management program 105 can will be stored for all entries 310 of the page table of OS 110B into daily record 315, rather than select storage
The subdivision of page table entries in cache 120.
Although in figure 3, before the scheduling time of VM 107B has expired, it is stored in selected in daily record 315
Page table entries 320 are identified, but in another embodiment, management program 105 can select one after the time expires
Or multiple page table entries 320.For example, stopping executing OS 110B in processor 115 and starting to deposit between execution OS 110A
In some downtimes.During this period, management program 105 can select which page table entries 320 being stored in daily record 315.
In addition, management program 105 can processor 115 start to select after executing OS 110A some or all page table entries 320 with
It is stored in daily record 315.Because being replaced currently in TLB 305 and height in page table entries of the processor 115 corresponding to OS 110A
Some times may be needed before page table entries in speed caching 120, so management program 105 may having time assessment TLB
305 and/or cache 120 in entry determine which entry will be stored in daily record 315.
Method 200 is returned to, in frame 210, processor is switched to the 2nd VM of execution from the first VM is executed.As described above, calculating
Each VM in system can be assigned specific time block to execute.Therefore, for distributing to the time block of VM, processor is held
The instruction that the hand-manipulating of needle pair OS corresponding with VM is received, and other VM are idle.That is, processor does not execute for non-scheduled
VMs instruction.
Fig. 4 is the frame according to the computing system 300 of one embodiment described herein switched between VM 107
Figure.With Fig. 3 on the contrary, in computing system 300, processor 115 now execute from OS 110A rather than what OS 110B were received
Instruction.Since 305 caches of TLB are used for page table entries (the operation system previously executed on processor 115 of OS 110B
System), processor 115, which represents many (if not all) translation request that OS 110A are submitted, will lead to cache miss.As
Response, computing system 300 are held in the page table entries in being stored in cache 120 (for example, main memory of computing system 300)
The row page traverses.However, cache 120 can have limited storage capacity-for example, the page table item of set amount can be stored only
Mesh.In one embodiment, computing system 300 can limit the memory for the cache 120 that can be used for storing page table entries
Amount.For example, cache 120 can be main memory, wherein 2% cache 120 is preserved for page table entries, and other
98% be preserved for the data asked by OS 110.In this way, computing system 300 may not be able to be stored for cache
The page table entries of all different VMs 107 in 120.
For example, in figure 3, cache 120 can mainly store the page table entries 310 for OS 110B.As a result, by
Many memory translation requests that MMU in processor 115 is submitted will lead to the miss in cache 120.In response,
Computing system 300 can retrieve the page table entries corresponding to OS 110A from memory 125, this may need hundreds thousand of processing
The device period.
Fig. 4 shows that computing system 300 is previously stored in the replacement of page table entries 405 of OS 110A in cache 120
Entry result.Although it is not shown, the entry in TLB 305 can also be updated to include for OS 110A without
It is the page table entries of OS 110B.Now, the translation request submitted by processor 115 is more likely to result in TLB 305 or high speed is slow
The hit in 120 is deposited, to eliminate the needs of inquiry storage 125.This can increase the speed that processor 115 completes instruction,
Because the page table entries that access is stored in TLB 305 and cache 120 may need fewer than accessing data from memory 125
Process cycle much.
Back to method 200, at frame 215, management program will correspond to the before the time restriction of the 2nd VM is completed
The memory translation of one VM is loaded into closer in the memory hierarchy of processor.That is, when processor still execute for pair
Should be when the instruction of the OS of the 2nd VM, management program starts to translate from memory hierarchical structure corresponding to the memory of the OS of the first VM
Relatively low rank be loaded into higher level, such as enter main memory from memory.
Fig. 5 is the computing system that memory translation is preloaded before switching VM according to one embodiment described herein
Block diagram.In Figure 5, processor 115 still carries out the instruction received from OS 110A.However, management program 105 will be used for
The selected page table entries 310 of OS 110B are moved to from the daily record 315 in memory 125 in cache 120.Implement at one
In example, the predetermined time before VM 107A and VM 107B are switched out, management program 105 can start the page table that will be selected
Item 320 is moved in cache 120, such as a microsecond before handover, or when VM 107A only remaining remaining times
When 5%.In one example, before processor 115 is switched to and executes OS 110B, management program 105 may not be by institute
There is entry 320 to be moved in cache 120.Nevertheless, even if before OS 110B start execution, entry 320 does not complete
It is moved into cache 120, management program 105 at least also begins to stop the page table entries 320 of OS 110B in processor 115
Before only executing the instruction for OS 110A, it is moved in cache 120.In other words, management program 105 is VM 107A's
Processing time starts to copy to the page table entries 320 for being used for OS 110B into the process in cache 120 before terminating.
In one embodiment, when processor 115 is still when executing OS 110A, management program 105 can be completed will be selected
The page table entries 320 selected are moved in cache 120.Because the size of cache 120 may be limited (to keep for page
Number of entries in the cache of table clause may be fixed), management program 105 can selectively determine OS 110A
Which page entries 405 are removed to discharge the core position of the page table entries 320 of OS 110B.In other words, management program
The page table entries 320 of OS 110B are replaced in 105 selections for which page table entries 405 of OS 110A.
In one embodiment, when executing OS 110A to distribute to the remaining time of VM 107A, management program 105 can
To determine which page table entries 405 are most unlikely used by processor 115.By doing so, management program 105 will be hopeful to keep away
Exempt to remove page table entry 405 for OS 110A, then the page table entry 405 must take out from memory 125, to slow down OS 110A
Execution.In other words, management program 105 can predict which page table processor 115 most unlikely uses when executing OS 110A
Entry 405, and those entries 405 are only removed from page table to be 320 vacating space of page table entries for OS110B.
In one embodiment, management program 105 using least recently used (LRU) algorithm come select will be from cache
The page table entries 405 removed in 120.When so done, 105 selection processor of management program, 115 most common page table entries 405
To execute memory translation, the page table entries 320 for OS 110B replace those entries.In another example, pass through monitoring
Historical data, management program 105 can be identified when processor 115 stops which page table entries the when of executing OS 110A usually accesses
(and which is not accessed) and only remove the entry being not frequently used.For example, processor 115 can use identical page
Identical attended operation is executed when switching between the VM107 of table clause.By the way which page table entries identified during attended operation
405 are used, these entries can be retained in cache 120 by management program 105, while remove other entries.Ability
Domain skilled artisan will realize that, these examples are only used for predicting which page table entries will be by (or will not) in the future
It can be applied to some in the different technologies of the embodiments described herein.
Although Fig. 5, which is shown, to be moved to cache 120 from memory 125 for the page table entries 320 of OS 110B,
But in another embodiment, before management program 105 is switched to VM 107B from VM 107A, page table entries 320 can be with
It is moved in TLB 305.That is, management program 105 can be by one or more page table entries 320 for OS110B
Switch out one or more of TLB305 entries.Although being replaced with the entry 320 for OS 110B all in TLB 305
Entry may not be desired, because doing so the translation request for significantly increasing and being submitted when executing OS 110A leads to TLB not
The chance of hit, replace some entries be likely to reduced when processor 115 start execute OS 110B when must inquire memory 125
Search the possibility of page table entries.
In addition, in one embodiment, once processor 115 is switched to OS 110B, management program from OS 110A are executed
105 can remove the remaining page table entries 405 for OS 110A from cache 120 and/or TLB 305.For example, if
Management program 105 is known when executing OS 110B never or almost from the page table entries being not used for OS 110A, then manages
Program 105 can continue to remove the remaining entry in cache 120 or TLB 305, and the page table entries 320 of selection is used in combination to replace it
.In one embodiment, once processor 115 stops executing OS 110A and starts to execute OS 110B, when OS 110A still exist
When being executed on processor 115, the page table entries 320 being saved in cache 120 can be moved to TLB by management program 105
In 305.
When page table entries 320 are moved in cache 120, the selection of computing system 300 is stored in cache 120
And/or the page table entries 505 for OS 110A in TLB 305, and these entries are saved in daily record 315.In this way, working as
VM 107A are switched back to, management program 105 will can be moved to height for the entry 505 of OS 110 from daily record 315 as described above
In speed caching 120 or TLB 305.In one example, management program 105 can select which entry 505 for OS 110A
It is saved in daily record 315, while memory level will be moved to from daily record 315 for the selected page table entries 320 of OS 110B
The upper layer-i.e. of structure cache 120 or TLB 305.
Method 200 is returned to, at frame 220, the memory of processor inquiry load is translated to be held after being switched to the first VM
The virtual address translation that arrives physics of the row for the first VM.In other words, computing system has begun that the first VM will be used at least
Some page table entries move closer to memory hierarchy-such as main memory or TLB of processor from memory, without from depositing
Reservoir movement is corresponding to waiting before the page table entries of the first VM until TLB miss and cache-miss.In a reality
It applies in example, some page table entries for the first VM are already stored in main memory or TLB, need not to increase computing system
It goes to store to meet in the chance for executing the memory translation request submitted when the instruction by the OS submissions for the first VM.Here
It is known as preheating TLB by the page table entries for the first VM are moved to the higher level in memory hierarchical structure from memory.I.e.
Make before processor starts to execute the OS of the first virtual machine, the page table entries for the first virtual machine are not actually moved to
In TLB, due to when processor starts to execute OS really, embodiment here, which improves TLB miss and need not inquire, deposits
The possibility of reservoir, doing so still can preheat TLB.Delay on the contrary, at least some page table entries of the first VM can be located at high speed
In depositing-for example, main memory-its access speed is much faster.
Fig. 6 is the block diagram according to the computing system 300 of one embodiment described herein switched between different VM.
As shown, processor 115, which is switched to from execution OS 110A (as shown in Figure 5), executes OS 110B.In this example,
Page table entries for OS 110A are removed from cache 120, and are taken by the page table entries 605 for OS 110B
Generation.In one embodiment, after executing the OS 110B sufficiently long times, for the OS 110A's in cache 120
The page table entries 605 that all page table entries 405 may be only used for OS 110B are replaced.Similarly, although it is not shown, TLB
Entry in 305 may be replaced relative to the entry of the TLB 305 at the time represented by Fig. 5.
Although some page table entries 605 for OS 110B may be pre-loaded in cache 120, such as Fig. 5
It is shown, but the remainder of entry 605 can after processor 115 starts to execute OS 110B-i.e. when computing system 300
It is loaded from executing when VM 107A are switched to execution VM 107B.For example, processing element 115 can submit it is pre- including not corresponding to
The translation request of one virtual address in the page table entries of load.In this case, computing system 300 is from storage device
Corresponding page table entries are retrieved in 125.Therefore, although some page table entries 605 may be pre-loaded to cache 120
In (and/or TLB 305), but computing system 300 can be retrieved after processor 115 starts execution OS 110B from memory
Other page table entries for OS 110B.
Once the processing time of VM 107B begins to shut off, method 200 can repeat.That is, as shown in figure 3, cutting
Before gaining VM 107A, selected entry can be saved in from page table entries 605 in daily record 315 by management program 105.
In addition, management program 105 can start 505 pre-add of page table entries of the selection for the OS 110A that will be used to be stored in daily record 315
It is downloaded in cache 120, it is expected to be switched to VM 107A from VM 107B.As described above, management program 105 can remove height
Some page table entries 605 of OS 110B in speed caching 120, with for 505 vacating space of selected page table entries.
The description of various embodiments of the present invention has been presented for purposes of illustration, but is not intended to limit or is limited to
The disclosed embodiments.In the case where not departing from the scope and spirit of described embodiment, for the common skill of this field
For art personnel, many modifications and variations will be apparent.It is to best explain reality to select term as used herein
The principle for applying example, the practical application relative to the technology found in the market or technological improvement, or make the common skill of this field
Art personnel are it will be appreciated that embodiment disclosed herein.
In front, with reference to the embodiment presented in the disclosure.However, the scope of the present disclosure is not limited to the implementation specifically described
Example.On the contrary, regardless of whether being related to different embodiments, any combinations of above-mentioned feature and element are all envisioned for realization and reality
Trample expected embodiment.In addition, although embodiment disclosed herein may be implemented to possible solution better than other or existing
The advantages of technology, but whether realize that specific advantages are not intended to limit the scope of the present disclosure by given embodiment.Therefore, it retouches here
The aspect stated, feature, embodiment and advantage are merely illustrative, and are not considered as the element or limit of appended claims
System, unless clearly stating in the claims.Similarly, the reference of " present invention " is not necessarily to be construed as to disclosed herein
The summary of any subject matter, and it is not considered as element or the limitation of appended claims, unless in the claims
It is expressly recited.
The aspect of the present invention can take whole hardware embodiments, complete software embodiment (including firmware, resident software,
Microcode etc.) or integration software and hardware aspect embodiment form, may be generally referred to as " circuit " herein,
" module " or " system ".
The present invention can be system, method and/or computer program product.Computer program product may include having thereon
It is useful for making the computer readable storage medium that processor executes the computer-readable program instructions of each aspect of the present invention (or more
A medium).
Computer readable storage medium can be can preserve and store the instruction used for instruction execution equipment tangible
Equipment.Computer readable storage medium can be such as but not limited to electronic storage device, magnetic storage apparatus, light storage device,
Electromagnetism storage device, semiconductor memory apparatus or any suitable combination above-mentioned.Computer readable storage medium it is more specific
Exemplary non-exhaustive list includes following：Portable computer diskette, hard disk, random access memory (RAM), read-only memory
(ROM), Erasable Programmable Read Only Memory EPROM (EPROM or flash memory), static RAM (SRAM), portable optic disk
Read-only memory (CD-ROM), digital versatile disc (DVD), memory stick, floppy disk, the device mechanically encoded, such as with
Record has card punch in the groove of instruction or bulge-structure and any suitable combination above-mentioned thereon.Used here as
Computer readable storage medium be not interpreted temporary signal itself, the electromagnetism of such as radio wave or other Free propagations
Wave, the electromagnetic wave propagated by waveguide or other transmission mediums (for example, across light pulse of fiber optic cables) or is passed by conducting wire
Defeated electric signal.
Computer-readable program instructions described herein can be downloaded to from computer readable storage medium corresponding calculating/
Processing equipment, or download to outer computer via network (such as internet, LAN, wide area network and/or wireless network)
Or External memory equipment.Network may include copper transmission cable, optical delivery fiber, wireless transmission, router, fire wall, exchange
Machine, gateway computer and/or Edge Server.Adapter or network interface in each calculating/processing equipment are from network
Computer-readable program instructions are received, and computer-readable program instructions are forwarded for being stored in corresponding calculating/processing equipment
In interior computer readable storage medium.
Can be assembly instruction, instruction set architecture (ISA) for executing the computer-readable program instructions that the present invention operates
Instruction, machine instruction, machine-dependent instructions, microcode, firmware instructions, condition setup data or source code or with one or more
Programming language (including object oriented program language, such as Smalltalk, C++ etc.) and such as " C " program is set
Meter language or the object code write similar to any combinations of the conventional procedural programming language of programming language.Meter
Calculation machine readable program instructions can completely on the user computer, partly on the user computer, as independent software package, part
On the user computer, partly on the remote computer, it or executes on a remote computer or server completely.In latter
In the case of, remote computer can pass through the computer of any kind of network connection to user, including LAN (LAN) or wide
Domain net (WAN), or the connection of outer computer is may be coupled to (for for example, passing through using Internet Service Provider mutual
Networking).In some embodiments, including such as programmable logic circuit, it field programmable gate array (FPGA) or programmable patrols
The electronic circuit of volume array (PLA) can execute computer-readable by using the status information of computer-readable program instructions
Program instruction is with individual electronic circuit, to execute various aspects of the invention.
Referring herein to according to the method for the embodiment of the present invention, the flow chart of device (system) and computer program product and/
Or block diagram describes each aspect of the present invention.It will be appreciated that flowchart and or block diagram in each frame and flow chart and/
Or the combination of the frame in block diagram can be realized by computer-readable program instructions.
These computer-readable program instructions are provided to all-purpose computer, special purpose computer or other programmable datas
The processor of processing unit is to generate machine so that is executed via computer or the processor of other programmable data processing devices
Instruction create for realizing in one or more frames of flowchart and or block diagram specify function action device.These
Computer-readable program instructions are also stored in computer readable storage medium, which can be with
Computer, programmable data processing device and/or other equipment is instructed to run in a specific way so as to be wherein stored with instruction
Computer readable storage medium includes manufacture article comprising is realized in one or more boxes of flowchart and or block diagram
The instruction of the aspect of specified function action.
Computer-readable program instructions can also be loaded into computer, other programmable data processing devices or other set
It is standby upper, so that executing series of operation steps in computer, on other programmable devices or other equipment to generate computer
The process of realization so that the instruction that is executed on computer, other programmable devices or other equipment realize in flow chart and/or
The function action specified in one or more frames of block diagram.
Flow chart and block diagram in attached drawing illustrate system according to various embodiments of the present invention, method and computer journey
The framework in the cards of sequence product, function and operation.In this regard, each frame in flowchart or block diagram can indicate include
For realizing the module of the instruction of one or more executable instructions of specified logic function, section or part.In some replacements
In embodiment, the function of being mentioned in box can not occur according to the sequence marked in attached drawing.For example, depending on involved
Function, two frames continuously shown can essentially substantially simultaneously execute or frame can execute in reverse order sometimes.
It is also noted that the combination of each frame in block diagram and or flow chart and the frame in block diagram and or flow chart can pass through
It executes specific function or behavior or execute specific use hardware and computer instruction combination carrys out reality based on the system of specialized hardware
It is existing.
Although foregoing teachings are directed to the embodiment of the present invention, without departing from the essential scope may be used
With other and the further embodiment of the design present invention, and the scope thereof is determined by the claims that follow.
Claims (20)
1. a kind of method, including：
The first operating system (OS) for corresponding to the first virtual machine (VM) is executed using processor in first time period；
Before the first time period expires, by the way that the page table entries are moved to from the relatively low rank of memory hierarchical structure
Higher level preloads the page table entries of the 2nd OS corresponding to the 2nd VM, wherein the more relatively low rank of the higher level more connects
Processor in nearly memory hierarchical structure；And
After the first time period expires, is executed using processor in second time period and correspond to the second of the 2nd VM
OS。
2. the method for claim 1, wherein the first time period, which corresponds to, distributes to the predefined of the first VM
Period, and the second time period corresponds to the time predefined section for distributing to the 2nd VM.
3. method as claimed in claim 2, wherein described when executing an OS during the first time period
2nd OS is idle, and when executing two OS during the second time period, and the first OS is idle.
4. the page table entries are the method for claim 1, wherein moved to higher level from relatively low rank includes：
The page table entries are moved to random access memory (RAM) equipment from the journal file in storage device.
5. the method as described in claim 1 further includes：
Before first and second period, the 2nd OS is executed using processor during the third period；And
Before the first time period, selection corresponds to one or more page table entries of the 2nd OS to be stored in memory
In the relatively low rank of hierarchical structure.
6. method as claimed in claim 5, wherein selection includes corresponding to one or more page table entries of the 2nd OS：
When executing two OS on a processor during the third period, determine that most recently used (MRU) is described
One or more page table entries are to execute memory address translation.
7. method as claimed in claim 5, further includes：
Before starting to execute the first OS during the first time period, selected one or more page table entries are protected
It is stored to non-volatile memory device.
8. the method as described in claim 1, wherein the page table entries for preloading the 2nd OS for corresponding to the 2nd VM include：
Before page table entries are moved to higher level from relatively low rank, least recently used (LRU) algorithm, selection pair are used
One or more of higher level of first OS page table entries described in Ying Yu；And
Before the page table entries are moved to higher level from relatively low rank, removed from the higher level of memory hierarchical structure
Corresponding to selected one or more page table entries of the first OS.
9. a kind of computing system, including：
Processor is configured as executing the first operating system (OS) corresponding to the first virtual machine (VM) in first time period；With
Management program is configured as：
Before the first time period expires, by the way that the page table entries are moved to from the relatively low rank of memory hierarchical structure
Higher level preloads the page table entries of the 2nd OS corresponding to the 2nd VM, wherein the more relatively low rank of the higher level more connects
Processor in nearly memory hierarchical structure, and
After the first time period expires, indicates that the processor starts to execute in second time period and correspond to described second
The 2nd OS of VM.
10. computing system as claimed in claim 9, wherein the first time period, which corresponds to, distributes to the pre- of the first VM
The period is defined, and the second time period corresponds to the time predefined section for distributing to the 2nd VM.
11. computing system as claimed in claim 10, wherein when executing the first OS during the first time period
When, the 2nd OS is idle, and when executing two OS during the second time period, and the first OS is idle.
12. computing system as claimed in claim 9, wherein the management program be configured as when by the page table entries from
When relatively low rank is moved to higher level, the page table entries are moved to arbitrary access from the journal file in storage device and are deposited
Reservoir (RAM) equipment.
13. computing system as claimed in claim 9, wherein the management program is configured as：At described first and second
Between indicate that processor executes the 2nd OS during the third period before section；And
Before the first time period, selection corresponds to one or more page table entries of the 2nd OS to be stored in memory
In the relatively low rank of hierarchical structure.
14. computing system as claimed in claim 13, wherein one or more of pages of the selection corresponding to the 2nd OS
Table clause includes：
When executing two OS on a processor during the third period, determine that most recently used (MRU) is described
One or more page table entries are to execute memory address translation.
15. computing system as claimed in claim 13, wherein the management program is configured as：
Before starting to execute the first OS during the first time period, selected one or more page table entries are protected
It is stored in non-volatile memory device.
16. computer program product of the one kind for switching between virtual machine (VM), the computer program product include：
Computer readable storage medium has the computer readable program code being included in, the computer-readable journey
Sequence code can by one or more computer processors execute with：
Indicate that processor executes the first operating system (OS) corresponding to the first VM in first time period；
Before the first time period expires, by the way that the page table entries are moved to from the relatively low rank of memory hierarchical structure
Higher level preloads the page table entries of the 2nd OS corresponding to the 2nd VM, wherein the more relatively low rank of the higher level more connects
Processor in nearly memory hierarchical structure；And
After the first time period expires, indicate that the processor is executed in second time period corresponding to the 2nd VM's
2nd OS.
17. computer program product as claimed in claim 16, wherein the first time period, which corresponds to, distributes to described the
The time predefined section of one VM, and the second time period corresponds to the time predefined section for distributing to the 2nd VM.
18. computer program product as claimed in claim 17, wherein when executing described during the first time period
When one OS, the 2nd OS is idle, and when executing two OS during the second time period, and the first OS is empty
It is not busy.
19. computer program product as claimed in claim 16, wherein the computer readable program code can also carry out with：
Indicate that processor executes the 2nd OS during the third period before first and second period；And
Selection corresponds to one or more page table entries of the 2nd OS to be stored in memory before the first time period
In the relatively low rank of hierarchical structure.
20. computer program product as claimed in claim 16 corresponds to the 2nd VM corresponding second wherein preloading
The page table entries of OS include：
Before page table entries are moved to higher level from relatively low rank, least recently used (LRU) algorithm, selection pair are used
One or more of higher level of first OS page table entries described in Ying Yu；And
Before the page table entries are moved to higher level from relatively low rank, removed from the higher level of memory hierarchical structure
Corresponding to selected one or more page table entries of the first OS.
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| US14/925,651 | 2015-10-28 | ||
| PCT/IB2016/055772 WO2017072610A1 (en) | 2015-10-28 | 2016-09-27 | Pre-loading page table cache lines of a virtual machine |
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| CN111552653A (en) * | 2020-05-14 | 2020-08-18 | 上海燧原科技有限公司 | Page table reading method, device and equipment and computer storage medium |
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| US10534715B2 (en) | 2016-04-22 | 2020-01-14 | International Business Machines Corporation | Operation of a multi-slice processor implementing a unified page walk cache |
| CN107450958A (en) * | 2017-08-20 | 2017-12-08 | 长沙曙通信息科技有限公司 | A kind of desktop virtualization intelligent management mirror image template preloads implementation method |
| CN108052538B (en) * | 2017-11-16 | 2020-09-08 | 成都视达科信息技术有限公司 | Page loading method and system |
| JP2019160253A (en) * | 2018-03-16 | 2019-09-19 | 株式会社リコー | Information processing system, control method for information processing system, and control program for information processing system |
| CN110162373B (en) * | 2019-05-28 | 2022-07-19 | 创新先进技术有限公司 | Method and device for displaying chart in webpage |
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| GB2559289A (en) | 2018-08-01 |
| US9904569B2 (en) | 2018-02-27 |
| US20170123833A1 (en) | 2017-05-04 |
| US9910780B2 (en) | 2018-03-06 |
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| GB201807592D0 (en) | 2018-06-27 |
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| JP6916782B2 (en) | 2021-08-11 |
| GB2559289B (en) | 2019-01-09 |
| JP2018536219A (en) | 2018-12-06 |
| US20170123986A1 (en) | 2017-05-04 |
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