JPH04219842A - Cache control system - Google Patents

Abstract

PURPOSE:To increase the hit rates of a cache for main storage access and an address conversion cache even right after a set of memory spaces that a central arithmetic unit accesses changes abruptly. CONSTITUTION:If an event such as process switching, interruption, and supervisor calling wherein an abrupt change of memory spaces that the central arithmetic unit accesses changes abruptly is generated, a saving means 3 saves the contents of a cache 1 before the event generation in a saving area 5 for afterward use and a loading means 1 loads the cache contents to be used after the event generation to the cache 1 from the saving area 5 to restructure the cache 1.

Description

[Detailed description of the invention]

0001

[Industrial Application Field] The present invention relates to an electronic computer having a cache such as a main memory access cache that holds a copy of the contents of the main memory and an address translation cache that is used to convert virtual addresses to real addresses. , and in particular, their cache control methods.

0002

2. Description of the Related Art Conventionally, a main memory access cache that holds a copy of a portion of the contents stored in the main memory is provided in a central processing unit, consisting of a memory, registers, etc. that can be accessed at high speed. The contents of the main memory access cache are updated based on a predetermined algorithm each time the main memory access cache is accessed, so that frequently accessed instructions and data are stored in the main memory access cache with a high probability. If the corresponding content exists in the main memory access cache when fetching instructions or data from the main memory access cache, the desired content can be fetched from the main memory access cache at high speed without actually accessing the main memory. .

[0003] Furthermore, in electronic computers using a virtual memory system, an address translation cache that holds address translation information, which is the result of translation from a virtual address to a real address, is configured with memory, registers, etc. that can be accessed at high speed, and the central processing unit and update the contents of the address translation cache based on a predetermined algorithm for each address translation so that address translation information for frequently used virtual address parts is stored in the address translation cache with a high probability, If address translation information in the address translation cache can be used during address translation, address translation can be performed at high speed without actually calculating address translation.

0004

[Problems to be Solved by the Invention] By using the above-mentioned main memory access cache and address translation cache, it is possible to operate faster than an electronic computer that does not use them.

However, the hit rate increases only when the contents of the main memory access cache and address translation cache are updated by frequently accessing the same set of memory spaces. Immediately after a sudden change in the set of memory spaces accessed by the central processing unit, such as when a supervisor call is made, it is often of little use for a while, and conventional methods have been to improve the hit rate by increasing the cache capacity of subsequent memory accesses. I relied on updates. The present invention solves these conventional problems, and its purpose is to provide a cache control method that can increase the cache hit rate even immediately after a sudden change in the set of memory spaces accessed by the central processing unit. Our goal is to provide the following.

[0006]

[Means for Solving the Problems] In order to achieve the above object, the present invention provides a cache such as a main memory access cache, an address translation cache, etc. whose contents are updated by an updating means 2, as shown in FIG. 1, events that are expected to cause sudden changes in the save area 5 where the contents of cache 1 are saved and the memory space accessed by the central processing unit, such as process switching, interrupts, supervisor calls, etc. It has a save means 3 that saves the contents of the cache 1 before the occurrence of the event to the save area 5, and a load means 4 that loads the cache contents to be used after the occurrence of the event from the save area 5 to the cache 1.

[0007]

[Operation] In the cache control method of the present invention, when an event that is predicted to cause a sudden change in the memory space accessed by the central processing unit occurs, the save means 3 saves the contents of the cache 1 before the occurrence of the event. The content is saved in the save area 5 in preparation for its use, and the loading means 4 loads the cache contents to be used after the occurrence of the event from the save area 5 into the cache 1 to reconstruct the contents of the cache 1.

[0008]

Embodiments Next, embodiments of the present invention will be described in detail with reference to the drawings. FIG. 2 is a block diagram of an electronic computer to which a cache control method according to an embodiment of the present invention is applied, and the main memory access cache is the object of control.

In FIG. 2, 100 is a central processing unit;
00 is a main memory device, and the central processing unit 100 includes a main memory access cache 10 consisting of a memory and registers that can be accessed at high speed and holds a copy of a part of the contents of the main memory device 200, and a main memory By updating the cache management information of the main memory access cache 10 based on a predetermined algorithm each time the device 200 is accessed, frequently accessed instructions, operands, etc. are stored in the main memory access cache 10 with a high probability. Cache management information updating means 20 for storing cache management information; process switching means 71 for switching processes executed on central processing unit 100; interrupt processing means 72 for processing interrupts; and supervisor processing for supervisor calls. A call processing means 73 and a cache 10 for main memory access before an event such as a process switch, an interrupt, or a supervisor call occurs.
The cache management information saving means 30 saves the cache management information of the main memory access cache to a predetermined area of the main storage device 200, and the cache management information of the main memory access cache used after the occurrence of the above event is saved from the predetermined area of the main storage device 200. The cache management information loading means 40 is loaded into the main memory access cache 10.

Here, the main memory access cache 10
The cache management information includes a copy of the instruction code and operand of the main memory 200 held in the main memory access cache 10, a copy of the address thereof, information indicating the current control state by a predetermined algorithm, for example, LRU, etc. This information is information that is sufficient to later reproduce the state of the main memory access cache 10 at that time.

The main storage device 200 also has a system space 201 including a cache management information save area 51, and process-specific spaces 202 and 203 corresponding to processes, including cache management information save areas 52 and 53. Note that the initial value of each cache management information save area 51 to 53 may be such that the main memory access cache 10 is rebuilt to its initial state; however, if the memory space to be accessed can be predicted in advance, It is desirable that the main memory access cache 10 be constructed in a state that matches the above. In this embodiment, since it is easy to predict in advance the interrupt processing executed at the time of an interrupt and the supervisor call processing executed at the time of a supervisor call as described above, cache management information matching them is created in advance. and store it in the cache management information save area 51 of the system space 201,
Furthermore, we have adopted a configuration in which they are not saved during execution. Of course, it is possible to adopt a configuration that saves these as well.

Next, the operation of this embodiment configured as described above will be explained below, focusing on the operation when each event of process switching, interrupt, and supervisor call occurs.

"Process Switching" When a process switching event occurs in the electronic computer shown in FIG. 1, the processing shown in FIG. 3 is started.

First, cache management information saving means 30
saves the cache management information of the current main memory access cache 10 in the cache management information save area existing in the process-specific space of the currently operating process (S10). That is, assuming that the process corresponding to the process specific space 202 is currently operating, the cache management information of the main memory access cache 10 is saved in the cache management information save area 52.

Next, the process switching means 71 switches the process (S11).

Next, cache management information loading means 40
However, by loading the cache management information saved in the cache management information save area existing in the process private space of the switched process into the main memory access cache 10, the main memory access cache 10
(S12). For example, process eigenspace 2
03, the main memory access cache 10 is rebuilt based on the cache management information saved in the cache management information save area 53.

[0017] The process switching process is now complete.
Thereafter, the switched process is executed using the reconstructed main memory access cache 10. here,
The cache management information loaded into the main memory access cache 10 for reconstruction is the cache management information that was saved when the previous process was switched and was sequentially updated under the execution environment of that process. A sufficiently high hit rate can be expected even immediately after execution.

"Interruption" When an interrupt occurs in the computer shown in FIG. 1, the processing shown in FIG. 4 is started.

When an interrupt occurs (S20), first,
The cache management information saving means 30 saves the cache management information of the current main memory access cache 10 in the cache management information save area existing in the process-specific space of the interrupted process (S21). For example, when an interrupt occurs during execution of a process corresponding to the process specific space 202, the cache management information of the main memory access cache 10 at that time is saved in the cache management information save area 52.

Next, cache management information loading means 40
By loading the cache management information stored in advance in the save area for interrupt processing in the cache management information save area 51 of the system space 201 into the main memory access cache 10, the main memory access cache 10 is restructured into one suitable for the interrupt processing environment (S22).

In this state, the interrupt processing means 7
2 performs interrupt processing (S23).

When the processing by the interrupt processing means 72 is completed, the cache management information loading means 40 loads the cache management information saved in the cache management information save area 52 of the process specific space 202 of the interrupted process for main memory access. By loading the data into the cache 10, the main memory access cache 10 is rebuilt to the state immediately before the interrupt (S24). This completes the interrupt handling and resumes execution of the original process (S
25). "Supervisor call" In the electronic computer shown in Figure 1, an executing process (for example, process specific space 2
When a supervisor call occurs from a process corresponding to 02), the process shown in FIG. 5 is started.

When a supervisor call occurs from a running process (S30), first, the cache management information saving means 30 stores the contents of the current main memory access cache 10 in the process private space 202 of the calling process. The information is saved in the cache management information save area 52 (S31).

Next, cache management information loading means 40
However, only when the user space is not accessed by a supervisor call, the cache management information previously stored in the save area for the supervisor call process in the cache management information save area 51 of the system space 201 is stored in the main memory access cache 10. By loading, the main memory access cache 10 is rebuilt into a state suitable for the environment of the supervisor call process (S32, S33).

Next, the supervisor call processing means 73
performs supervisor calling processing (S34).

When the process by the supervisor call processing means 73 is completed, the cache management information loading means 40
The main memory access cache 10 is loaded by loading the cache management information saved in the cache management information save area 52 of the process specific space 202 of the calling process into the main memory access cache 10.
is rebuilt to the state immediately before the supervisor was called (S3
5). This completes the supervisor call and resumes execution of the original process (S36).

FIG. 6 is a block diagram of a virtual memory type electronic computer to which a cache control method according to another embodiment of the present invention is applied, and the address translation cache is the object of control.

In FIG. 6, the central processing unit 100 has an address translation cache 11 composed of high-speed accessible memory, registers, etc. that holds address translation information that is the result of translation from a virtual address to a real address, and By updating the address translation information in the address translation cache 11 based on a predetermined algorithm every time, the address translation information for frequently used virtual address spaces is stored in the address translation cache 11 with a high probability. Address translation cache updating means 21, process switching means 71 for switching processes, interrupt processing means 72 for processing interrupts, supervisor call processing means 73 for processing supervisor calls, and events such as process switching, interrupts, and supervisor calls. The address translation cache save means 31 saves the address translation information in the address translation cache 11 before the occurrence of the above event to a predetermined area of the main storage device 200, and the address translation cache save means 31 saves the address translation information to be used after the occurrence of the above event to a predetermined area of the main storage device 200. and address translation cache loading means 41 for loading the address translation cache 11 from the area.

The main storage device 200 also has a system space 201 including an address translation information save area 61 and process-specific spaces 202 and 203 corresponding to processes, including address translation information save areas 62 and 63. Note that the initial value of each address translation information save area 61 to 63 may be the content that rebuilds the address translation cache 11 to its initial state, but if the memory space to be accessed can be predicted in advance, It is desirable that the content allows the address translation cache 11 to be rebuilt into a matching state. In this embodiment, since it is easy to predict in advance the interrupt processing executed at the time of an interrupt and the supervisor call processing executed at the time of a supervisor call as described above, address translation information matching them is created in advance. The information is stored in the address translation information save area 61 of the system space 201, and the configuration is such that they are not saved during execution. Of course, it is possible to adopt a configuration that saves these as well.

Next, the operation of this embodiment configured as described above will be explained below, focusing on the operation when each event of process switching, interrupt, and supervisor call occurs.

"Process Switching" When a process switching event occurs in the electronic computer shown in FIG. 6, the process shown in FIG. 7 is started.

First, the address translation cache save means 31 saves the current contents of the address translation cache 11.
Save in the address translation information save area that exists in the process-specific space of the currently running process (S40)
. For example, if a process corresponding to the process specific space 202 is currently operating, address translation information in the address translation cache 11 is saved in the address translation information save area 62.

Next, the process switching means 71 switches the process (S41).

Next, the address translation cache loading means 41 loads the address translation information saved in the address translation information save area in the process-specific space of the switched process into the address translation cache 11. The conversion cache 11 is rebuilt (S42). For example, when switching to a process corresponding to the process specific space 203, the address translation cache 11 is rebuilt based on the address translation information saved in the address translation information save area 63.

[0035] The process switching process is now complete.
Thereafter, the switched process is executed using the reconstructed address translation cache 11. Here, the address translation information loaded into the address translation cache 11 for reconstruction is the address translation information that was saved at the time of previous process switching and was updated sequentially under the execution environment of that process. A sufficiently high hit rate can be expected even immediately after execution.

"Interruption" When an interrupt occurs in the electronic computer shown in FIG. 6, the processing shown in FIG. 8 is started.

When an interrupt occurs (S50), first,
The address translation cache saving means 31 saves the address translation information of the current address translation cache 11 in the address translation information save area existing in the process-specific space of the interrupted process (S51). for example,
When an interrupt occurs during execution of a process corresponding to the process specific space 202, the address translation information in the address translation cache 11 at that time is saved in the address translation information save area 62.

Next, the address translation cache loading means 41 loads the address translation information stored in advance in the save area for interrupt processing in the address translation information save area 61 of the system space 201 into the address translation cache 11. By loading the address translation cache 1 into a state suitable for the interrupt processing environment.
1 is rebuilt (S52).

In this state, the interrupt processing means 7
2 performs interrupt processing (S53).

When the processing by the interrupt processing means 72 is completed, the address translation cache loading means 41 loads the address translation information saved in the address translation information save area 62 of the process specific space 202 of the interrupted process into the address translation cache 11. By loading the address translation cache 11 into the state immediately before the interrupt (S54). This completes the interrupt processing and resumes execution of the original process (S55). "Supervisor call" In the electronic computer shown in FIG.
When a supervisor call occurs from a process corresponding to 02), the process shown in FIG. 9 is started.

When a supervisor call occurs from a running process (S60), first, the address translation cache save means 31 saves the address translation information in the current address translation cache 11 to the process specific space 202 of the calling process. The address conversion information is saved in the address conversion information save area 62 (S61).

Next, only when the address translation cache loading means 41 does not access the user space by a supervisor call, the address translation cache load means 41 stores in advance in the save area for the supervisor call processing in the address translation information save area 61 of the system space 201. By loading the address translation information into the address translation cache 11, the address translation cache 11 is rebuilt into a state suitable for the environment of the supervisor call process (S6
2, S63).

Next, the supervisor call processing means 73
performs supervisor calling processing (S64).

When the process by the supervisor call processing means 73 is completed, the address translation cache load means 41 loads the process private space 202 of the called process.
By loading the address translation information saved in the address translation information save area 62 into the address translation cache 11, the address translation cache 11 is rebuilt to the state immediately before the supervisor call (S65). This completes the supervisor call and resumes execution of the original process (S66).

FIG. 10 shows an example of the configuration of a virtual storage electronic computer to which a cache control method according to yet another embodiment of the present invention is applied, and the same reference numerals as in FIGS. 2 and 6 indicate the same parts.

The embodiment shown in FIG. 10 controls both the main memory access cache 10 and the address translation cache 11, and when switching processes, the operations shown in FIGS. 3 and 7 are performed in parallel. At the time of an interrupt, the operations shown in FIGS. 4 and 8 are performed in parallel, and when the supervisor is called, the operations shown in FIGS. 5 and 9 are performed in parallel.

Although the present invention has been described above with reference to several embodiments, the present invention is not limited to the above embodiments, and various other additions and changes are possible. For example, when an event occurs, the main memory access cache 10 and address translation cache 11 are always saved and loaded, but if valid cache management information and address translation information to be loaded do not yet exist, exceptionally , it is also possible to perform only the save and omit the load process.

[0048]

[Effects of the Invention] As explained above, in the cache control method of the present invention, events such as process switching, interrupts, and supervisor calls, which are expected to cause sudden changes in the memory space accessed by the central processing unit, When an event occurs, the contents of caches such as the main memory access cache and address translation cache before the occurrence of the event are saved to a save area in preparation for later use, and the cache contents to be used after the event are cached from the save area. Since the cache is rebuilt by loading the data into the cache, it is possible to increase the hit rate of the cache immediately after an event occurs, making it possible to speed up the operation.

[Brief explanation of the drawing]

FIG. 1 is a diagram showing a configuration example of the present invention.

FIG. 2 is a configuration diagram of an electronic computer to which a cache control method according to an embodiment of the present invention is applied.

FIG. 3 is a diagram illustrating an example of processing when a process switch occurs.

FIG. 4 is a diagram illustrating an example of processing when an interrupt occurs.

FIG. 5 is a diagram illustrating an example of processing when a supervisor call occurs.

FIG. 6 is a configuration diagram of an electronic computer to which a cache control method according to another embodiment of the present invention is applied.

FIG. 7 is a diagram illustrating another example of processing when a process switch occurs.

FIG. 8 is a diagram showing another example of processing when an interrupt occurs.

FIG. 9 is a diagram showing another example of processing when a supervisor call occurs.

FIG. 10 is a configuration diagram of an electronic computer to which a cache control method according to yet another embodiment of the present invention is applied.

[Explanation of symbols]

10...Main memory access cache 11...Address translation cache 20...Cache management information updating means 21...Address translation cache updating means 30...Cache management information saving means 31...Address translation cache saving means 40...Cache management information loading means 41...Address Conversion cache loading means 51 to 53...
Cache management information save areas 61 to 63...Address conversion information save area 71...Process switching means 72...Interrupt processing means 73...Supervisor call processing means 100...Central processing unit 200...Main storage device 201...System space 202, 203...Process specific space

Claims (6)

[Claims] 1. In an electronic computer having a cache whose contents are updated by an updating means, it is predicted that a save area where the contents of the cache are saved and a memory space accessed by a central processing unit will change rapidly. The present invention is characterized by comprising a save means for saving the contents of the cache before the occurrence of the event to the save area, and a loading means for loading the cache contents to be used after the occurrence of the event from the save area to the cache. A cache control method that uses 2. The cache is a main memory access cache that holds a copy of the contents of the main memory,
2. The cache control system according to claim 1, wherein the updating means is a cache management information updating means for updating the cache management information of the main memory access cache according to a predetermined algorithm every time the main memory is accessed. 3. The cache control method according to claim 2, wherein at least one of process switching, interrupt, and supervisor call is handled as the event. 4. The cache is an address translation cache used for translation from a virtual address to a real address, and the updating means updates the address translation cache based on a predetermined algorithm each time translation from a virtual address to a real address is performed. 2. The cache control system according to claim 1, further comprising address translation cache updating means for updating address translation information in said address translation cache. 5. The cache control method according to claim 4, wherein at least one of process switching, interrupt, and supervisor call is handled as the event. 6. A main memory access cache that holds a copy of the contents of the main memory, and cache management information of the main memory access cache that is updated according to a predetermined algorithm each time the main memory is accessed. a cache management information update means; an address translation cache used for translation from a virtual address to a real address; and address translation information in the address translation cache according to a predetermined algorithm every time a translation from a virtual address to a real address is performed. In a virtual memory electronic computer having an address translation cache updating means for updating, a cache management information save area in which cache management information of the main memory access cache is saved, and an address translation information in the address translation cache is saved. an address translation information save area that is to be accessed, and cache management information of the main memory access cache before the occurrence of an event in which the memory space accessed by the central processing unit is predicted to change rapidly, in the cache management information save area. cache management information saving means for evacuating; and cache management information loading means for loading cache management information of a main memory access cache to be used after the occurrence of the event from the cache management information save area into the main memory access cache; address translation cache saving means for saving address translation information of the address translation cache before the occurrence of the event into the address translation information save area; and cache management information of the address translation cache to be used after the occurrence of the event is saved to the address translation cache; A cache control method comprising: address translation cache loading means for loading translation information from a translation information save area into the address translation cache.