JPH0652058A - Address converter - Google Patents

Abstract

PURPOSE:To save memory resources since it is not required to hold a process number in a supervisor address conversion buffer in a converter from a virtual address to a real address in a computer in which a virtual memory system is employed. CONSTITUTION:The supervisor address conversion buffer 11 is equipped with plural address conversion entries including a virtual address part and a real address part, and a user address conversion buffer 12 is equipped with the plural address conversion entries consisting of a virtual address part, a process number part, and a real address part. An address conversion buffer control part 13 performs such control to output an address conversion result from either of the address conversion buffers according to the operating mode of a processor in address conversion.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an address conversion device for converting a virtual address from a processor into a real address to a memory in a computer adopting a virtual memory system.

[0002]

2. Description of the Related Art In recent years, a virtual memory system has been adopted in many computers, and these computers have an address conversion device inside the processor or as an auxiliary device of the processor. Adopting the virtual memory method relieves the physical restrictions (memory space restrictions) on the program significantly by providing a large amount of virtual memory, but on the other hand, from the virtual address specified by the program to the actual address on the memory. Need to be converted to.

Most computers adopting the virtual memory system are provided with an address translation device including an address translation buffer for storing a pair of a virtual address and a real address which have recently been used. The address translation buffer uses a content addressable memory,
By performing address comparison in parallel, the processing time for address conversion is reduced to the extent that it does not affect the operation of the program. (For example, "Information Processing" Vol. 32, No. 12, 12
Pages 30-1238. In addition, many computers are provided with a supervisor mode in which the operating system operates and a user mode in which the user program operates so that the general user program does not destroy the operating system or other user programs.

In the user mode, the address translator identifies the user program by the process number and translates the virtual address to the real address for each individual process. This protects other user programs. In the supervisor mode, the address translation device translates addresses without being aware of the process number. If a user mode program tries to access the memory space dedicated to supervisor mode,
The address translator generates a privilege violation exception signal (or interrupt signal). This protects the operating system.

An example of the above-mentioned conventional address translation device will be described below with reference to the drawings. FIG. 5 is a diagram showing the configuration of a conventional address translation device. In FIG. 5, reference numeral 51 is an address translation buffer, and 52 is an output unit. FIG. 6 shows the structure of the address translation entry stored in the address translation buffer 51. 61 is a valid bit,
A value of 1 indicates that the address translation entry is valid, and a value of 0 indicates that it is invalid. Reference numeral 62 is a virtual address portion, 63 is a process number portion, 64 is a supervisor portion, and 1 indicates a supervisor mode address translation entry, and 0 indicates a user mode address translation entry. Reference numeral 65 is a real address part.

The operation of the address translation device configured as described above will be described in the order of (1) operation of writing an address translation entry in the address translation buffer and (2) address translation operation. (1) Operation to write an address translation entry in the address translation buffer If the desired address translation entry does not exist in the address translation buffer during normal instruction address translation, the address translation device issues an address translation buffer miss exception to the operating system. Occurrence is reported.
The operating system searches the address translation table provided in the main memory and then writes the address translation entry into the address translation buffer as follows.

In writing the address translation entry, the operating system inputs the virtual address, the process number, the supervisor bit, and the real address into the address translation buffer 51. Here, the supervisor bit is 1 and the supervisor mode address is 0.
Indicates that the address is for user mode. In the address translation buffer 51, if there is an address translation entry whose valid bit 61 is 0 among the address translation entries, the address translation entry is determined in advance, and if it does not exist, it is determined in advance from among the FIFO algorithm, the LRU algorithm, the random algorithm or the like. Select the address translation entry to replace according to the algorithm provided. 1 is set in the valid bit 61 for the selected address translation entry,
A virtual address, a process number, a supervisor bit and a real address given by the operating system are written in the process number section 63, the supervisor section 64 and the real address section 65, respectively.

(2) Address Translation Operation Next, the translation operation from a virtual address such as an instruction address during normal instruction execution or an operand address of a memory access instruction to a real address will be described. First, the processor inputs the virtual address and the process number into the address translation buffer 51.

In the address translation buffer 51, among the address translation entries in the buffer whose effective bit 61 is 1, the virtual address given from the processor is compared with the virtual address portion 62, and the supervisor portion 64 In the address translation entry whose value is 0, the process number given by the processor and the process number section 63 are compared in parallel in each address translation entry. As a result of the comparison, there is an address translation entry in which the valid bit 61 is 1, the value of the supervisor section 64 is 1, and the value of the virtual address section 62 matches the virtual address given by the processor, or the valid bit 61 is Is 1 and the value of the supervisor section 64 is 0
Then, if there is an address translation entry in which the value of the virtual address part 62 matches the virtual address given by the processor and the value of the process number part 63 matches the process number given by the processor, it becomes a valid real address. The output unit 5 outputs the real address portion 65 of the address translation entry that matches the signal indicating that the translation has been completed (hereinafter referred to as a hit).
Output to 2. On the contrary, if there is no matching address translation entry, a signal indicating that the real address cannot be translated (hereinafter referred to as a mistake) is output to the output unit 52. In the output unit 52, when the state of the processor is in the user mode but the address translation entry in which the value of the supervisor unit 64 is 1 is hit, a privilege violation exception is generated. In other cases, the output of the address conversion buffer 51, which is a signal indicating hit or miss, and the real address in the case of hit are output.

[0010]

However, the above-mentioned configuration has a problem in that the memory resource is wasted because the process number portion which is unnecessary in the address translation entry of the supervisor mode is also used. Further, since the process numbers are not compared in the supervisor mode but the process numbers are compared in the user mode, there is a problem that a bit for distinguishing between the supervisor mode and the user mode is required for each address translation entry.

Further, in successive address conversions in the same process in the user mode, since process numbers that would otherwise be unnecessary are compared every time, it is determined that both process numbers and virtual addresses match. However, there is a problem that there is an overhead (dead time) that is required. In view of the above problems, it is an object of the present invention to provide an address translation device which does not waste memory resources and has a small overhead.

[0012]

In order to solve the above-mentioned problems, the address translation device of the present invention comprises an address translation buffer for storing translation information necessary for translation from a virtual address to a real address. An address translation device that translates a virtual address from a processor having two or more operation modes different from each other into a real address, and stores a plurality of address translation entries including a real address corresponding to the virtual address as the translation information. Of the address translation buffer and a control unit for switching the address translation buffer used for translation based on a mode signal indicating which mode is input from the processor,
The address translation buffer is provided for each different operation mode.

Of the two or more operation modes, one may be a supervisor mode and at least one may be a user mode. Further, in a virtual storage system computer in which a plurality of processes can operate, an address translation device that translates a virtual address into a real address according to a process number, and a real address corresponding to the virtual address is provided for each process number. It is provided with a plurality of address translation buffers to be stored and a control unit for switching the address translation buffers used for translation based on the process number.

The control unit may be configured to switch to a corresponding address translation buffer prior to address translation based on a process switching signal and a process number given by the processor that indicate switching of processes.

[0015]

According to the present invention, each address translation buffer is provided according to the difference in the translation information for each mode by the above-mentioned means, and the control unit controls the switching of the address translation buffer used for translation according to the mode signal. Also,
Each address translation buffer is provided for each process number, and the control unit controls to switch the address translation buffer used for translation according to the process number input from the processor.

[0016]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT An address translator according to an embodiment of the present invention will be described with reference to the drawings. FIG. 1 is a block diagram of an address translator according to an embodiment of the present invention. Reference numeral 11 denotes a supervisor address translation buffer, which holds a plurality of address translation entries composed of real addresses corresponding to virtual addresses in the supervisor mode.

Reference numeral 12 is a user address translation buffer, which holds a plurality of address translation entries consisting of virtual addresses, process numbers and corresponding real addresses in the user mode. An address translation buffer control unit 13 controls address translation and writing of an address translation entry into the address translation buffer according to a processor operation mode signal and a supervisor mode signal provided from the processor. Specifically, in address translation, in accordance with the processor operation mode signal, in the supervisor mode, the virtual address is translated by the supervisor address translation buffer into the virtual address, and in the user mode, the virtual address is translated by the user address translation buffer in the user address translation buffer. . Here, the processor operation mode signal is a signal indicating whether the operation mode of the processor is the supervisor mode or the user mode. When writing the address translation entry, the address translation entry is written in the supervisor address translation buffer for the supervisor address translation entry or in the user address translation buffer for the user mode in accordance with the supervisor mode signal. Here, the supervisor mode signal is a signal indicating whether the address translation entry given from the processor is for the supervisor or for the user.

An input unit 14 receives a virtual address, a process number, and a real address from the processor when writing an address translation entry, and inputs a virtual address, a process number, and the like during normal address translation. 15
Is an output unit that outputs a real address as a result of address translation, a signal indicating that an address translation entry does not exist, and a signal indicating a privilege violation exception.

FIG. 2A shows the structure of the address translation entry held in the supervisor address translation buffer 11. Reference numeral 21 is a valid bit, and 1 indicates that the address translation entry is valid, and 0 indicates that it is invalid. Reference numeral 22 is a virtual address portion, which is a (logical) address in the virtual storage device specified by the program. Reference numeral 23 is a real address part, which is a (physical) address in a real memory.

FIG. 2B shows the structure of the address translation entry held in the user address translation buffer 12.
24 is a valid bit, which is the same as the valid bit 21, 25 is a virtual address part, which is similar to the virtual address part 22, and 27 is a real address part, which is similar to the real address part 23. Reference numeral 26 is a process number section, which indicates the number of a process in the user mode.

The operation of the address translation device configured as described above will be described in the order of (1.1) operation of writing an address translation entry into the address translation buffer and (1.2) address translation operation. (1.1) Write operation of address translation entry to address translation buffer Write to address translation buffer is performed by operating system when desired address translation entry does not exist in address translation buffer in normal address translation. . The operating system outputs the processor operation mode, the supervisor mode, the virtual address, the process number in the case of the user mode, and the real address to the address translator as in the conventional example. The address translation buffer control unit 13 selects the supervisor address translation buffer 11 in the supervisor mode and the user address translation buffer 12 in the user mode according to the supervisor bit given from the operating system.

When the supervisor address translation buffer 11 is selected, the supervisor address translation buffer 1
1 selects the address translation entry to be replaced according to the FIFO algorithm, the LRU algorithm, the random algorithm or the like if the address translation entry having the valid bit 21 of 0 exists if it does not exist.

When the user address translation buffer 12 is selected, the user address translation buffer 12 refers to the valid bit 24 and selects the address translation entry to be replaced in the same manner as in the case of the supervisor address translation buffer 11. Then, the address translation buffer control unit 13 controls the input unit 14 by outputting the supervisor bit given from the operating system to the input unit 14. When the supervisor bit is in the supervisor mode, the input unit 14 sets the valid bit 21 of the selected address translation entry in the supervisor address translation buffer 11 to 1, and the virtual address unit 22 and the real address unit 23 to the operating system, respectively. Write the virtual address and the real address given by. When the supervisor bit is in the user mode, 1 is set in the valid bit 24 of the address translation entry selected in the user address translation buffer 12.
The virtual address, process number and real address given by the operating system are written in the virtual address part 25, the process number part 26 and the real address part 27, respectively.

(1.2) Address Translation Operation Next, the translation operation from a virtual address such as an instruction address during normal instruction execution or an operand address of a memory access instruction to a real address will be described. First, the processor inputs the virtual address and the process number into the input unit 14. The input unit 14 outputs a virtual address to the supervisor address translation buffer 11 and a virtual address and a process number to the user address translation buffer 12, respectively.

In the supervisor address translation buffer 11, the address translation entry whose valid bit 21 is 1 among the address translation entries in the buffer is the target, and the virtual address given from the input unit 14 and the virtual address unit 22 are used for each address. The translation entries are compared in parallel, and if there is a matching address translation entry, the real address part 23 of the address translation entry that matches the signal indicating a hit is output to the output part 15. If there is no matching address translation entry, a signal indicating a miss is output to the output unit 15.

At the same time, the user address translation buffer 12
Then, among the address translation entries in the buffer, the address translation entry whose effective bit 24 is 1 is targeted,
The virtual address and the virtual address portion 25 given from the input unit 14 are compared in parallel with the process number and the process number portion 26 given from the input unit 14 in each address translation entry. If there is an address translation entry that also matches the virtual address and the process number, the real address unit 27 of the address translation entry that matches the signal indicating a hit is output to the output unit 15. If there is no address translation entry in which both the virtual address and the process number match, a signal indicating a miss is output to the output unit 15.

The address translation buffer control unit 13 controls the output unit 15 by outputting to the output unit 15 whether the operation mode of the processor is the supervisor mode or the user mode. The output unit 15 determines either the output from the supervisor address translation buffer 11 or the output from the user address translation buffer 12 as the final address translation result according to the processor operation mode given from the address translation buffer control unit 13. Output.

If there is a matching address translation entry in the supervisor address translation buffer 11, if the processor operation mode output from the address translation buffer control unit 13 is the supervisor mode, a signal indicating a hit is given. The real address output from the supervisor address translation buffer 11 is output, and when the processor operation mode is the user mode, a signal indicating a privilege violation exception is output.

If there is no matching address translation entry in the supervisor address translation buffer 11 and there is a matching address translation entry in the user address translation buffer 12, it is a hit regardless of the processor operation mode. And a real address output from the user address conversion buffer 12 are output.

When there is no matching address translation entry in both the supervisor address translation buffer 11 and the user address translation buffer 12, a signal indicating a miss is output. As described above, according to the present embodiment, the supervisor address translation buffer and the user address translation buffer including the address translation buffer for performing the user address translation are provided, the address translation is performed in parallel, and the supervisor provided to the operating system is provided. An address translation buffer control unit is provided that controls writing of address translation according to the bits and controls output of the address translation result according to the processor operation mode. As a result, it is not necessary to have a bit for distinguishing between the supervisor mode and the user mode for each address translation entry, and it is also unnecessary to hold an unnecessary process number in the supervisor address translation buffer.

A second embodiment of the present invention will be described below with reference to the drawings. FIG. 3 is a block diagram of an address translation device showing a second embodiment of the present invention. In FIG.
Reference numeral 31 is a supervisor address translation buffer, 32 is a process address translation buffer, 33 is an address translation buffer control unit, 34 is an input unit, and 35 is an output unit.
The configuration is the same as that of. The difference from FIG. 1 is that a plurality of process address conversion buffers 32 are provided as user address conversion buffers, a user address conversion buffer management unit 36 for managing these, and a process number unit 37 for each process address conversion buffer 32. That is the point.

FIG. 4 shows the structure of the address translation entry stored in the supervisor address translation buffer 31 and the process address translation buffer 32 according to the second embodiment of the present invention. 41 is a valid bit and 42 is a virtual bit. The address part and 43 are real address parts. The address translation device configured as described above will be described below with reference to FIGS.
The following describes the operations in the order of (2.1) operation of user address translation buffer management unit, (2.2) operation of writing address translation entry to address translation buffer, and (2.3) address translation operation.

(2.1) Operation of User Address Translation Buffer Management Unit First, the operation of the user address translation buffer management unit 36 will be described. User address translation buffer management unit 3
6 indicates whether each of a plurality of process address translation buffers 32 is valid and which process address translation buffer 32 is used for the current address translation (hereinafter referred to as the current process address translation buffer). Manage. If the process address translation buffer 32 is valid, it means that it can be used.
Invalid means that it cannot be used. For example, when a process terminates, the process address translation buffer for that process becomes invalid. Further, the current process address conversion buffer is only one process address conversion buffer 32, and is changed in synchronization with the change of the process number of the processor. That is, it is rewritten according to the process switching signal and the process number notified from the processor when switching the process.

User address translation buffer management unit 36
Compares the process number portion 37 of each valid process address conversion buffer 32 with the process number given by the processor, and if there is a match, selects the matched process address conversion buffer 32 and selects it. The process address translation buffer 32 is stored as the current process address translation buffer. If there is no valid process address translation buffer 32 with the same process number and there is an invalid process address translation buffer 32, one invalid process address translation buffer 32 is selected by some method, and the selected process address The translation buffer 32 is stored as the current process address translation buffer, the selected user address translation buffer is enabled, and the process number portion 37 stores the process number given by the processor. Also,
If there is no valid process address translation buffer 32 with the same process number and there is no invalid process address translation buffer 32, the FIFO algorithm, the LRU algorithm, the random algorithm, or the like is preliminarily selected from all user address translation buffers. According to a predetermined algorithm, one process address translation buffer 32 is selected, the selected process address translation buffer 32 is stored as the current process address translation buffer, and the process number given by the processor is stored in the process number section 37. The valid bit 41 of all the address translation entries stored in the selected process address translation buffer 32 is set to 0.

(2.2) Write Operation of Address Translation Entry to Address Translation Buffer Next, writing of the address translation entry to the address translation buffer will be described. The operation is different from that of the first embodiment in that the process address translation buffer 32 is selected when the supervisor bit provided by the operating system is in the user mode, and the address translation entry of the selected user address translation buffer is changed. It is writing. When the supervisor bit is in the user mode, the address translation buffer control unit 33 selects the current process address translation buffer 32 stored in the user address translation buffer management unit 36. The selected process address translation buffer 32 selects one address translation entry in the same manner as in the first embodiment, and the input unit 34 sets 1 in the valid bit 41 of the selected address translation entry and the virtual address unit. 42 and real address part 43
In, the virtual address and the real address given by the operating system are written respectively. The operation of writing the address translation entry to the address translation buffer other than the operation described above is the same as that of the first embodiment.

(2.3) Address Translation Operation Finally, the translation operation from the virtual address of the instruction address during the normal instruction execution and the operand address of the memory access instruction to the real address will be described. That action is first
Unlike the above embodiment, the input unit 34 outputs virtual addresses to the current process address conversion buffer 32 stored in the supervisor address conversion buffer 31 and the user address conversion buffer management unit 36, respectively. The search operation of the address translation entry in the current process address translation buffer 32 and the output operation to the output unit 35 are the same as the operation of the address translation entry in the supervisor address translation buffer 11 of the first embodiment, and the valid bit 41 Targeting the address translation entry whose value is 1
The comparison is performed by comparing the virtual address given from No. 4 with the virtual address portion 42. Others, the search operation of the address translation entry in the supervisor address translation buffer 31 and the output operation to the output unit 35, the control operation to the output unit 35 of the address translation buffer control unit 33, and the output operation of the address translation result of the output unit 35. Is the same as in the first embodiment.

As described above, by providing a plurality of user address translation buffers having the process number portion and providing the user address translation buffer management portion for managing the user address translation buffer corresponding to the process number of the processor, the user address translation buffer is provided. It is not necessary to provide the process number part in the address translation entry of the buffer. Also, by switching the current process address translation buffer when switching processes, there is no need to compare process numbers when translating addresses, so processing that determines whether both the process number and virtual address match is unnecessary. The dead time can be reduced.

In the first and second embodiments, the contents of the real address parts 23, 27 and 43 are used as real memory addresses. However, in addition to the real memory addresses, the memory attributes used for access control etc. Including, output section 15 and 3
Further detailed access control may be performed in step 5.

[0039]

As described above, according to the present invention, by providing the supervisor address translation buffer, the user address translation buffer, and the address translation buffer control unit, the supervisor address translation buffer is provided for each address translation entry. It is not necessary to hold an unnecessary process number, and it is not necessary to have a bit for distinguishing between the supervisor mode and the user mode, which has an effect of reducing waste of memory resources.

By providing a plurality of process address conversion buffers having a process number section and a user address conversion buffer management section, it becomes unnecessary to hold the process number in each address conversion entry of the user address conversion buffer. This has an effect of reducing waste of memory resources. Furthermore, by switching the process address conversion buffer in advance when switching processes, it is not necessary to compare process numbers during address conversion, so processing for determining that both the process number and virtual address match is not required. This has the effect of reducing overhead (dead time).

[Brief description of drawings]

FIG. 1 is a configuration diagram of an address translation device according to a first embodiment of the present invention.

FIG. 2A is a configuration diagram of an address translation entry of a supervisor address translation buffer in the embodiment. FIG. 7B is a configuration diagram of an address translation entry of the user address translation buffer in the embodiment.

FIG. 3 is a configuration diagram of an address translation device according to a second embodiment of the present invention.

FIG. 4 is a configuration diagram of an address translation entry in the embodiment.

FIG. 5 is a configuration diagram of a conventional address translation device.

FIG. 6 is a configuration diagram of a conventional address translation entry.

[Explanation of symbols]

 11 supervisor address conversion buffer 12 user address conversion buffer 13 address conversion buffer control unit 14 input unit 15 output unit 21 valid bit 22 virtual address unit 23 real address unit 24 valid bit 25 virtual address unit 26 process number unit 27 real address unit 31 supervisor Address translation buffer 32 Process address translation buffer 33 Address translation buffer control unit 34 Input unit 35 Output unit 36 User address translation buffer management unit 37 Process number unit 41 Effective bit 42 Virtual address unit 43 Real address unit

Claims (4)

[Claims] 1. An address translation buffer for storing translation information necessary for translation from a virtual address to a real address, wherein a virtual address from a processor having two or more operation modes in which the configurations of the translation information are different from each other is implemented. An address translation device for translating an address, showing a plurality of address translation buffers that store an address translation entry including a real address corresponding to a virtual address as the translation information, and which mode is input from a processor An address translation device, comprising: a control unit that switches an address translation buffer used for translation based on a mode signal, wherein the address translation buffer is provided for each different operation mode. 2. The address translation device according to claim 1, wherein, of the two or more operation modes, one is a supervisor mode and at least one is a user mode. 3. An address translation device for translating a virtual address into a real address according to a process number in a virtual storage system computer in which a plurality of processes can operate, each process number corresponding to a virtual address. An address translation device comprising: a plurality of address translation buffers that store real addresses; and a control unit that switches an address translation buffer used for translation based on a process number. 4. The control unit is configured to switch to a corresponding address translation buffer prior to address translation based on a process switching signal and a process number which indicate switching of a process given from a processor. The address translation device according to claim 3.