JPH07262004A - Processor - Google Patents

Abstract

PURPOSE:To move data at a high speed while applying an instruction sequence composed of a store instruction and a load instruction, to the move of data from a first storage means of a first arithmetic means to a second storage means of a second arithmetic means on the same chip. CONSTITUTION:When executing the store instruction to store the data in a register inside a register file 13 to a main memory 2, a virtual address showing the store destination is set to a slot inside an address/size holding part 14 corresponding to the register by an integral arithmetic unit 12. In the case of decoding the load instruction to load the data from the main memory to a register file 16, when there is any valid slot inside the address/size holding part 14 to which the virtual address showing the load destination designated by the load instruction is set, the data in the register inside the register file 13 corresponding to the slot are transferred to the designated register in the register file 16 by a data transfer unit 17.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention comprises a first arithmetic means having a first arithmetic function and a second arithmetic means having a second arithmetic function which the first arithmetic means does not have. More specifically, the present invention relates to a processor incorporated in a chip, and more particularly, for moving data from a first storage means for a first arithmetic means to a second storage means for a second arithmetic means, The present invention relates to a processor that applies an instruction sequence of storing in a memory and loading from the memory into a second storage unit.

[0002]

2. Description of the Related Art In recent processors, in addition to an integer arithmetic unit (first arithmetic means having a first arithmetic function), a floating point arithmetic function (second Some include a coprocessor (second arithmetic means) having an arithmetic function.

This type of processor stores a general-purpose register file (first storage means) for integer arithmetic, which holds data used for arithmetic operations performed by the integer arithmetic unit, and data used for arithmetic operations performed by the coprocessor. And a coprocessor general-purpose register file (second storage means) for holding.

In order to use the data in the general-purpose register file for integer arithmetic in floating-point arithmetic and the like by the coprocessor, it is necessary to move the data to the coprocessor general-purpose register file.

Conventionally, in order to move data from the general-purpose register file for integer arithmetic to the general-purpose register file for coprocessor, the general-purpose register file for integer arithmetic is stored in the main memory and the main-memory is stored in the coprocessor general-purpose register file. It was necessary to execute the load instruction sequence.

[0006]

SUMMARY OF THE INVENTION As described above, the first
In a conventional processor having an arithmetic means (first arithmetic means) having the arithmetic function (1), and an arithmetic means (second arithmetic means) not having the first arithmetic means, To move data from the first storage means for the first arithmetic means to the second storage means for the second arithmetic means, a store from the first storage means to the main memory and a transfer from the main memory to the main memory are performed. It was necessary to faithfully execute the instruction sequence of loading into the second storage means.

However, since it takes time to access the main memory, there is a problem that the data cannot be moved from the first storage means to the second storage means at high speed. In particular, while the store from the first storage unit to the main memory is being waited for due to a cache miss or the like, subsequent loading from the main memory to the second storage unit cannot be executed.
There is a problem that the data movement from the first storage means to the second storage means is further delayed.

The present invention has been made in view of the above circumstances, and an object thereof is an arithmetic means having a first arithmetic function (first arithmetic function).
Storage means and load instruction for data movement from the first storage means for the second calculation means) to the second storage means for the second calculation means having the second calculation function on the same chip. To provide a processor capable of high-speed data movement by setting information at the time of executing a store instruction in a storage unit (third storage unit) and applying the information at the time of a load instruction while applying the following instruction sequence. is there.

Another object of the present invention is to provide a processor which requires only a small capacity of storage means for setting information when executing a store instruction. Still another object of the present invention is to effectively use the storage means for temporarily storing the data to be stored, so that the first storage means can be transferred to the second storage means without providing any special storage means. It is to provide a processor capable of speeding up data movement.

[0010]

Means and Actions for Solving the Problems
A store instruction for data movement from the first storage means for the first calculation means having the first calculation function to the second storage means for the second calculation means having the second calculation function on the same chip. In a processor to which an instruction sequence consisting of a load instruction and a load instruction is applied, third storage means having storage areas corresponding to the respective storage areas of the first storage means and target data are stored when the store instruction is executed. An information setting means for setting information including address information indicating a store destination in the third storage means internal storage area corresponding to the first storage means internal storage area, and the first storage means to the second storage means A data transfer means for directly transferring data to the third storage means and a valid storage area in which the address information indicating the load source is stored by referring to the third storage means when the load instruction is decoded. If present, instead of executing the load instruction, the data stored in the storage area in the first storage means corresponding to the storage area is designated by the data transfer means by the second load instruction. Data transfer control means for transferring to a storage area in the storage means are provided.

In the above structure, when the store instruction in the instruction sequence for moving the data from the first storage means to the second storage means is executed, the target data is stored in the first storage means. Information including address information indicating a store destination is set by the information setting means in the storage area in the third storage means corresponding to the area.

On the other hand, when the load instruction in the above instruction sequence is decoded, the transfer control means refers to the inside of the third storage means, and an effective storage area in which the address information indicating the load source is stored. If so, the data transfer means is activated instead of executing the load instruction. The data transfer means extracts data from the first storage means internal storage area corresponding to the third storage means internal storage area in which the address information indicating the load source is stored. This data matches the target data of the load instruction. Then, the data transfer means transfers this data to the storage area in the second storage means designated by the load instruction.

As described above, while applying the instruction sequence consisting of the store instruction and the load instruction for the data movement from the first storage means to the second storage means, the third storage means is stored in the third storage means when the store instruction is executed. By using the set information, the data to be loaded into the second storage means can be taken out from the first storage means rather than from the external memory, so that the first storage means to the second storage means. Data can be moved at high speed.

In the above arrangement, the third storage means needs to have the same number of storage areas as the first storage means, but the number of storage areas in the third storage means is set to the first storage area. It is also possible to make it smaller than the storage area in the storage means. However, in this case, the information setting means selects one storage area in the third storage means at the time of executing the store instruction, and the storage area stores the target data as well as the address information indicating the store destination. It is necessary to set information including pointer information that points to the first storage area in the first storage means.
On the other hand, the data transfer control means executes the load instruction if the third storage means has an effective storage area in which the address information indicating the load source is stored when the load instruction is decoded. Instead of this, the data stored in the storage area in the first storage means pointed to by the pointer information stored in the storage area is stored in the storage area in the second storage means designated by the load instruction by the data transfer means. Need to transfer.

Further, although the above-mentioned third storage means is newly provided, address information indicating the data to be stored and the storage destination (for efficient store operation from the processor to the external memory). It is also possible to use the storage means for temporarily storing the as the third storage means. However, in this case, the data transfer control means refers to the inside of the third storage means when the load instruction is decoded, and if there is an effective storage area in which the address information indicating the load source is stored, Instead of executing the load instruction, it is necessary to transfer the data stored in the storage area to the second storage area in the second storage means designated by the load instruction by the data transfer means.

[0016]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment in which the present invention is applied to a virtual memory control type information processing apparatus will be described below with reference to the drawings. [First Embodiment] FIG. 1 is a block diagram of an information processing apparatus showing a first embodiment of the present invention.

The information processing apparatus of FIG. 1 mainly includes a processor 1 for executing various instructions, a main memory 2 for storing an instruction group executed by the processor 1, data, and the like.
It comprises a processor 1 and a memory bus 3 to which the main memory 2 and the like are connected. In addition to the processor 1, the main memory 2 is directly accessed through the memory bus 3, for example, LS.
A device (not shown) as a means for utilizing the I-shaped main memory is connected. Each device connected to the memory bus 3 exchanges information with the main memory 2 via the memory bus 3.

The processor 1 includes an address conversion / data transfer unit 11, an integer operation unit 12, an integer operation general purpose register file 13, an address / size holding unit 14, a coprocessor unit 15, a coprocessor general purpose register file 16 and a data transfer unit. 17 is built in the same chip.

The address conversion / data transfer unit 11 is provided between the memory bus 3 and the integer arithmetic unit 12 and fetches an instruction or data from the main memory 2 in accordance with a read request for the instruction or data from the integer arithmetic unit 12. Has a data transfer function. The address conversion / data transfer unit 11 also has a data transfer function of storing data in the main memory 2 in response to a data write request from the integer arithmetic unit 12. Address conversion / data transfer unit 1
1 further has an address conversion function for converting a virtual address into a physical address for data transfer with the main memory 2.

The integer arithmetic unit 12 has an address conversion
It is an arithmetic unit having a standard arithmetic function (here, an integer arithmetic function) for decoding and executing the instruction fetched by the data transfer unit 11.

When the decoded instruction is a coprocessor instruction to be operated by the coprocessor unit 15, the integer arithmetic unit 12 sends the instruction to the coprocessor unit 15.

When the decoded instruction is a store instruction for storing the data of the register in the general-purpose register file 13 for integer arithmetic in the main memory 2, the integer arithmetic unit 12 performs the operation instructed by the instruction, Information including the data is also registered in the corresponding slot of the address / size storage unit 14.

If the decoded instruction is a load instruction for loading data from the main memory 2 to the coprocessor general-purpose register file 16, the integer arithmetic unit 12 further checks the address / size holding unit 14 to check the address / size. If the target data is held in the size holding unit 14, the data transfer unit 17 transfers the data from the address / size holding unit 14 to the coprocessor general-purpose register file 16.

Further, the integer arithmetic unit 12 is adapted to put the corresponding slot of the address / size holding unit 14 into an invalid state when rewriting the register in the general-purpose register file 13 for integer arithmetic due to the execution of an instruction.

The general-purpose register file 13 for integer arithmetic is
It is a storage unit including a group of registers used for holding data used for the arithmetic operation performed by the integer arithmetic unit 12. The address / size holding unit 14 is a storage unit for holding the virtual address and size of the data held in each register in the general-purpose register file 13 for integer arithmetic. This address / size holding unit 14 is shown in FIG.
As shown in (a), it has a slot (storage area) corresponding to each register of the general-purpose integer register file 13.

Each slot in the address / size storage unit 14 comprises a virtual address field 141, a size field 142 and a valid field 143, as shown in FIG. 2 (b).

The virtual address field 141 is for setting the virtual address of the data held in the corresponding register in the integer general purpose register file 13, and the size field 142 is for setting the size of the data. It is for doing. The valid field 143 is for setting a valid flag (valid / invalid information) indicating whether or not the information of the corresponding slot is valid (valid).

The coprocessor unit 15 is an arithmetic means having an arithmetic function which the integer arithmetic unit 12 does not have, for example, a floating point arithmetic function. Coprocessor unit 15
Receives the coprocessor instruction decoded by the integer arithmetic unit 12 from the unit 12 and executes the coprocessor instruction.

Coprocessor general purpose register file 16
Is a storage means composed of a register group used to hold data used for the calculation performed by the coprocessor unit 15.

The data transfer unit 17 has a data transfer function for transferring data from the integer general purpose register 13 to the coprocessor general purpose register file 16 in accordance with the data transfer request from the integer arithmetic unit 12.

Next, the operation of the first embodiment of the present invention will be described with reference to the flow charts of FIGS. 3 and 4. First, it is assumed that the address translation / data transfer unit 11 fetches an instruction from the main memory 2 and sends it to the integer arithmetic unit 12.

The integer arithmetic unit 12 is for address conversion
The instruction sent from the data transfer unit 11 is decoded (step S1). If this decoded instruction transfers the data in the register in the general-purpose register file 13 for integer arithmetic to the main memory 2
In the case of a store instruction for storing in, the integer arithmetic unit 12 performs the processing described below.

First, the integer operation unit 12 stores the data held in the register in the general-purpose register file 13 for integer operation designated by the store instruction in the main memory 2 by the address conversion / data transfer unit 11. The original operation instructed by the store instruction is performed (step S2).

That is, the integer arithmetic unit 12 requests the address conversion / data transfer unit 11 to write to the main memory 2, and at the same time, specifies the virtual address designated by the store instruction (indicating the store destination) and the store instruction. The data held in the register in the general-purpose register file 13 for integer arithmetic is passed. As a result, the address translation / data transfer unit 11 translates the virtual address (indicating the store destination) passed from the integer arithmetic unit 12 into a physical address (real address), and an area in the main memory 2 indicated by the physical address. A write access for writing the data passed from the integer arithmetic unit 12 is performed via the memory bus 3.

Further, the integer arithmetic unit 12 obtains the slot in the address / size storage unit 14 corresponding to the register in the general-purpose register file 13 for integer arithmetic designated by the store instruction (step S3).

The integer operation unit 12 uses the valid field 1 of the obtained slot in the address / size storage unit 14.
43 (the valid flag thereof) is set to the valid display state, the virtual address designated by the store instruction is set in the virtual address field 141 of the slot, and the size of the data designated by the store instruction is set in the size field 142 of the slot. Yes (step S4).

Next, the integer arithmetic unit 12 determines the address
The virtual address fields 141 of all other slots in the size holding unit 14 are checked, and if they match the virtual address specified by the store instruction, the valid field 143 (valid flag of the slot) is set to the invalid display state. (Steps S5 and S6).

Next, a case will be described in which the instruction decoded by the integer arithmetic unit 12 is an instruction that involves rewriting the register in the integer general purpose register file 13.
In this case, the integer arithmetic unit 12 performs the original operation instructed by the instruction (step S7), and also the valid field of the slot in the address / size holding unit 14 corresponding to the register in the general-purpose register file 13 for rewriting. 143 (the valid flag thereof) is set to the invalid display state (step S8).

Next, a case where the instruction decoded by the integer arithmetic unit 12 is a load instruction for loading data from the main memory 2 to the register in the general-purpose register file 13 for integer arithmetic will be described.

In this case, first, the integer arithmetic unit 12
Valid field 1 in address / size storage unit 14
A slot in which 43 is in the valid display state is searched for (step S9).

Next, the integer arithmetic unit 12 checks whether or not the contents of the virtual address field 141 of the searched slot match the virtual address designated by the load instruction (indicating the load source) (step S10). .

If there is a slot in the address / size storage unit 14 that has a virtual address field 141 that matches the virtual address specified by the load instruction (there is one slot at most due to the operations of steps S4 to S6 when the store instruction is executed). If the contents of the size field 142 of the slot match the size (of the data to be loaded) specified by the load instruction (step S).
11), the integer arithmetic unit 12 does not perform the original operation instructed by the load instruction. In this case, the integer arithmetic unit 12 uses the coprocessor specified by the load instruction (as the load destination) from the register in the integer arithmetic general purpose register file 13 corresponding to the slot in the address size holding unit 14 in which the virtual address matches. Data transfer to the registers in the general-purpose register file 16 is performed by the data transfer unit 17 (step S12).

Data transferred in step S12, that is, virtual address and size (data size)
The data held in the register in the general-purpose integer register file 13 for the integer operation corresponding to the slot in the address / size holding unit 14 in which is matched is stored in the area in the main memory 2 designated by the virtual address and size of the load instruction ( It matches the data that is originally stored (or should be stored if the store operation is not completed) according to the instruction of the previous store instruction). Therefore, instead of the data loading operation from the main memory 2 to the register in the coprocessor general-purpose register file 13 instructed by the load instruction, the data held in the slot in the address / size holding unit 14 that matches this data is replaced by the data transfer unit By transferring to the register in the coprocessor general-purpose register file 16 by 17, high-speed transfer becomes possible.

On the other hand, is there a slot in the address / size storage unit 14 having a virtual address field 141 that matches the virtual address specified by the load instruction?
Alternatively, even if there is, if the content of the size field 142 of the slot does not match the size specified by the load instruction, the integer arithmetic unit 12 determines that the main memory 2
The address translation / data transfer unit 11 performs the original operation instructed by the load instruction to load the data stored in the register into the register in the coprocessor general-purpose register file 16 via the coprocessor unit 15 (step S13). .

In the flowcharts of FIGS. 3 and 4, the above store instruction (store instruction for storing the data in the register in the integer arithmetic general purpose register file 13 in the main memory 2), the integer arithmetic general purpose register file 1
3 instructions involving rewriting of internal registers, and load instructions (from the main memory 2 to the general-purpose register file 13 for integer arithmetic)
The operation procedure for instructions other than the load instruction for loading data into the inner register) is omitted because it is not directly related to the present invention.

By the way, depending on the system, the general-purpose register file 13 for integer arithmetic may be controlled by the register window method. In the register window method, the register group forming the general-purpose register file 13 for integer arithmetic is managed by being divided into a plurality of groups (register windows), and in terms of software, only the register groups in one group (register window) among them are managed. It is invisible (cannot handle). Therefore,
In the integer arithmetic general-purpose register file 13 controlled by the register window method, when an instruction for switching the register window is executed, the integer arithmetic general-purpose register file 1 constituting the register window before the switching is executed.
The register group in 3 does not match the register group in the general-purpose register file 13 for integer operation which constitutes the register window after switching.

Therefore, when the general-purpose register file 13 for integer arithmetic is controlled by the register window system, the integer arithmetic unit 12 receives all the general-purpose register files for integer arithmetic when the instruction to switch the register windows is executed. Valid field 1 of address / size storage unit 14 slot corresponding to register 13
43 is set to the invalid display state. By doing so, erroneous data (due to the switching of the register window) is generated in the address / size storage unit 1 at the time of the load instruction.
Coprocessor general-purpose register file 1 from slot 4
6 can be prevented.

The relationship between the virtual address and the physical address is not generally fixed, and even the same virtual address may have different physical addresses before and after the process switching. This is because the conversion map for converting a virtual address into a physical address is rewritten (by the operating system or the like). When such rewriting is performed, the subroutine is always called or the subroutine returns.

Therefore, in this embodiment, the integer arithmetic unit 1
2 is when the instruction to call the subroutine is executed,
Alternatively, when an instruction returning from a subroutine is executed, as in the case of executing the above-mentioned instruction for switching the register window, a valid field of a slot in the address / size holding unit 14 corresponding to all registers in the general-purpose register file 13 for integer arithmetic. 143 is set to the invalid display state. This prevents erroneous data from being transferred from the slot in the address / size storage unit 14 to the coprocessor general-purpose register file 16 (due to the switching of the virtual address-physical address conversion map) at the time of the load instruction. it can.

Although the above description is applied to the information processing apparatus of the virtual memory control method, when the virtual memory control method is not applied, the invalid operation at the time of the above subroutine call is unnecessary. .

If the size of the data handled by the load instruction and the store instruction is fixed, the size field 142 of the slot in the address / size holding unit 14 is unnecessary, and the processing of step S11 is also unnecessary. [Second Embodiment] In the first embodiment described above, it is necessary that the number of slots in the address / size storage unit (14) is equal to the number of registers in the general-purpose register file for integer operation (13). It was Therefore, a second embodiment in which the number of slots in the address / size storage unit is less than the number of registers in the general-purpose register file for integer calculation will be described with reference to the drawings.

FIG. 5 is a block diagram of the information processing apparatus showing the second embodiment of the present invention. The information processing apparatus in FIG. 5 includes a processor 4, a main memory 5 and a memory bus 6, which correspond to the processor 1, the main memory 2 and the memory bus 3 in the first embodiment, respectively.

The processor 4 is made into one chip like the processor 1 in the first embodiment, and the address conversion / data transfer unit 11 of the processor 1 is provided.
An address conversion / data transfer unit 41 and an integer corresponding respectively to the integer operation unit 12, integer operation general-purpose register file 13, address / size holding unit 14, coprocessor unit 15, coprocessor general-purpose register file 16 and data transfer unit 17. Arithmetic unit 42,
It has an integer arithmetic general-purpose register file 43, an address / size storage unit 44, a coprocessor unit 45, a coprocessor general-purpose register file 46, and a data transfer unit 47.

As described above, the configuration of the processor 4 is almost the same as that of the processor 1 in the first embodiment. Therefore, only the difference in the configuration of the processor 4 from the processor 1 will be described.

The processor 4 of this embodiment differs most from the processor 1 of the first embodiment in the structure of the address / size storage unit 44. Ie address
As shown in FIG. 6A, the size holding unit 44 has slots of n stages (m and n are positive integers), which are smaller than the total number m of registers of the general-purpose register file 43 for integer arithmetic. On the other hand, the address / size storage unit 14 on the processor 1 in the first embodiment, as shown in FIG.
Total number of registers in general-purpose register file 13 for integer arithmetic m
It has an m-stage slot corresponding to.

As described above, each slot in the address size holding unit 44 has a one-to-one correspondence with each register in the general-purpose register file 43 for integer arithmetic (unlike the address size holding unit 14 in the first embodiment). Does not correspond to.
Therefore, as shown in FIG. 6B, the virtual address field 141 and the size field 142 of the slot in the address / size holding unit 14 in the first embodiment are stored in each slot in the address / size holding unit 44. And a virtual address field 441 (corresponding to the valid field 143), a size field 442, and a valid field 443, as well as a register pointer field 444 pointing to a corresponding register in the general-purpose register file 43 for integer arithmetic.

Since the structure of the address size holding unit 44 is different from that of the address size holding unit 14 in the first embodiment, the operation of the integer arithmetic unit 42 also differs from that of the integer arithmetic unit 12 in the first embodiment. A little different. This will be described in detail in the operation description.

Next, the operation of the second embodiment of the present invention will be described with reference to the flowcharts of FIGS. 7 and 8. First, it is assumed that the address translation / data transfer unit 41 fetches an instruction from the main memory 5 and sends it to the integer arithmetic unit 42.

The integer arithmetic unit 42 is for address conversion
The instruction sent from the data transfer unit 41 is decoded (step S21). If the decoded instruction is a store instruction for storing the data in the register in the general-purpose integer register file 43 in the main memory 5, the integer arithmetic unit 42 performs the processing described below.

First, the integer arithmetic unit 42 stores the data held in the register in the integer general purpose register file 43 designated by the store instruction in the main memory 5 by the address conversion / data transfer unit 41. The original operation instructed by the store instruction is performed (step S22). In this case, the store operation by the address conversion / data transfer unit 41 is performed by converting the virtual address designated by the store instruction into a physical address and using the physical address to write-access the main memory 5.

Further, the integer arithmetic unit 42 selects a slot in the address / size holding unit 44 to be associated with the register in the general-purpose register file 43 for integer arithmetic designated by the store instruction (step S23). As this slot selection method, any method such as a random method of randomly selecting a slot or an LRU (Least Recently Used) method of selecting the most recently used slot can be applied.

The integer arithmetic unit 42 puts the valid field 443 (valid flag thereof) of the slot in the selected address / size storage unit 44 into the valid display state,
The virtual address field 441 of the slot specifies the virtual address specified by the store instruction, the size field 442 of the slot specifies the size of the data specified by the store instruction, and the register pointer field 444 of the slot specifies the store instruction. A pointer (register pointer) that points to a register in the general-purpose register file 43 for integer calculation is set (step S2).
4).

Next, the integer arithmetic unit 42 outputs the address
The virtual address fields 441 of all other slots in the size holding unit 44 are checked, and if they match the virtual address specified by the store instruction, the valid field 443 (valid flag of) of that slot is set to the invalid display state. (Steps S25 and S26).

Next, a case will be described in which the instruction decoded by the integer arithmetic unit 42 is an instruction that involves rewriting the register in the integer general purpose register file 43.
In this case, the integer arithmetic unit 42 performs the original operation instructed by the instruction (step S27), and
Register pointer fields 44 of all slots (or all valid slots) in size holder 14
4 is checked, and if there is a slot pointing to the register to be rewritten, the valid field 443 of that slot
(Valid flag of) is set to the invalid display state (step S28).

In addition, the integer arithmetic unit 42, as in the integer arithmetic unit 12 in the first embodiment, has the following conditions (a), (b) and (c): The valid fields (valid flags) of all the slots in the address / size storage unit 14 are set to the invalid display state.

(A) General-purpose register file 4 for integer arithmetic
When 3 is controlled by the register window method,
When an instruction to switch the register window is executed (b) When an instruction to call a subroutine is executed (c) When an instruction to return from the subroutine is executed Next, the instruction decoded by the integer arithmetic unit 42 is the main memory. A case of a load instruction for loading data from 5 to a register in the coprocessor general-purpose register file 46 will be described.

In this case, first, the integer arithmetic unit 42
Valid field 4 in address / size storage 44
A slot in which 43 is in the valid display state is searched for (step S29).

Next, the integer arithmetic unit 42 checks whether or not the contents of the virtual address field 441 of the searched slot match the virtual address designated by the load instruction (step S30).

If there is a slot in the address / size storage unit 44 having a virtual address field 441 that matches the virtual address specified by the load instruction (by the operations of steps S24 to S26 when the store instruction is executed,
If the contents of the size field 442 of the slot match the size specified by the load instruction (step S31), the integer arithmetic unit 42 performs the original operation instructed by the load instruction. Not performed. In this case, the integer arithmetic unit 42 uses the integer arithmetic general purpose register file 43 indicated by the contents (register pointer) of the register pointer field 444 of the slot in the address size holding unit 14 in which the virtual addresses match.
From the internal register with the relevant load instruction (as the load destination)
Data transfer to the designated register in the coprocessor general-purpose register file 16 is performed by the data transfer unit 47 (step S32).

On the other hand, is there a slot in the address / size storage unit 44 having a virtual address field 441 that matches the virtual address specified by the load instruction?
Alternatively, even if there is, if the content of the size field 442 of the slot does not match the size specified by the load instruction, the integer operation unit 42 determines that the main memory 5
The address translation / data transfer unit 41 performs the original operation instructed by the load instruction to load the data stored in the register into the register in the coprocessor general-purpose register file 46 via the coprocessor unit 45 (step S33). . [Third Embodiment] In the first and second embodiments described above, it is necessary to provide a new storage means called the address / size holding unit (14, 44). By the way, there is known a processor having a store buffer for temporarily storing data to be stored and virtual address information indicating a store destination for an efficient store operation to a main memory. Therefore, this store buffer is stored in the first and second storage buffers.
A third embodiment adapted to be used as a storage means instead of the address / size holding unit in the above embodiment (however, the data structure of the slot in the store buffer is different) will be described with reference to the drawings.

FIG. 9 is a block diagram of the information processing apparatus showing the third embodiment of the present invention. The information processing apparatus shown in FIG. 9 includes a processor 7, a main memory 8 and a memory bus 9, which respectively correspond to the processor 1, the main memory 2 and the memory bus 3 in the first embodiment.

The processor 7 includes an address conversion / data transfer unit 71, an integer operation unit 72, an integer operation general purpose register file 73, a store buffer 74, a coprocessor unit 75, and a coprocessor general purpose register file 76.
And the data transfer unit 77 is built in the same chip.

The address conversion / data transfer unit 71 is provided between the memory bus 9 and the integer arithmetic unit 72, and fetches an instruction or data from the main memory 8 in accordance with an instruction or data read request from the integer arithmetic unit 72. Has a data transfer function. The address conversion / data transfer unit 71 also has a data transfer function of storing data in the main memory 8 in accordance with a data write request from the integer arithmetic unit 72. Address conversion / data transfer unit 7
1 further has an address conversion function for converting a virtual address into a physical address for data transfer with the main memory 8.

The integer arithmetic unit 72 has an address conversion
It is an arithmetic unit having a standard arithmetic function (integer arithmetic function here) for decoding and executing the instruction fetched by the data transfer unit 71.

When the decoded instruction is a coprocessor instruction to be operated by the coprocessor unit 75, the integer arithmetic unit 72 sends the instruction to the coprocessor unit 75.

If the decoded instruction is a store instruction for storing the data in the register in the general-purpose register file 73 for integer arithmetic in the main memory 8, the integer arithmetic unit 72 sends a write request to the main memory 8, The virtual address designated by the store instruction (indicating the store destination) and the data held in the register in the general-purpose register file for integer operation 73 designated by the store instruction are passed to the address conversion / data transfer unit 71 to be transferred to the main memory. A store operation to 8 is performed.

If the decoded instruction is a load instruction for loading data from the main memory 8 to the coprocessor general-purpose register file 76, the integer operation unit 72 further checks the store buffer 74 and checks the store buffer 7 concerned.
4 holds the target data, the data transfer unit 77 stores the target data in the store buffer 74.
To the coprocessor general-purpose register file 76.

When rewriting the register in the general-purpose register file 73 for integer arithmetic with the execution of the instruction, the integer arithmetic unit 72 further stores the store buffer 7 indicating the register.
If there are four internal slots, that slot is also set to the invalid state.

The general-purpose register file 73 for integer arithmetic is
It is a data storage means including a group of registers used to hold data used for the arithmetic operation performed by the integer arithmetic unit 72.

The store buffer 74 is a storage means for holding information including data stored in the main memory 8 by the address conversion / data transfer unit 71. As shown in FIG. 10A, the store buffer 74 has p stages (p is a positive integer) of slots # 1, # 2, # 3, ... #p.
Has -1, #p.

Each slot in the store buffer 74 is composed of a data field 741, a virtual address field 742, a physical address field 743, a size field 744, a register pointer field 745 and a valid field 746, as shown in FIG. 10B. .

The data field 741 is for setting the data stored in the main memory 8. The virtual address field 742 is the data field 7
The physical address field 743 is for setting a virtual address indicating the storage destination of the data set in 41, and the physical address field 743 is for setting the physical address corresponding to the virtual address. The size field 744 is for setting the size of the data set in the data field 741, and the register pointer field 745 is a pointer that points to a register in the general-purpose register file 73 for integer arithmetic in which the data is held. This is for setting (register pointer). The valid field 746 is for setting a valid flag (valid / invalid information) indicating whether or not the information of the corresponding slot is valid (valid).

The coprocessor unit 75 is an arithmetic means having an arithmetic function which the integer arithmetic unit 72 does not have, for example, a floating point arithmetic function. Coprocessor unit 75
Receives the coprocessor instruction decoded by the integer arithmetic unit 72 from the unit 72 and executes it.

Coprocessor general-purpose register file 76
Is a data storage means composed of a register group used for holding data used for the calculation performed by the coprocessor unit 75.

The data transfer unit 77 has a data transfer function of transferring data from the store buffer 74 to the general-purpose register file 76 in accordance with the data transfer request from the integer arithmetic unit 72.

Next, the operation of the third embodiment of the present invention will be described with reference to the flow charts of FIGS. 11 and 12. First, the address translation / data transfer unit 71 fetches an instruction from the main memory 8, and the integer operation unit 7
Suppose it was sent to 2.

The integer arithmetic unit 72 is for address conversion
The instruction sent from the data transfer unit 71 is decoded (step S41). If the decoded instruction is a store instruction for storing the data of the register in the general-purpose integer register file 73 in the main memory 8, the integer arithmetic unit 72 instructs the address conversion / data transfer unit 71 to Along with the write request to the main memory 8, the virtual address designated by the store instruction (indicating the store destination) and the data held in the register in the general-purpose register file for integer operation 73 designated by the store instruction are passed. Is stored in the main memory 8 via the store buffer 74 as described below (step S42).

The address translation / data transfer unit 71 translates the virtual address (indicating the store destination) passed from the unit 72 into a physical address (real address) in response to a write request from the integer operation unit 72. Then, the address translation / data transfer unit 71 sets the valid field 746 (valid flag of the slot) of the slot in the store buffer 74 pointed to by a write pointer (not shown) to the valid display state, and passes it from the integer arithmetic unit 72 to the data field 741 of the slot. The virtual address passed from the integer arithmetic unit 72 to the virtual address field 742 of the slot, the physical address obtained by the address conversion to the physical address field 743 of the slot, and the size field 744 of the slot to The size of the data is set in the register pointer field 745 of the slot, and the pointers pointing to the registers in the general-purpose register file for integer operation 73 in which the data is held are set. At this time, the write pointer is updated to point to the next slot.

The address conversion / data transfer unit 71 refers to the first slot # 1 of the store buffer 74 when the memory bus 9 is empty, and if the valid field 746 of the slot is in the valid display state, the slot concerned. A write access for storing the data set in the data field 741 of the slot is performed via the memory bus 9 in the area in the main memory 2 indicated by the physical address set in the physical address field 743 of the above.

As a result of this store operation, the store buffer 7
When the first slot # 1 of No. 4 becomes empty, the address translation / data transfer unit 71 sets the valid field 746 of the slot # 1 to the invalid display state, and then the slot # 2.
Content of slot # 1 is copied to slot # 1, the content of slot # 3 is copied to slot # 2, and so on. Similarly, the content of slot #p is copied to slot # p-1.

If a structure is provided in which a read pointer pointing to the slot in the store buffer 74 is provided and the data held in (the data field 741 of) the slot pointed to by the read pointer is stored in the main memory 8, The copy operation is unnecessary, and it suffices to update the read pointer to point to the next slot after the store operation.

Next, a case will be described in which the instruction decoded by the integer arithmetic unit 72 is an instruction that involves rewriting the registers in the integer general purpose register file 73.
In this case, the integer arithmetic unit 72 performs the original operation instructed by the instruction (step S43), and also checks the register pointer fields 745 of all slots (or all valid slots) of the store buffer 74,
If there is a slot pointing to the register to be rewritten, the valid field 746 (valid flag of the slot) of that slot is set to the invalid display state (step S44).

Besides, in the same way as the integer arithmetic unit 12 in the first embodiment, the integer arithmetic unit 72, when at least one of the following (a), (b) and (c) is satisfied, The valid fields 746 (valid flags thereof) of all the slots in the store buffer 74 are set to the invalid display state.

(A) General-purpose register file 7 for integer arithmetic
When 3 is controlled by the register window method,
When an instruction to switch the register window is executed (b) When an instruction to call a subroutine is executed (c) When an instruction to return from the subroutine is executed Next, the instruction decoded by the integer arithmetic unit 72 is the main memory. A case of a load instruction for loading data from 8 to a register in the general-purpose register file for integer operation 73 will be described.

In this case, first, the integer arithmetic unit 72
A slot in which the valid field 746 is in the valid display state is searched for in the store buffer 74 (step S45).

Next, the integer arithmetic unit 72 checks whether or not the contents of the virtual address field 742 of the searched slot match the virtual address designated by the load instruction (step S46).

If there is a slot in the store buffer 74 having a virtual address field 742 that matches the virtual address specified by the load instruction (only one at most matches), and the size field 744 of that slot.
If the contents of the number match the size specified by the load instruction (step S47), the integer operation unit 72 does not perform the original operation instructed by the load instruction. In this case, the integer calculation unit 72 (the data field 7 of the slot in the store buffer 74 in which the virtual address matches)
41), the data transfer unit 77 causes the data transfer unit 77 to transfer the data to the register in the coprocessor general-purpose register file 76 designated by the load instruction (as the load destination) (step S48).

On the other hand, there is no slot in the store buffer 74 having the virtual address field 742 that matches the virtual address specified by the load instruction, or if there is, there is a size field 744 of that slot.
If the contents of the above do not match the size specified by the load instruction, the integer operation unit 72 causes the address conversion / data transfer unit 71 to transfer the data stored in the main memory 8 via the coprocessor unit 75 to the coprocessor general-purpose unit. The original operation instructed by the load instruction is performed to load the register in the register file 76 (step S49).

[0099]

As described above in detail, according to the present invention,
A store instruction for data movement from the first storage means for the first calculation means having the first calculation function to the second storage means for the second calculation means having the second calculation function on the same chip. In the processor to which the instruction sequence including the load instruction and the load instruction is applied, the third storage unit having the storage regions corresponding to the respective storage regions of the first storage unit is provided, and the target data is stored when the store instruction is executed. Information including address information indicating the store destination is set in the third storage unit internal storage area corresponding to the first storage unit internal storage area, and the third storage unit is set when the load instruction is decoded. If there is a valid storage area in which the address information indicating the load source is stored, the first storage section in the first storage means corresponding to the storage area instead of executing the load instruction. With the configuration in which the stored data is transferred to the storage area in the second storage means designated by the load instruction, the store instruction and the storage instruction for moving the data from the first storage means to the second storage means are stored. Since the data to be loaded into the second storage means can be taken out from the first storage means instead of from the external memory while applying the instruction sequence including the load instruction, the second storage from the first storage means Data can be moved to the means at high speed.

Further, according to the present invention, pointer information indicating a storage area in the first storage means in which not only address information indicating a store destination but also target data is stored in the storage area in the third storage means. If the effective storage area in which the address information indicating the load source is stored in the third storage means when the load instruction is decoded, Instead of executing the load instruction, the data stored in the storage area in the first storage means pointed to by the pointer information stored in the storage area is transferred to the second storage means. The number of storage areas of the third storage means can be made smaller than the number of storage areas of the first storage means.

Further, according to the present invention, the storage means for temporarily holding the data to be stored and the address information indicating the storage destination for the efficient storage operation from the processor to the external memory is provided as the third storage. If a valid storage area in which the address information indicating the load source is stored when the load instruction is decoded is used as a means, instead of executing the load instruction. By configuring the data stored in the storage area to be transferred to the storage area in the second storage means, it is possible to transfer data from the first storage means to the second storage means without providing a special storage means. It is possible to speed up data movement.

[Brief description of drawings]

FIG. 1 is a block configuration diagram of an information processing apparatus showing a first embodiment of the present invention.

2 is a diagram showing the relationship between the slots in the address / size storage unit 14 and the registers in the general-purpose register file 13 for integer arithmetic in FIG. 1, and the data structure of the slots in the address / size storage unit 14;

FIG. 3 is a diagram showing a part of a flowchart for explaining the operation of the first embodiment.

FIG. 4 is a diagram showing the rest of the flowchart for explaining the operation of the first embodiment.

FIG. 5 is a block configuration diagram of an information processing apparatus showing a second embodiment of the present invention.

6 is a diagram showing the relationship between the slots in the address / size storage unit 44 and the registers in the general-purpose integer register file 43 in FIG. 5, and the data structure of the slots in the address / size storage unit 44.

FIG. 7 is a diagram showing a part of a flowchart for explaining the operation of the second embodiment.

FIG. 8 is a view showing the rest of the flowchart for explaining the operation of the second embodiment.

FIG. 9 is a block configuration diagram of an information processing apparatus showing a third embodiment of the present invention.

10 is a diagram showing a structure of a store buffer 74 in FIG. 9 and a data structure of a slot in the store buffer 74. FIG.

FIG. 11 is a diagram showing a part of a flowchart for explaining the operation of the third embodiment.

FIG. 12 is a diagram showing the rest of the flowchart for explaining the operation of the third embodiment.

[Explanation of symbols]

1 ... Processor, 2 ... Main memory, 3 ... Memory bus, 11
... address conversion / data transfer section, 12 ... integer operation unit (first operation means, information setting means, data transfer control means), 13 ... integer operation general purpose register file (first operation means)
Storage unit), 14 ... Address / size holding unit (third storage unit), 15 ... Coprocessor unit (second operation unit), 16 ... Coprocessor general-purpose register file (second storage unit), 17 ... Data transfer unit (data transfer means), 4 ... Processor, 5 ... Main memory, 6 ... Memory bus, 41 ... Address conversion / data transfer section, 42 ... Integer operation unit (first operation means, information setting means, data transfer) Control unit), 43 ... General-purpose register file for integer calculation (first storage unit), 44 ... Address / size storage unit (third storage unit), 45 ... Coprocessor unit (second calculation unit), 46 ... Coprocessor general-purpose register file (second storage means), 47 ... Data transfer unit (data transfer means), 7 ... Processor, 8 ... Main memory, 9 ... Memory bus, DESCRIPTION OF SYMBOLS 1 ... Address conversion / data transfer section (information setting means, store means), 72 ... Integer operation unit (first operation means, information setting means, data transfer control means), 73 ... General purpose register file for integer operation (first) Storage means), 74 ... Store buffer (third storage means), 75 ... Coprocessor unit (second arithmetic means), 76 ... Coprocessor general-purpose register file (second)
Storage means), 77 ... Data transfer unit (data transfer means).

Claims (8)

[Claims] 1. A first arithmetic means having a first arithmetic function, a first storage means for holding data used for arithmetic operation performed by the first arithmetic means, and the first arithmetic means. A second arithmetic means having a second arithmetic function which is not present and a second storage means for holding data used for arithmetic operation performed by the second arithmetic means are built in the same chip; When moving data from one storage means to the second storage means, a store instruction for instructing data storage from the first storage means to a memory outside the chip and from the memory to the second storage means In a processor to which an instruction sequence including a load instruction for instructing data loading is applied, a storage area corresponding to each storage area of the first storage means, in which information including address information is set, A third storage unit having the third storage unit, and the third storage unit corresponding to the storage area in the first storage unit in which target data is stored when the store instruction is executed.
An information setting means for setting information including address information indicating a store destination in a storage area in the storage means; a data transfer means for directly transferring data from the first storage means to the second storage means; When the load instruction is decoded, the inside of the third storage means is referred to, and if there is an effective storage area in which the address information indicating the load source is stored, then the execution of the load instruction is executed instead of the execution of the load instruction. Data transfer control means for causing the data transfer means to transfer the data stored in the first storage means internal storage area corresponding to the storage area to the second storage means internal storage area specified by the load instruction. A processor provided with. 2. The information set in each storage area of the third storage means includes valid / invalid information indicating whether or not the content of the storage area is valid, and the information set. The means also sets valid / invalid information indicating that the content of the storage area is valid when the information is set in the storage area in the third storage means, and the third storage means Among the other storage areas in the storage area, the valid / invalid information of the storage area in which the address information matching the address information indicating the store destination specified by the store instruction is set is set to the invalid display state, and the first storage is performed. 7. When executing an instruction that involves rewriting the contents of the storage area in the storage means, the valid / invalid information of the storage area in the third storage means corresponding to the storage area is set to an invalid display state. 1 professional Sessa. 3. A first arithmetic means having a first arithmetic function, a first storage means for holding data used in an arithmetic operation performed by the first arithmetic means, and the first arithmetic means. A second arithmetic means having a second arithmetic function which is not present and a second storage means for holding data used for arithmetic operation performed by the second arithmetic means are built in the same chip; When moving data from one storage means to the second storage means, a store instruction for instructing data storage from the first storage means to a memory outside the chip and from the memory to the second storage means In a processor to which an instruction sequence consisting of a load instruction for instructing data loading is applied, the number of storage areas is smaller than the storage area in the first storage means, and refers to address information and the storage area in the first storage means. Third storage means having a plurality of storage areas in which information including pointer information is set, and when executing the store instruction, one storage area in the third storage means is selected and set to the storage area. , Information setting means for setting information including address information indicating a store destination and pointer information pointing to a storage area in the first storage means in which target data is stored, and the first storage means to the second storage means. There is a data transfer means for directly transferring data to the storage means, and a valid storage area in which the address information indicating the load source is stored by referring to the inside of the third storage means when the load instruction is decoded. If so, instead of executing the load instruction, the data stored in the storage area in the first storage means pointed to by the pointer information stored in the storage area is replaced with the data. Processor, characterized by comprising the data transfer control means for transferring the to the storage area the second storage means for designating of the load instruction by the feeding means. 4. The information set in each storage area of the third storage means includes valid / invalid information indicating whether or not the content of the storage area is valid, and the information set. The means also sets valid / invalid information indicating that the content of the storage area is valid when the information is set in the storage area in the third storage means, and the third storage means Among the other storage areas in the storage area, the valid / invalid information of the storage area in which the address information matching the address information indicating the store destination specified by the store instruction is set is set to the invalid display state, and the first storage is performed. At the time of executing an instruction that involves rewriting the contents of the storage area in the means, of all the storage areas in the third storage means,
4. The processor according to claim 3, wherein the valid / invalid information of the storage area in which the pointer information that points to the rewritable first storage means storage area is set to the invalid display state. 5. A first arithmetic means having a first arithmetic function, a first storage means for holding data used for arithmetic operation performed by the first arithmetic means, and the first arithmetic means. A second arithmetic means having a second arithmetic function which is not present and a second storage means for holding data used for arithmetic operation performed by the second arithmetic means are built in the same chip; When moving data from one storage means to the second storage means, a store instruction for instructing data storage from the first storage means to a memory outside the chip and from the memory to the second storage means In a processor to which an instruction sequence including a load instruction for instructing data loading is applied, the processor has a plurality of storage areas in which information including address information indicating data to be stored in the memory and a storage destination is set. And a third storage unit for executing the store instruction, the information including the address information indicating the data stored in the first storage unit internal storage area designated by the store instruction Information setting means to be set in a storage area in the third storage means, data transfer means for directly transferring data from the third storage means to the second storage means, and storage in the third storage means Reference is made to store means for storing the data stored in the area in the memory designated by the address information stored in the storage area, and inside the third storage means when the load instruction is decoded. If there is a valid storage area in which address information indicating the load source is stored, the data stored in that storage area is replaced with the data in place of the execution of the load instruction. Data transfer control means for causing the data transfer means to transfer to the storage area in the second storage means specified by the load instruction. 6. The information set in each storage area of the third storage means includes valid / invalid information indicating whether or not the contents of the storage area are valid, and the storage area. Pointer information indicating a storage area in the first storage unit in which data is stored is included, and the information setting unit specifies the first storage specified by the store instruction for executing the store instruction. Valid / invalid indicating that the contents of the storage area is valid when the address information indicating the data stored in the internal storage area and the store destination is set in the third internal storage area.
Invalid information and pointer information pointing to the storage area in the first storage means designated by the store instruction are set together, and at the time of execution of the instruction accompanied by rewriting of the contents of the storage area in the first storage means, 6. The valid / invalid information of the storage area, in which the pointer information pointing to the rewritable storage area is set among all the storage areas in the storage means No. 3, is set to the invalid display state. Processor. 7. A processor to which a method in which a storage area group in the first storage means is managed by being divided into a plurality of groups, and only the storage area in one of the groups can be processed is applied. The information setting means sets the valid / invalid information of all the storage areas in the third storage means to an invalid display state at the time of executing the instruction to switch the group to be processed. Claim 2, Claim 4 or Claim 6
Processor described in. 8. The information setting means displays the valid / invalid information of all storage areas in the third storage means in an invalid display state at the time of executing an instruction for calling a subroutine or an instruction for returning from a subroutine. The processor according to claim 2, claim 4, claim 6, or claim 7.